Futher NAND development

This commit is contained in:
Gregory Nutt 2013-11-16 13:19:09 -06:00
parent 204d351720
commit 28a1a5e428
3 changed files with 79 additions and 2 deletions

View File

@ -3195,6 +3195,29 @@ config SAMA5_EBICS3_NAND
endchoice # CS3 Memory Type
endif # SAMA5_EBICS3
if SAMA5_EBICS0_NAND || SAMA5_EBICS1_NAND || SAMA5_EBICS2_NAND || SAMA5_EBICS3_NAND
config SAMA5_NAND_READYBUSY
bool "NAND Ready/Busy"
default n
---help---
Board logic supports and interface to detect NAND Busy/Ready signal.
If defined, the board must provide:
bool board_nand_busy(int cs);
config SAMA5_NAND_CE
bool "NAND Chip Enable"
default n
---help---
Board logic supports and interface to control the NAND Chip Enable signal.
If defined, the board must provide:
void board_nand_ce(int cs, bool enable);
endif # SAMA5_EBICS0_NAND
endmenu # External Memory Configuration
choice

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@ -80,6 +80,9 @@ struct nand_dev_s
{
struct mtd_dev_s mtd; /* Externally visible part of the driver */
uint8_t cs; /* Chip select number (0..3) */
uintptr_t cmdaddr; /* NAND command address base */
uintptr_t addraddr; /* NAND address address base */
uintptr_t dataaddr; /* NAND data address */
};
/****************************************************************************
@ -260,6 +263,10 @@ static int nand_ioctl(struct mtd_dev_s *dev, int cmd, unsigned long arg)
* be bound to other functions (such as a block or character driver front
* end).
*
* This MTD devices implements a RAW NAND interface: No ECC or sparing is
* performed here. Those necessary NAND features are provided by common,
* higher level MTD layers found in drivers/mtd.
*
* Input parameters:
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
@ -362,6 +369,9 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
priv->mtd.bwrite = nand_bwrite;
priv->mtd.ioctl = nand_ioctl;
priv->cs = cs;
priv->cmdaddr = cmdaddr;
priv->addraddr = addraddr;
priv->dataaddr = dataaddr;
/* Initialize the NAND hardware */
/* Perform board-specific SMC intialization for this CS */
@ -376,7 +386,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
/* Probe the NAND part */
ret = nand_initialize(cmdaddr, addraddr, dataaddr);
ret = nand_initialize(&priv->mtd, cmdaddr, addraddr, dataaddr);
if (ret < 0)
{
fdbg("ERROR: CS%d nand_initialize failed: %d at (%p, %p, %p)\n",
@ -389,5 +399,5 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
/* Return the implementation-specific state structure as the MTD device */
return (struct mtd_dev_s *)priv;
return &priv->mtd;
}

View File

@ -112,6 +112,50 @@ struct mtd_dev_s *sam_nand_initialize(int cs);
int board_nandflash_config(int cs);
/****************************************************************************
* Name: board_nand_busy
*
* Description:
* Must be provided if the board logic supports and interface to detect
* NAND Busy/Ready signal.
*
* Input Parameters:
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
*
* Returned Values:
* True: NAND is busy, False: NAND is ready
*
****************************************************************************/
#ifdef CONFIG_SAMA5_NAND_READYBUSY
bool board_nand_busy(int cs);
#endif
/****************************************************************************
* Name: board_nandflash_config
*
* Description:
* Must be provided if the board logic supports and interface to control
* the NAND Chip Enable signal.
*
* Input Parameters:
* cs - Chip select number (in the event that multiple NAND devices
* are connected on-board).
* enable - True: enable Chip Select, False: Disable Chip select
*
* Returned Values:
* OK if the HSMC was successfully configured for this CS. A negated
* errno value is returned on a failure. This would fail with -ENODEV,
* for example, if the board does not support NAND FLASH on the requested
* CS.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_NAND_CE
void board_nand_ce(int cs, bool enable);
#endif
#undef EXTERN
#if defined(__cplusplus)
}