Futher NAND development
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@ -3195,6 +3195,29 @@ config SAMA5_EBICS3_NAND
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endchoice # CS3 Memory Type
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endif # SAMA5_EBICS3
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if SAMA5_EBICS0_NAND || SAMA5_EBICS1_NAND || SAMA5_EBICS2_NAND || SAMA5_EBICS3_NAND
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config SAMA5_NAND_READYBUSY
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bool "NAND Ready/Busy"
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default n
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---help---
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Board logic supports and interface to detect NAND Busy/Ready signal.
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If defined, the board must provide:
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bool board_nand_busy(int cs);
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config SAMA5_NAND_CE
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bool "NAND Chip Enable"
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default n
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---help---
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Board logic supports and interface to control the NAND Chip Enable signal.
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If defined, the board must provide:
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void board_nand_ce(int cs, bool enable);
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endif # SAMA5_EBICS0_NAND
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endmenu # External Memory Configuration
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choice
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@ -80,6 +80,9 @@ struct nand_dev_s
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{
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struct mtd_dev_s mtd; /* Externally visible part of the driver */
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uint8_t cs; /* Chip select number (0..3) */
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uintptr_t cmdaddr; /* NAND command address base */
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uintptr_t addraddr; /* NAND address address base */
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uintptr_t dataaddr; /* NAND data address */
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};
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/****************************************************************************
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@ -260,6 +263,10 @@ static int nand_ioctl(struct mtd_dev_s *dev, int cmd, unsigned long arg)
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* be bound to other functions (such as a block or character driver front
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* end).
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*
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* This MTD devices implements a RAW NAND interface: No ECC or sparing is
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* performed here. Those necessary NAND features are provided by common,
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* higher level MTD layers found in drivers/mtd.
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*
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* Input parameters:
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* cs - Chip select number (in the event that multiple NAND devices
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* are connected on-board).
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@ -362,6 +369,9 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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priv->mtd.bwrite = nand_bwrite;
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priv->mtd.ioctl = nand_ioctl;
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priv->cs = cs;
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priv->cmdaddr = cmdaddr;
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priv->addraddr = addraddr;
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priv->dataaddr = dataaddr;
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/* Initialize the NAND hardware */
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/* Perform board-specific SMC intialization for this CS */
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@ -376,7 +386,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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/* Probe the NAND part */
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ret = nand_initialize(cmdaddr, addraddr, dataaddr);
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ret = nand_initialize(&priv->mtd, cmdaddr, addraddr, dataaddr);
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if (ret < 0)
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{
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fdbg("ERROR: CS%d nand_initialize failed: %d at (%p, %p, %p)\n",
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@ -389,5 +399,5 @@ struct mtd_dev_s *sam_nand_initialize(int cs)
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/* Return the implementation-specific state structure as the MTD device */
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return (struct mtd_dev_s *)priv;
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return &priv->mtd;
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}
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@ -112,6 +112,50 @@ struct mtd_dev_s *sam_nand_initialize(int cs);
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int board_nandflash_config(int cs);
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/****************************************************************************
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* Name: board_nand_busy
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*
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* Description:
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* Must be provided if the board logic supports and interface to detect
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* NAND Busy/Ready signal.
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*
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* Input Parameters:
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* cs - Chip select number (in the event that multiple NAND devices
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* are connected on-board).
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*
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* Returned Values:
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* True: NAND is busy, False: NAND is ready
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_NAND_READYBUSY
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bool board_nand_busy(int cs);
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#endif
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/****************************************************************************
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* Name: board_nandflash_config
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*
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* Description:
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* Must be provided if the board logic supports and interface to control
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* the NAND Chip Enable signal.
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*
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* Input Parameters:
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* cs - Chip select number (in the event that multiple NAND devices
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* are connected on-board).
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* enable - True: enable Chip Select, False: Disable Chip select
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*
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* Returned Values:
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* OK if the HSMC was successfully configured for this CS. A negated
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* errno value is returned on a failure. This would fail with -ENODEV,
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* for example, if the board does not support NAND FLASH on the requested
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* CS.
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*
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****************************************************************************/
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#ifdef CONFIG_SAMA5_NAND_CE
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void board_nand_ce(int cs, bool enable);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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