Xtensa/ESP32: Add CPU1 startup logic
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Gregory Nutt
parent
a8e3f79494
commit
28d1478480
@ -108,6 +108,10 @@
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# define CONFIG_ARCH_INTERRUPTSTACK 0
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#endif
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/* Used for stack usage measurements */
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#define STACK_COLOR 0xdeadbeef
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/* In the XTENSA model, the state is copied from the stack to the TCB, but
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* only a referenced is passed to get the state from the TCB.
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*
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@ -183,12 +183,20 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
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size_t size_of_stack;
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#ifdef CONFIG_STACK_COLORATION
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uint32_t *ptr;
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int i;
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/* Yes.. If stack debug is enabled, then fill the stack with a
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* recognizable value that we can use later to test for high
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* water marks.
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*/
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memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
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for (i = 0, ptr = (uint32_t *)tcb->stack_alloc_ptr;
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i < stack_size;
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i += sizeof(uint32_t))
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{
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*ptr++ = STACK_COLOR;
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}
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#endif
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/* XTENSA uses a push-down stack: the stack grows toward lower
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@ -41,7 +41,8 @@ HEAD_CSRC = esp32_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_vectors.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_user_handlers.S
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CMN_ASRCS += xtensa_vectors.S
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CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
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CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c
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@ -80,7 +81,7 @@ endif
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# Required ESP32 files (arch/xtensa/src/lx6)
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CHIP_ASRCS =
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CHIP_ASRCS = esp32_cpuhead.S
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CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c
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CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c
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CHIP_CSRCS += esp32_start.c esp32_timerisr.c
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139
arch/xtensa/src/esp32/esp32_cpuhead.S
Normal file
139
arch/xtensa/src/esp32/esp32_cpuhead.S
Normal file
@ -0,0 +1,139 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/esp32_cpuhead.S
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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.file "esp32_cpuhead.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Private Data
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****************************************************************************/
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section .noinit, "aw"
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.align 16
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.global g_cpu1_idlestack
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.type g_cpu1_idlestack, @object
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g_cpu1_idlestack:
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.space (CONFIG_SMP_IDLETHREAD_STACKSIZE & ~15)
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.Lcpu1_stacktop:
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.size g_cpu1_idlestack, . - g_cpu1_idlestack
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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.text
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/****************************************************************************
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* Name: __cpu[n]_start
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*
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* Description:
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* Boot functions for each CPU (other than CPU0). These functions set up
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* the ARM operating mode, the initial stack, and configure co-processor
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* registers. At the end of the boot, esp32_cpu_boot() is called.
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*
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* These functions are provided by the common ARMv7-A logic.
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*
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* Input parameters:
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* None
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*
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* Returned Value:
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* Do not return.
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*
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****************************************************************************/
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#if CONFIG_SMP_NCPUS > 1
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.global __cpu1_start
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.type __cpu1_start, #function
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.Lcpu1_bottomofstack:
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long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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#ifdef CONFIG_STACK_COLORATION
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.Lcpu1_bottomofstack:
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long .Lcpu1_stacktop
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.size .Lcpu1_bottomofstack, . - .Lcpu1_bottomofstack
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.Lcpu1_stackcolor:
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long STACK_COLOR
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.size .Lcpu1_stackcolor, . - .Lcpu1_stackcolor
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#endif
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__cpu1_start:
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/* Set up the stack pointer and the CPU index */
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l32r .Lcpu1_bottomofstack
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#ifdef CONFIG_STACK_COLORATION
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/* Write a known value to the IDLE thread stack to support stack
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* monitoring logic
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*/
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mov a0, sp
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l32r a1, .Lcpu1_bottomofstack
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l32r a2, .Lcpu1_stackcolor
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1:
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s32i a2, a1, 0
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addi a2, a2, 4
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bne a1, a2, 1b
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#endif
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/* Set up the intiali PS */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM;
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#else
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
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#endif
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wsr a0, PS
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/* Finish initialization in C */
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movi a2, 1 /* Argument 1: CPU ID */
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call0 xtensa_start_handler
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/* xtensa_start_handler() does not return */
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2: b 2b
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.size __cpu1_start, . - __cpu1_start
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@ -197,6 +197,12 @@ int xtensa_start_handler(int irq, FAR void *context)
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xtensa_registerdump(tcb);
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* And Enable interrupts */
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up_irq_enable();
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#endif
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/* Then switch contexts. This instantiates the exception context of the
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* tcb at the head of the assigned task list. In this case, this should
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* be the CPUs NULL task.
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@ -265,7 +271,7 @@ int up_cpu_start(int cpu)
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/* Set the CPU1 start address */
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ets_set_appcpu_boot_addr((uint32_t)xtensa_start_handler);
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ets_set_appcpu_boot_addr((uint32_t)__cpu1_start);
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/* And way for the initial task to run on CPU1 */
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@ -186,7 +186,6 @@ void xtensa_irq_initialize(void)
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esp32_gpioirqinitialize();
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#endif
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* And finally, enable interrupts */
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