From 291a5755cc662bebe3ec76f1ad729e69d3c4a7c3 Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Mon, 22 Feb 2021 09:35:17 -0300 Subject: [PATCH] risc-v/esp32c3: Add support for MWDT0 and MWDT1 --- arch/risc-v/src/esp32c3/Kconfig | 31 + arch/risc-v/src/esp32c3/Make.defs | 7 + arch/risc-v/src/esp32c3/esp32c3_wdt.c | 923 +++++ arch/risc-v/src/esp32c3/esp32c3_wdt.h | 147 + .../src/esp32c3/esp32c3_wdt_lowerhalf.c | 746 ++++ .../src/esp32c3/esp32c3_wdt_lowerhalf.h | 58 + .../src/esp32c3/hardware/esp32c3_rtccntl.h | 3618 +++++++++++++++++ .../risc-v/src/esp32c3/hardware/esp32c3_tim.h | 529 +++ .../risc-v/esp32c3/esp32c3-devkit/README.txt | 27 + .../esp32c3-devkit/configs/watchdog/defconfig | 48 + .../esp32c3-devkit/configs/watcher/defconfig | 51 + .../esp32c3/esp32c3-devkit/src/Makefile | 4 + .../esp32c3-devkit/src/esp32c3-devkit.h | 18 +- .../esp32c3/esp32c3-devkit/src/esp32c3_boot.c | 9 - .../esp32c3-devkit/src/esp32c3_bringup.c | 12 + .../esp32c3/esp32c3-devkit/src/esp32c3_wdt.c | 94 + 16 files changed, 6311 insertions(+), 11 deletions(-) create mode 100644 arch/risc-v/src/esp32c3/esp32c3_wdt.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_wdt.h create mode 100644 arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c create mode 100644 arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h create mode 100644 boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig create mode 100644 boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig create mode 100644 boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index 950fc374a2..6fc67ab34f 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -104,6 +104,10 @@ config ESP32C3_CPU_FREQ_MHZ menu "ESP32-C3 Peripheral Support" +config ESP32C3_WDT + bool + default n + config ESP32C3_GPIO_IRQ bool "GPIO pin interrupts" ---help--- @@ -119,6 +123,33 @@ config ESP32C3_UART1 default n select UART1_SERIALDRIVER +config ESP32C3_MWDT0 + bool "Main System Watchdog Timer (Group 0)" + default n + select ESP32C3_WDT + ---help--- + Includes MWDT0. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32C3_MWDT1 + bool "Main System Watchdog Timer (Group 1)" + default n + select ESP32C3_WDT + ---help--- + Includes MWDT1. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32C3_RWDT + bool "RTC Watchdog Timer" + default n + select ESP32C3_WDT + ---help--- + Includes RWDT. This watchdog timer is from the RTC module. + When it is selected, if the developer sets it to reset on expiration + it will reset Main System and the RTC module. If you don't want + to have the RTC module reset, please, use the Timers' Module WDTs. + They will only reset Main System. + endmenu endif # ARCH_CHIP_ESP32C3 diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index 09abfcf46f..331db55109 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -53,3 +53,10 @@ CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_idle.c CHIP_CSRCS += esp32c3_irq.c esp32c3_timerisr.c CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c CHIP_CSRCS += esp32c3_serial.c esp32c3_lowputc.c + +ifeq ($(CONFIG_ESP32C3_WDT),y) +CHIP_CSRCS += esp32c3_wdt.c +ifeq ($(CONFIG_WATCHDOG),y) +CHIP_CSRCS += esp32c3_wdt_lowerhalf.c +endif +endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.c b/arch/risc-v/src/esp32c3/esp32c3_wdt.c new file mode 100644 index 0000000000..02aae402f3 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt.c @@ -0,0 +1,923 @@ +/**************************************************************************** + * arch/riscv/src/esp32c3/esp32c3_wdt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_rtccntl.h" +#include "hardware/esp32c3_tim.h" + +#include "esp32c3_wdt.h" +#include "esp32c3_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check whether the provided device is a RTC Watchdog Timer */ + +#define IS_RWDT(dev) ((struct esp32c3_wdt_priv_s *)dev)->base == \ + RTC_CNTL_OPTIONS0_REG + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32c3_wdt_priv_s +{ + struct esp32c3_wdt_ops_s *ops; + uint32_t base; /* WDT register base address */ + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* Interrupt ID */ + int32_t cpuint; /* CPU interrupt assigned to this WDT */ + bool inuse; /* Flag indicating if this WDT is in use */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* WDT registers access *****************************************************/ + +static void esp32c3_wdt_putreg(struct esp32c3_wdt_dev_s *dev, + uint32_t offset, + uint32_t value); +static void esp32c3_wdt_modifyreg32(struct esp32c3_wdt_dev_s *dev, + uint32_t offset, + uint32_t clearbits, + uint32_t setbits); +static uint32_t esp32c3_wdt_getreg(struct esp32c3_wdt_dev_s *dev, + uint32_t offset); + +/* WDT operations ***********************************************************/ + +static void esp32c3_wdt_start(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_stop(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_enablewp(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_disablewp(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_pre(struct esp32c3_wdt_dev_s *dev, + uint16_t value); +static int32_t esp32c3_wdt_settimeout(struct esp32c3_wdt_dev_s *dev, + uint32_t value, + enum esp32c3_wdt_stage_e stage); +static void esp32c3_wdt_feed(struct esp32c3_wdt_dev_s *dev); +static int32_t esp32c3_wdt_config_stage(struct esp32c3_wdt_dev_s *dev, + enum esp32c3_wdt_stage_e stage, + enum esp32c3_wdt_stage_action_e cfg); +static void esp32c3_wdt_update_conf(struct esp32c3_wdt_dev_s *dev); +static int32_t esp32c3_wdt_setisr(struct esp32c3_wdt_dev_s *dev, + xcpt_t handler, void *arg); +static void esp32c3_wdt_enableint(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_disableint(struct esp32c3_wdt_dev_s *dev); +static void esp32c3_wdt_ackint(struct esp32c3_wdt_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ESP32 WDT ops */ + +struct esp32c3_wdt_ops_s esp32c3_mwdt_ops = +{ + .start = esp32c3_wdt_start, + .stop = esp32c3_wdt_stop, + .enablewp = esp32c3_wdt_enablewp, + .disablewp = esp32c3_wdt_disablewp, + .pre = esp32c3_wdt_pre, + .settimeout = esp32c3_wdt_settimeout, + .feed = esp32c3_wdt_feed, + .stg_conf = esp32c3_wdt_config_stage, + .upd_conf = esp32c3_wdt_update_conf, + .rtc_clk = NULL, + .setisr = esp32c3_wdt_setisr, + .enableint = esp32c3_wdt_enableint, + .disableint = esp32c3_wdt_disableint, + .ackint = esp32c3_wdt_ackint, +}; + +struct esp32c3_wdt_ops_s esp32c3_rwdt_ops = +{ + .start = esp32c3_wdt_start, + .stop = esp32c3_wdt_stop, + .enablewp = esp32c3_wdt_enablewp, + .disablewp = esp32c3_wdt_disablewp, + .pre = NULL, + .settimeout = esp32c3_wdt_settimeout, + .feed = esp32c3_wdt_feed, + .stg_conf = esp32c3_wdt_config_stage, + .upd_conf = NULL, + .rtc_clk = NULL, + .setisr = esp32c3_wdt_setisr, + .enableint = esp32c3_wdt_enableint, + .disableint = esp32c3_wdt_disableint, + .ackint = esp32c3_wdt_ackint, +}; + +#ifdef CONFIG_ESP32C3_MWDT0 +struct esp32c3_wdt_priv_s g_esp32c3_mwdt0_priv = +{ + .ops = &esp32c3_mwdt_ops, + .base = TIMG_T0CONFIG_REG(0), + .periph = ESP32C3_PERIPH_TG0_WDT, + .irq = ESP32C3_IRQ_TG0_WDT, + .cpuint = -ENOMEM, + .inuse = false, +}; +#endif + +#ifdef CONFIG_ESP32C3_MWDT1 +struct esp32c3_wdt_priv_s g_esp32c3_mwdt1_priv = +{ + .ops = &esp32c3_mwdt_ops, + .base = TIMG_T0CONFIG_REG(1), + .periph = ESP32C3_PERIPH_TG1_WDT, + .irq = ESP32C3_IRQ_TG1_WDT, + .cpuint = -ENOMEM, + .inuse = false, +}; +#endif + +#ifdef CONFIG_ESP32C3_RWDT +struct esp32c3_wdt_priv_s g_esp32c3_rwdt_priv = +{ + .ops = &esp32c3_rwdt_ops, + .base = RTC_CNTL_OPTIONS0_REG, + .periph = ESP32C3_PERIPH_RTC_CORE, + .irq = ESP32C3_IRQ_RTC_CORE, + .cpuint = -ENOMEM, + .inuse = false, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_wdt_putreg + * + * Description: + * Write a 32-bit register value by offset. + * + * Parameters: + * dev - Pointer to the driver state structure. + * offset - Offset value to the base address of the WDT device. + * value - Value to written to the specified memory region. + * + ****************************************************************************/ + +static void esp32c3_wdt_putreg(struct esp32c3_wdt_dev_s *dev, + uint32_t offset, + uint32_t value) +{ + DEBUGASSERT(dev); + + putreg32(value, ((struct esp32c3_wdt_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: esp32c3_wdt_modifyreg32 + * + * Description: + * Atomically modify a 32-bit register value by offset. + * + * Parameters: + * dev - Pointer to the driver state structure. + * offset - Offset value to the base address of the WDT device. + * clearbits - Bits to be cleared on the specified memory region. + * setbits - Bits to be set on the specified memory region. + * + ****************************************************************************/ + +static void esp32c3_wdt_modifyreg32(struct esp32c3_wdt_dev_s *dev, + uint32_t offset, + uint32_t clearbits, + uint32_t setbits) +{ + DEBUGASSERT(dev); + + modifyreg32(((struct esp32c3_wdt_priv_s *)dev)->base + offset, + clearbits, setbits); +} + +/**************************************************************************** + * Name: esp32c3_wdt_getreg + * + * Description: + * Read a 32-bit register value by offset. + * + * Parameters: + * dev - Pointer to the driver state structure. + * offset - Offset value to the base address of the WDT device. + * + * Returned Values: + * A 32-bit value from the provided memory region of the WDT device. + * + ****************************************************************************/ + +static uint32_t esp32c3_wdt_getreg(struct esp32c3_wdt_dev_s *dev, + uint32_t offset) +{ + DEBUGASSERT(dev); + + return getreg32(((struct esp32c3_wdt_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: esp32c3_wdt_start + * + * Description: + * Release the counter. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_start(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, 0, RTC_CNTL_WDT_EN); + } + else + { + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, 0, TIMG_WDT_EN); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_config_stage + * + * Description: + * Configure the action to be triggered by a stage on expiration. + * + * Parameters: + * dev - Pointer to the driver state structure. + * stage - WDT stage to be configured. + * cfg - Action to be executed on stage expiration. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int32_t esp32c3_wdt_config_stage(struct esp32c3_wdt_dev_s *dev, + enum esp32c3_wdt_stage_e stage, + enum esp32c3_wdt_stage_action_e cfg) +{ + int32_t ret = OK; + uint32_t mask; + DEBUGASSERT(dev); + + switch (stage) + { + case ESP32C3_WDT_STAGE0: + { + if (IS_RWDT(dev)) + { + mask = (uint32_t)cfg << RTC_CNTL_WDT_STG0_S; + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, + RTC_CNTL_WDT_STG0_M, mask); + } + else + { + mask = (uint32_t)cfg << TIMG_WDT_STG0_S; + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, + TIMG_WDT_STG0_M, mask); + } + break; + } + + case ESP32C3_WDT_STAGE1: + { + if (IS_RWDT(dev)) + { + mask = (uint32_t)cfg << RTC_CNTL_WDT_STG1_S; + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, + RTC_CNTL_WDT_STG1_M, mask); + } + else + { + mask = (uint32_t)cfg << TIMG_WDT_STG1_S; + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, + TIMG_WDT_STG1_M, mask); + } + break; + } + + case ESP32C3_WDT_STAGE2: + { + if (IS_RWDT(dev)) + { + mask = (uint32_t)cfg << RTC_CNTL_WDT_STG2_S; + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, + RTC_CNTL_WDT_STG2_M, mask); + } + else + { + mask = (uint32_t)cfg << TIMG_WDT_STG2_S; + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, + TIMG_WDT_STG2_M, mask); + } + break; + } + + case ESP32C3_WDT_STAGE3: + { + if (IS_RWDT(dev)) + { + mask = (uint32_t)cfg << RTC_CNTL_WDT_STG3_S; + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, + RTC_CNTL_WDT_STG3_M, mask); + } + else + { + mask = (uint32_t)cfg << TIMG_WDT_STG3_S; + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, + TIMG_WDT_STG3_M, mask); + } + break; + } + + default: + { + wderr("ERROR: unsupported stage %d\n", stage); + ret = -EINVAL; + goto errout; + } + } + + errout: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_wdt_update_conf + * + * Description: + * Update the Watchdog Timer configuration registers. + * Configuration registers for the MWDT are updated asynchronously. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_update_conf(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, 0, + TIMG_WDT_CONF_UPDATE_EN); +} + +/**************************************************************************** + * Name: esp32c3_wdt_stop + * + * Description: + * Disable the watchdog. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_stop(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_modifyreg32(dev, RWDT_CONFIG0_OFFSET, RTC_CNTL_WDT_EN, 0); + } + else + { + esp32c3_wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_EN, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_enablewp + * + * Description: + * Enable write protection (WP) on registers against accidental writing. + * TRM recommends to change any WDT register through this sequence: + * - Disable WP + * - Do the op + * - Reenable WP + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_enablewp(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_WP_REG, 0); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_WP_REG, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_disablewp + * + * Description: + * Disable write protection (WP) on registers against accidental writing. + * TRM recommends to change any WDT register through this sequence: + * - Disable WP + * - Do the op + * - Reenable WP + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_disablewp(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_WP_REG, RTC_CNTL_WDT_WKEY_VALUE); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_WP_REG, TIMG_WDT_WKEY_VALUE); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_pre + * + * Description: + * Set a prescale value. + * The MWDT clock period is 12.5 ns * value (pre). + * NOTE: There's no prescaler register for RWDT and its source clock is + * clocked from the RTC slow clock. + * + * Parameters: + * dev - Pointer to the driver state structure. + * pre - Prescaler value to be configured. + * + ****************************************************************************/ + +static void esp32c3_wdt_pre(struct esp32c3_wdt_dev_s *dev, + uint16_t pre) +{ + uint32_t mask = (uint32_t)pre << TIMG_WDT_CLK_PRESCALE_S; + + DEBUGASSERT(dev); + + esp32c3_wdt_modifyreg32(dev, MWDT_CLK_PRESCALE_OFFSET, + TIMG_WDT_CLK_PRESCALE_M, mask); +} + +/**************************************************************************** + * Name: esp32c3_wdt_settimeout + * + * Description: + * Set the WDT timeout. + * + * Parameters: + * dev - Pointer to the driver state structure. + * value - Timeout value in number of WDT cycles. + * stage - Stage whose timeout value needs to be configured. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int32_t esp32c3_wdt_settimeout(struct esp32c3_wdt_dev_s *dev, + uint32_t value, + enum esp32c3_wdt_stage_e stage) +{ + int32_t ret = OK; + DEBUGASSERT(dev); + + switch (stage) + { + case ESP32C3_WDT_STAGE0: + { + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_STAGE0_TIMEOUT_OFFSET, value); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_STAGE0_TIMEOUT_OFFSET, value); + } + break; + } + + case ESP32C3_WDT_STAGE1: + { + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_STAGE1_TIMEOUT_OFFSET, value); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_STAGE1_TIMEOUT_OFFSET, value); + } + break; + } + + case ESP32C3_WDT_STAGE2: + { + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_STAGE2_TIMEOUT_OFFSET, value); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_STAGE2_TIMEOUT_OFFSET, value); + } + break; + } + + case ESP32C3_WDT_STAGE3: + { + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_STAGE3_TIMEOUT_OFFSET, value); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_STAGE3_TIMEOUT_OFFSET, value); + } + break; + } + + default: + { + wderr("ERROR: unsupported stage %d\n", stage); + ret = -EINVAL; + goto errout; + } + } + + errout: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_wdt_feed + * + * Description: + * Feed the watchdog. + * The watchdog timer returns to stage 0 and its counter restarts from 0. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_feed(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_modifyreg32(dev, RWDT_FEED_OFFSET, 0, RTC_CNTL_WDT_FEED); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_FEED_OFFSET, TIMG_WDT_FEED); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_setisr + * + * Description: + * Allocate a Level CPU Interrupt, connect the peripheral source to this + * Interrupt, register the callback and enable the interrupt. + * In case a NULL handler is provided, deallocate the interrupt and + * unregister the previously provided handler. + * + * Parameters: + * dev - Pointer to the driver state structure. + * handler - Callback to be invoked on watchdog timer interrupt. + * arg - Argument to be passed to the handler callback. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int32_t esp32c3_wdt_setisr(struct esp32c3_wdt_dev_s *dev, + xcpt_t handler, + void *arg) +{ + struct esp32c3_wdt_priv_s *wdt = NULL; + int32_t ret = OK; + + DEBUGASSERT(dev); + + wdt = (struct esp32c3_wdt_priv_s *)dev; + + /* Disable interrupt when callback is removed. */ + + if (handler == NULL) + { + if (wdt->cpuint != -ENOMEM) + { + /* If a CPU Interrupt was previously allocated, + * then deallocate it. + */ + + up_disable_irq(wdt->cpuint); + irq_detach(wdt->irq); + esp32c3_free_cpuint(wdt->periph); + } + } + + /* Otherwise set callback and enable interrupt. */ + + else + { + if (wdt->cpuint != -ENOMEM) + { + /* Disable the provided CPU Interrupt to configure it. */ + + up_disable_irq(wdt->cpuint); + } + + wdt->cpuint = esp32c3_request_irq(wdt->periph, + ESP32C3_INT_PRIO_DEF, + ESP32C3_INT_LEVEL); + + if (wdt->cpuint < 0) + { + return wdt->cpuint; + } + + /* Attach and enable the IRQ. */ + + ret = irq_attach(wdt->irq, handler, arg); + if (ret == OK) + { + /* Enable the CPU Interrupt that is linked to the WDT. */ + + up_enable_irq(wdt->cpuint); + } + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_wdt_enableint + * + * Description: + * Enable a Level Interrupt at timeout. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_enableint(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, 0, + RTC_CNTL_WDT_INT_ENA); + } + else + { + esp32c3_wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, 0, + TIMG_WDT_INT_ENA); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_disableint + * + * Description: + * Disable a Level Interrupt at timeout. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_disableint(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, + RTC_CNTL_WDT_INT_ENA, 0); + } + else + { + esp32c3_wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, + TIMG_WDT_INT_ENA, 0); + } +} + +/**************************************************************************** + * Name: esp32c3_wdt_ackint + * + * Description: + * Acknowledge an interrupt. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +static void esp32c3_wdt_ackint(struct esp32c3_wdt_dev_s *dev) +{ + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + esp32c3_wdt_putreg(dev, RWDT_INT_CLR_REG_OFFSET, RTC_CNTL_WDT_INT_CLR); + } + else + { + esp32c3_wdt_putreg(dev, MWDT_INT_CLR_REG_OFFSET, TIMG_WDT_INT_CLR); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_wdt_init + * + * Description: + * Initialize WDT device. + * + * Parameters: + * wdt_id - A Watchdog Timer instance to be initialized. + * + * Return Values: + * Pointer to the driver state structure. + * + ****************************************************************************/ + +struct esp32c3_wdt_dev_s *esp32c3_wdt_init(enum esp32c3_wdt_inst_e wdt_id) +{ + struct esp32c3_wdt_priv_s *wdt = NULL; + + /* Get WDT instance */ + + switch (wdt_id) + { +#ifdef CONFIG_ESP32C3_MWDT0 + case ESP32C3_WDT_MWDT0: + { + wdt = &g_esp32c3_mwdt0_priv; + break; + } + +#endif + +#ifdef CONFIG_ESP32C3_MWDT1 + case ESP32C3_WDT_MWDT1: + { + wdt = &g_esp32c3_mwdt1_priv; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_RWDT + case ESP32C3_WDT_RWDT: + { + wdt = &g_esp32c3_rwdt_priv; + break; + } + +#endif + + default: + { + wderr("ERROR: unsupported WDT %d\n", wdt_id); + goto errout; + } + } + + /* If some code is using it then sends an error message, + * Otherwise, inform it has been used. + */ + + if (wdt->inuse == true) + { + wderr("ERROR: WDT %d is already in use\n", wdt_id); + wdt = NULL; + } + else + { + wdt->inuse = true; + } + + errout: + return (struct esp32c3_wdt_dev_s *)wdt; +} + +/**************************************************************************** + * Name: esp32c3_wdt_deinit + * + * Description: + * Deinitialize a WDT device. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + ****************************************************************************/ + +void esp32c3_wdt_deinit(struct esp32c3_wdt_dev_s *dev) +{ + struct esp32c3_wdt_priv_s *wdt = NULL; + + DEBUGASSERT(dev); + + wdt = (struct esp32c3_wdt_priv_s *)dev; + + wdt->inuse = false; +} + +/**************************************************************************** + * Name: esp32c3_wdt_is_running + * + * Description: + * Check whether the WDT is already started. + * + * Parameters: + * dev - Pointer to the driver state structure. + * + * Returned Values: + * true if the Watchdog Timer is already started, false otherwise. + * + ****************************************************************************/ + +bool esp32c3_wdt_is_running(struct esp32c3_wdt_dev_s *dev) +{ + uint32_t status = 0; + DEBUGASSERT(dev); + + if (IS_RWDT(dev)) + { + status = esp32c3_wdt_getreg(dev, RWDT_CONFIG0_OFFSET); + if (status & RTC_CNTL_WDT_EN) + { + return true; + } + } + else + { + status = esp32c3_wdt_getreg(dev, MWDT_CONFIG0_OFFSET); + if (status & TIMG_WDT_EN) + { + return true; + } + } + + return false; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.h b/arch/risc-v/src/esp32c3/esp32c3_wdt.h new file mode 100644 index 0000000000..5dad3e7e22 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt.h @@ -0,0 +1,147 @@ +/**************************************************************************** + * arch/riscv/src/esp32c3/esp32c3_wdt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define ESP32C3_WDT_START(d) ((d)->ops->start(d)) +#define ESP32C3_WDT_STOP(d) ((d)->ops->stop(d)) +#define ESP32C3_WDT_LOCK(d) ((d)->ops->enablewp(d)) +#define ESP32C3_WDT_UNLOCK(d) ((d)->ops->disablewp(d)) +#define ESP32C3_MWDT_PRE(d, v) ((d)->ops->pre(d, v)) +#define ESP32C3_WDT_STO(d, v, s) ((d)->ops->settimeout(d, v, s)) +#define ESP32C3_WDT_FEED(d) ((d)->ops->feed(d)) +#define ESP32C3_WDT_STG_CONF(d, s, c) ((d)->ops->stg_conf(d, s, c)) +#define ESP32C3_MWDT_UPD_CONF(d) ((d)->ops->upd_conf(d)) +#define ESP32C3_RWDT_CLK(d) ((d)->ops->rtc_clk(d)) +#define ESP32C3_WDT_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg)) +#define ESP32C3_WDT_ENABLEINT(d) ((d)->ops->enableint(d)) +#define ESP32C3_WDT_DISABLEINT(d) ((d)->ops->disableint(d)) +#define ESP32C3_WDT_ACKINT(d) ((d)->ops->ackint(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Instances of Watchdog Timer */ + +enum esp32c3_wdt_inst_e +{ + ESP32C3_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ + ESP32C3_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ + ESP32C3_WDT_RWDT /* RTC Watchdog Timer (RWDT) */ +}; + +/* Stages of a Watchdog Timer. A WDT has 4 stages. */ + +enum esp32c3_wdt_stage_e +{ + ESP32C3_WDT_STAGE0 = 0, /* Stage 0 */ + ESP32C3_WDT_STAGE1 = 1, /* Stage 1 */ + ESP32C3_WDT_STAGE2 = 2, /* Stage 2 */ + ESP32C3_WDT_STAGE3 = 3 /* Stage 3 */ +}; + +/** + * Behavior of the WDT stage if it times out. + * + * @note These enum values should be compatible with the + * corresponding register field values. + */ + +enum esp32c3_wdt_stage_action_e +{ + ESP32C3_WDT_STAGE_ACTION_OFF = 0, /* Disabled. This stage will have no effects on the system. */ + ESP32C3_WDT_STAGE_ACTION_INT = 1, /* Trigger an interrupt when the stage expires. */ + ESP32C3_WDT_STAGE_ACTION_RESET_CPU = 2, /* Reset a CPU core when the stage expires. */ + ESP32C3_WDT_STAGE_ACTION_RESET_SYSTEM = 3, /* Reset the main system when the stage expires. + * This includes the CPU and all peripherals. + * The RTC is an exception and will not be reset. + */ + ESP32C3_WDT_STAGE_ACTION_RESET_RTC = 4 /* Reset the main system and the RTC when the stage expires. + * ONLY AVAILABLE FOR RWDT. + */ +}; + +/* ESP32 WDT device */ + +struct esp32c3_wdt_dev_s +{ + struct esp32c3_wdt_ops_s *ops; +}; + +/* ESP32 WDT ops */ + +/* This is a struct containing the pointers to the wdt operations */ + +struct esp32c3_wdt_ops_s +{ + /* WDT tasks */ + + void (*start)(struct esp32c3_wdt_dev_s *dev); + void (*stop)(struct esp32c3_wdt_dev_s *dev); + + /* WDT configuration */ + + void (*enablewp)(struct esp32c3_wdt_dev_s *dev); + void (*disablewp)(struct esp32c3_wdt_dev_s *dev); + void (*pre)(struct esp32c3_wdt_dev_s *dev, uint16_t value); + int32_t (*settimeout)(struct esp32c3_wdt_dev_s *dev, + uint32_t value, + enum esp32c3_wdt_stage_e stage); + void (*feed)(struct esp32c3_wdt_dev_s *dev); + int32_t (*stg_conf)(struct esp32c3_wdt_dev_s *dev, + enum esp32c3_wdt_stage_e stage, + enum esp32c3_wdt_stage_action_e conf); + void (*upd_conf)(struct esp32c3_wdt_dev_s *dev); + uint16_t (*rtc_clk)(struct esp32c3_wdt_dev_s *dev); + + /* WDT interrupts */ + + int32_t (*setisr)(struct esp32c3_wdt_dev_s *dev, xcpt_t handler, + void * arg); + void (*enableint)(struct esp32c3_wdt_dev_s *dev); + void (*disableint)(struct esp32c3_wdt_dev_s *dev); + void (*ackint)(struct esp32c3_wdt_dev_s *dev); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct esp32c3_wdt_dev_s *esp32c3_wdt_init(enum esp32c3_wdt_inst_e wdt_id); +void esp32c3_wdt_deinit(struct esp32c3_wdt_dev_s *dev); +bool esp32c3_wdt_is_running(struct esp32c3_wdt_dev_s *dev); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c new file mode 100644 index 0000000000..229d62fd5d --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c @@ -0,0 +1,746 @@ +/**************************************************************************** + * arch/riscv/src/esp32c3/esp32c3_wdt_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_soc.h" +#include "esp32c3_wdt.h" +#include "esp32c3_wdt_lowerhalf.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MWDT clock period in microseconds */ + +#define MWDT_CLK_PERIOD_US (500) + +/* Number of MWDT cycles per microseconds */ + +#define MWDT_CYCLES_PER_MS (USEC_PER_MSEC / MWDT_CLK_PERIOD_US) + +/* Convert MWDT timeout cycles to milliseconds */ + +#define MWDT_TIMEOUT_MS(t) ((t) * MWDT_CYCLES_PER_MS) + +/* Maximum number of MWDT cycles supported for timeout */ + +#define MWDT_MAX_TIMEOUT_MS (UINT32_MAX / MWDT_CYCLES_PER_MS) + +/* MWDT clock prescaler value */ + +#define MWDT_CLK_PRESCALER_VALUE (MWDT_CLK_PERIOD_US * NSEC_PER_USEC / 12.5) + +/* Maximum number of cycles supported for a RWDT stage timeout */ + +#define RWDT_FULL_STAGE (UINT32_MAX) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef enum +{ + RTC, + TIMER, +} wdt_peripherals_t; + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * well-known watchdog_lowerhalf_s structure. + */ + +struct esp32c3_wdt_lowerhalf_s +{ + const struct watchdog_ops_s *ops; /* Lower half operations */ + struct esp32c3_wdt_dev_s *wdt; /* ESP32-C3 watchdog driver */ + uint32_t timeout; /* The current timeout */ + wdt_peripherals_t peripheral; /* Indicates if it is from RTC or Timer Module */ + uint32_t lastreset; /* The last reset time */ + bool started; /* True: Timer has been started */ + xcpt_t handler; /* User Handler */ + void *upper; /* Pointer to watchdog_upperhalf_s */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Interrupt handling *******************************************************/ + +static int esp32c3_wdt_handler(int irq, void *context, void *arg); + +/* "Lower half" driver methods **********************************************/ + +static int esp32c3_wdt_start(struct watchdog_lowerhalf_s *lower); +static int esp32c3_wdt_stop(struct watchdog_lowerhalf_s *lower); +static int esp32c3_wdt_keepalive(struct watchdog_lowerhalf_s *lower); +static int esp32c3_wdt_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int esp32c3_wdt_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t esp32c3_wdt_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct watchdog_ops_s g_esp32c3_wdg_ops = +{ + .start = esp32c3_wdt_start, + .stop = esp32c3_wdt_stop, + .keepalive = esp32c3_wdt_keepalive, + .getstatus = esp32c3_wdt_getstatus, + .settimeout = esp32c3_wdt_settimeout, + .capture = esp32c3_wdt_capture, + .ioctl = NULL, +}; + +#ifdef CONFIG_ESP32C3_MWDT0 +/* MWDT0 lower-half */ + +static struct esp32c3_wdt_lowerhalf_s g_esp32c3_mwdt0_lowerhalf = +{ + .ops = &g_esp32c3_wdg_ops, +}; +#endif + +#ifdef CONFIG_ESP32C3_MWDT1 +/* MWDT1 lower-half */ + +static struct esp32c3_wdt_lowerhalf_s g_esp32c3_mwdt1_lowerhalf = +{ + .ops = &g_esp32c3_wdg_ops, +}; +#endif + +#ifdef CONFIG_ESP32C3_RWDT +/* RWDT lower-half */ + +static struct esp32c3_wdt_lowerhalf_s g_esp32c3_rwdt_lowerhalf = +{ + .ops = &g_esp32c3_wdg_ops, +}; +#endif + +/**************************************************************************** + * Name: esp32c3_wdt_start + * + * Description: + * Start the watchdog timer, register a callback if there is one and + * enables interrupt, otherwise, configure it to reset system on + * expiration. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32c3_wdt_start(struct watchdog_lowerhalf_s *lower) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + int ret = OK; + irqstate_t flags; + + wdinfo("Entry: started\n"); + DEBUGASSERT(priv); + + if (priv->started == true) + { + /* Return EBUSY to indicate that the timer was already running */ + + ret = -EBUSY; + goto errout; + } + + /* If WDT was not started yet */ + + else + { + priv->started = true; + + /* Unlock WDT */ + + ESP32C3_WDT_UNLOCK(priv->wdt); + + /* No User Handler */ + + if (priv->handler == NULL) + { + /* Then configure it to reset on wdt expiration */ + + if (priv->peripheral == TIMER) + { + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_RESET_SYSTEM); + ESP32C3_MWDT_UPD_CONF(priv->wdt); + } + else + { + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_RESET_RTC); + } + } + + /* User handler was already provided */ + + else + { + /* Then configure it to call the user handler on wdt expiration */ + + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_INT); + + if (priv->peripheral == TIMER) + { + ESP32C3_MWDT_UPD_CONF(priv->wdt); + } + + /* Set the lower half handler and enable interrupt */ + + flags = enter_critical_section(); + ESP32C3_WDT_SETISR(priv->wdt, esp32c3_wdt_handler, priv); + leave_critical_section(flags); + ESP32C3_WDT_ENABLEINT(priv->wdt); + } + flags = enter_critical_section(); + priv->lastreset = clock_systime_ticks(); + ESP32C3_WDT_START(priv->wdt); + leave_critical_section(flags); + + /* Lock it again */ + + ESP32C3_WDT_LOCK(priv->wdt); + } + errout: + return ret; +} + +/**************************************************************************** + * Name: esp32c3_wdt_stop + * + * Description: + * Stop the watchdog timer. In case a callback was previously configured, + * unregister and deallocate it. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + ****************************************************************************/ + +static int esp32c3_wdt_stop(struct watchdog_lowerhalf_s *lower) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + irqstate_t flags; + + /* Unlock WDT */ + + ESP32C3_WDT_UNLOCK(priv->wdt); + + /* Disable the WDT */ + + ESP32C3_WDT_STOP(priv->wdt); + + /* In case there is some callback registered, disable and deallocate */ + + if (priv->handler != NULL) + { + ESP32C3_WDT_DISABLEINT(priv->wdt); + flags = enter_critical_section(); + ESP32C3_WDT_SETISR(priv->wdt, NULL, NULL); + leave_critical_section(flags); + } + + /* Lock it again */ + + ESP32C3_WDT_LOCK(priv->wdt); + + priv->started = false; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_wdt_keepalive + * + * Description: + * Reset the watchdog timer, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * + ****************************************************************************/ + +static int esp32c3_wdt_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + irqstate_t flags; + + wdinfo("Entry\n"); + + /* Unlock */ + + ESP32C3_WDT_UNLOCK(priv->wdt); + + /* Feed the dog and updates the lastreset variable */ + + flags = enter_critical_section(); + priv->lastreset = clock_systime_ticks(); + ESP32C3_WDT_FEED(priv->wdt); + leave_critical_section(flags); + + /* Lock */ + + ESP32C3_WDT_LOCK(priv->wdt); + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_wdt_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + ****************************************************************************/ + +static int esp32c3_wdt_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + uint32_t ticks; + uint32_t elapsed; + + DEBUGASSERT(priv); + + /* Flags */ + + status->flags = 0; + + /* If no handler was settled, then RESET on expiration. + * Otherwise, call the user handler. + */ + + if (priv->handler == NULL) + { + status->flags |= WDFLAGS_RESET; + } + else + { + status->flags |= WDFLAGS_CAPTURE; + } + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the current timeout in milliseconds */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (uint32_t)TICK2MSEC(ticks); + + if (elapsed < priv->timeout) + { + /* Return the approximate time until the watchdog timer expiration */ + + status->timeleft = priv->timeout - elapsed; + } + else + { + status->timeleft = 0; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_wdt_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int esp32c3_wdt_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + uint16_t rtc_cycles = 0; + uint32_t rtc_ms_max = 0; + + wdinfo("Entry: timeout=%"PRIu32"\n", timeout); + DEBUGASSERT(priv); + + /* Unlock WDT */ + + ESP32C3_WDT_UNLOCK(priv->wdt); + + /* Write the timeout value */ + + priv->timeout = timeout; + + /* Watchdog from Timer Module */ + + if (priv->peripheral == TIMER) + { + /* Is this timeout a valid value for Timer's WDT? */ + + if (timeout == 0 || timeout > MWDT_MAX_TIMEOUT_MS) + { + wderr("ERROR: Cannot represent timeout=%"PRIu32" > %"PRIu32"\n", + timeout, MWDT_MAX_TIMEOUT_MS); + return -ERANGE; + } + else + { + ESP32C3_WDT_STO(priv->wdt, MWDT_TIMEOUT_MS(timeout), + ESP32C3_WDT_STAGE0); + ESP32C3_MWDT_UPD_CONF(priv->wdt); + } + } + + /* Watchdog from RTC Module */ + + else + { + rtc_cycles = ESP32C3_RWDT_CLK(priv->wdt); + rtc_ms_max = (RWDT_FULL_STAGE / (uint32_t)rtc_cycles); + + /* Is this timeout a valid value for RTC WDT? */ + + if (timeout == 0 || timeout > rtc_ms_max) + { + wderr("ERROR: Cannot represent timeout=%"PRIu32" > %"PRIu32"\n", + timeout, rtc_ms_max); + return -ERANGE; + } + else + { + timeout = timeout * rtc_cycles; + ESP32C3_WDT_STO(priv->wdt, timeout, ESP32C3_WDT_STAGE0); + } + } + + /* Reset the wdt */ + + ESP32C3_WDT_FEED(priv->wdt); + + /* Lock it again */ + + ESP32C3_WDT_LOCK(priv->wdt); + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_wdt_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * newhandler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored, + * + * Returned Value: + * The previous watchdog expiration function pointer or NULL if there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t esp32c3_wdt_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler) +{ + struct esp32c3_wdt_lowerhalf_s *priv = + (struct esp32c3_wdt_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + + DEBUGASSERT(priv); + + wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t) handler); + + /* Get the old handler to return it */ + + oldhandler = priv->handler; + + ESP32C3_WDT_UNLOCK(priv->wdt); + + flags = enter_critical_section(); + + /* Save the new user handler */ + + priv->handler = handler; + + /* There is a user callback and the timer has already been started. + * The user wants to set a callback after starting the wdt or wants to + * change the callback function once a callback has already been settled. + */ + + if (priv->handler != NULL && priv->started == true) + { + /* Deallocate the previous allocated interrupt + * If there is a previous allocated interrupt. + */ + + if (oldhandler != NULL) + { + ESP32C3_WDT_SETISR(priv->wdt, NULL, NULL); + } + else + { + /* If it was previous configured to reset on timeout + * then change to interrupt. + */ + + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_INT); + + if (priv->peripheral == TIMER) + { + ESP32C3_MWDT_UPD_CONF(priv->wdt); + } + } + + /* Set the lower half handler and enable interrupt */ + + ESP32C3_WDT_SETISR(priv->wdt, esp32c3_wdt_handler, priv); + ESP32C3_WDT_ENABLEINT(priv->wdt); + } + + /* In case the user wants to disable the callback */ + + else + { + ESP32C3_WDT_DISABLEINT(priv->wdt); + ESP32C3_WDT_SETISR(priv->wdt, NULL, NULL); + + /* Then configure it to reset on WDT expiration */ + + if (priv->peripheral == TIMER) + { + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_RESET_SYSTEM); + ESP32C3_MWDT_UPD_CONF(priv->wdt); + } + else + { + ESP32C3_WDT_STG_CONF(priv->wdt, ESP32C3_WDT_STAGE0, + ESP32C3_WDT_STAGE_ACTION_RESET_RTC); + } + } + + leave_critical_section(flags); + ESP32C3_WDT_LOCK(priv->wdt); + return oldhandler; +} + +/* Interrupt handling *******************************************************/ + +static int esp32c3_wdt_handler(int irq, void *context, void *arg) +{ + struct esp32c3_wdt_lowerhalf_s *priv = arg; + + /* Run the user callback */ + + priv->handler(irq, context, priv->upper); + + /* Clear the Interrupt */ + + ESP32C3_WDT_UNLOCK(priv->wdt); + + ESP32C3_WDT_ACKINT(priv->wdt); + + ESP32C3_WDT_LOCK(priv->wdt); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_wdt_initialize + * + * Description: + * Initialize the watchdog timer. The watchdog timer is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should + * be of the form /dev/watchdogX + * wdt - WDT instance to be initialized. + * + * Returned Values: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32c3_wdt_initialize(const char *devpath, enum esp32c3_wdt_inst_e wdt) +{ + struct esp32c3_wdt_lowerhalf_s *lower = NULL; + int ret = OK; + + DEBUGASSERT(devpath); + + switch (wdt) + { +#ifdef CONFIG_ESP32C3_MWDT0 + case ESP32C3_WDT_MWDT0: + { + lower = &g_esp32c3_mwdt0_lowerhalf; + lower->peripheral = TIMER; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_MWDT1 + case ESP32C3_WDT_MWDT1: + { + lower = &g_esp32c3_mwdt1_lowerhalf; + lower->peripheral = TIMER; + break; + } +#endif + +#ifdef CONFIG_ESP32C3_RWDT + case ESP32C3_WDT_RWDT: + { + lower = &g_esp32c3_rwdt_lowerhalf; + lower->peripheral = RTC; + break; + } +#endif + + default: + { + ret = -ENODEV; + goto errout; + } + } + + /* Initialize the elements of lower half state structure */ + + lower->handler = NULL; + lower->timeout = 0; + lower->wdt = esp32c3_wdt_init(wdt); + + if (lower->wdt == NULL) + { + ret = -EINVAL; + goto errout; + } + + lower->started = esp32c3_wdt_is_running(lower->wdt); + + ESP32C3_WDT_UNLOCK(lower->wdt); + + /* If it is a Main System Watchdog Timer configure the Prescale to + * have a 500us period. + */ + + if (lower->peripheral == TIMER) + { + ESP32C3_MWDT_PRE(lower->wdt, MWDT_CLK_PRESCALER_VALUE); + ESP32C3_MWDT_UPD_CONF(lower->wdt); + } + + ESP32C3_WDT_LOCK(lower->wdt); + + /* Register the watchdog driver as /dev/watchdogX. If the registration goes + * right the returned value from watchdog_register is a pointer to + * watchdog_upperhalf_s that can be either used with watchdog_unregister() + * or with the handler's arg. + */ + + lower->upper = watchdog_register(devpath, + (struct watchdog_lowerhalf_s *)lower); + if (lower->upper == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the watchdog driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + ret = -EEXIST; + goto errout; + } + +errout: + return ret; +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h new file mode 100644 index 0000000000..318f21bb40 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/riscv/src/esp32c3/esp32c3_wdt_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_wdt.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_wdt_initialize + * + * Description: + * Initialize the watchdog timer. The watchdog timer is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should + * be of the form /dev/watchdogX + * wdt - WDT instance to be initialized. + * + * Returned Values: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32c3_wdt_initialize(const char *devpath, enum esp32c3_wdt_inst_e wdt); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h new file mode 100644 index 0000000000..2b54e4ed6c --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h @@ -0,0 +1,3618 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_rcccntl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Offset relative to each wathdog timer instance memory base */ + +#define RWDT_CONFIG0_OFFSET 0x0090 + +/* RWDT */ +#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0094 +#define RWDT_STAGE1_TIMEOUT_OFFSET 0x0098 +#define RWDT_STAGE2_TIMEOUT_OFFSET 0x009c +#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00a0 +#define RWDT_FEED_OFFSET 0x00a4 +#define RWDT_WP_REG 0x00a8 +#define RWDT_INT_ENA_REG_OFFSET 0x0040 +#define RWDT_INT_CLR_REG_OFFSET 0x004c + +/* The value that needs to be written to RTC_CNTL_WDT_WKEY to + * write-enable the wdt registers + */ + +#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1 + +/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG + * to write-enable the wdt registers + */ + +#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A + +/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH + * and RTC_CNTL_WDT_SYS_RESET_LENGTH + */ + +#define RTC_WDT_RESET_LENGTH_100_NS 0 +#define RTC_WDT_RESET_LENGTH_200_NS 1 +#define RTC_WDT_RESET_LENGTH_300_NS 2 +#define RTC_WDT_RESET_LENGTH_400_NS 3 +#define RTC_WDT_RESET_LENGTH_500_NS 4 +#define RTC_WDT_RESET_LENGTH_800_NS 5 +#define RTC_WDT_RESET_LENGTH_1600_NS 6 +#define RTC_WDT_RESET_LENGTH_3200_NS 7 + +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) + +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ + +/* Description: SW system reset */ + +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ + +/* Description: digital core force no reset in deep sleep */ + +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 + +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ + +/* Description: digital wrap force reset in deep sleep */ + +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 + +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ + +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 + +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ + +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 + +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ + +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 + +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ + +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 + +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ + +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 + +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ + +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 + +/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ + +#define RTC_CNTL_XTL_EXT_CTR_SEL 0x00000007 +#define RTC_CNTL_XTL_EXT_CTR_SEL_M ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S)) +#define RTC_CNTL_XTL_EXT_CTR_SEL_V 0x7 +#define RTC_CNTL_XTL_EXT_CTR_SEL_S 20 + +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ + +/* Description: wait bias_sleep and current source wakeup */ + +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 + +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ + +/* Description: crystal force power up */ + +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 + +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: crystal force power down */ + +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 + +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ + +/* Description: BB_PLL force power up */ + +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 + +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: BB_PLL force power down */ + +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ + +/* Description: BB_PLL_I2C force power up */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: BB_PLL _I2C force power down */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 + +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ + +/* Description: BB_I2C force power up */ + +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 + +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: BB_I2C force power down */ + +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 + +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: PRO CPU SW reset */ + +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 + +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: APP CPU SW reset */ + +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 + +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ + +/* Description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + * 0x86 will stall PRO CPU + */ + +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 + +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ + +/* Description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + * 0x86 will stall APP CPU + */ + +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) + +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) + +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ + +/* Description: timer alarm enable bit */ + +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 + +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ + +/* Description: RTC sleep timer high 16 bits */ + +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) + +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: Set 1: to update register with RTC timer */ + +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 + +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: enable to record system reset time */ + +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 + +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Enable to record 40M XTAL OFF time */ + +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 + +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Enable to record system stall time */ + +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) + +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: RTC timer low 32 bits */ + +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) + +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ + +/* Description: RTC timer high 16 bits */ + +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) + +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +/* Description: sleep enable bit */ + +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 + +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ + +/* Description: leep reject bit */ + +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 + +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ + +/* Description: leep wakeup bit */ + +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 + +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ + +/* Description: SDIO active indication */ + +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 + +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ + +/* Description: 1: APB to RTC using bridge */ + +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 + +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: clear RTC sleep reject cause */ + +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 + +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: RTC software interrupt to main CPU */ + +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) + +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ + +/* Description: PLL wait cycles in slow_clk_rtc */ + +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 + +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ + +/* Description: XTAL wait cycles in slow_clk_rtc */ + +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 + +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ + +/* Description: CK8M wait cycles in slow_clk_rtc */ + +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 + +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ + +/* Description: CPU stall wait cycles in fast_clk_rtc */ + +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 + +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ + +/* Description: CPU stall enable bit */ + +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) + +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ + +/* Description: minimal cycles in slow_clk_rtc for CK8M in power down state */ + +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) + +/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ + +#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_BT_POWERUP_TIMER_M ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S)) +#define RTC_CNTL_BT_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_BT_POWERUP_TIMER_S 25 + +/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ + +#define RTC_CNTL_BT_WAIT_TIMER 0x000001FF +#define RTC_CNTL_BT_WAIT_TIMER_M ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S)) +#define RTC_CNTL_BT_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_BT_WAIT_TIMER_S 16 + +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ + +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 + +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ + +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) + +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ + +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ + +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 + +/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ + +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S)) +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 + +/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ + +#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S)) +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) + +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ + +/* Description: minimal sleep cycles in slow_clk_rtc */ + +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) + +/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */ + +#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */ + +#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_M ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S)) +#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) + +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 + +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ + +/* Description: 1: CKGEN_I2C power up */ + +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 + +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ + +/* Description: 1: RFRX_PBUS power up */ + +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 + +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ + +/* Description: 1: TXRF_I2C power up */ + +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 + +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: 1: PVTMON power up */ + +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 + +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: start BBPLL calibration during sleep */ + +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 + +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: PLLA force power up */ + +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 + +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ + +/* Description: PLLA force power down */ + +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ + +/* Description: PLLA force power up */ + +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 + +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) + +/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +#define RTC_CNTL_DRESET_MASK_PROCPU (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_M (BIT(25)) +#define RTC_CNTL_DRESET_MASK_PROCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_PROCPU_S 25 + +/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +#define RTC_CNTL_DRESET_MASK_APPCPU (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_M (BIT(24)) +#define RTC_CNTL_DRESET_MASK_APPCPU_V 0x1 +#define RTC_CNTL_DRESET_MASK_APPCPU_S 24 + +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */ + +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M (BIT(23)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S 23 + +/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */ + +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M (BIT(22)) +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S 22 + +/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ + +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S 21 + +/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S 20 + +/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: PROCPU OcdHaltOnreset */ + +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M (BIT(19)) +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S 19 + +/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: APPCPU OcdHaltOnreset */ + +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M (BIT(18)) +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V 0x1 +#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S 18 + +/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: clear APP CPU reset flag */ + +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M (BIT(17)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S 17 + +/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: clear PRO CPU reset_flag */ + +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M (BIT(16)) +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S 16 + +/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: APP CPU reset flag */ + +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S 15 + +/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: PRO CPU reset_flag */ + +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S 14 + +/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */ + +/* Description: PRO CPU state vector sel */ + +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M (BIT(13)) +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S 13 + +/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */ + +/* Description: APP CPU state vector sel */ + +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M (BIT(12)) +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V 0x1 +#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S 12 + +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ + +/* Description: reset cause of APP CPU */ + +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 + +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ + +/* Description: reset cause of PRO CPU */ + +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) + +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ + +/* Description: wakeup enable bitmap */ + +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) + +/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_ENA (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: enbale gitch det interrupt */ + +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: enable xtal32k_dead interrupt */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 + +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: enable super watch dog interrupt */ + +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: enable RTC main timer interrupt */ + +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: enable brown out interrupt */ + +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 + +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: enable RTC WDT interrupt */ + +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: enable sleep reject interrupt */ + +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: enable sleep wakeup interrupt */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) + +/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_RAW (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_RAW_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_RAW_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: glitch_det_interrupt_raw */ + +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: xtal32k dead detection interrupt raw */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 + +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: super watch dog interrupt raw */ + +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: RTC main timer interrupt raw */ + +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: brown out interrupt raw */ + +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 + +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: RTC WDT interrupt raw */ + +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: sleep reject interrupt raw */ + +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: sleep wakeup interrupt raw */ + +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) + +/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_ST (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ST_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ST_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: glitch_det_interrupt state */ + +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: xtal32k dead detection interrupt state */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 + +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: super watch dog interrupt state */ + +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: RTC main timer interrupt state */ + +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: brown out interrupt state */ + +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 + +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: RTC WDT interrupt state */ + +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: sleep reject interrupt state */ + +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: sleep wakeup interrupt state */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) + +/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_CLR (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_CLR_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_CLR_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: Clear glitch det interrupt state */ + +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: Clear RTC WDT interrupt state */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 + +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: Clear super watch dog interrupt state */ + +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: Clear RTC main timer interrupt state */ + +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: Clear brown out interrupt state */ + +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 + +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: Clear RTC WDT interrupt state */ + +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: Clear sleep reject interrupt state */ + +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Clear sleep wakeup interrupt state */ + +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) + +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) + +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) + +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) + +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) + +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 + +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: 0: power down XTAL at high level */ + +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: XTAL_32K sel. 0: external XTAL_32k */ + +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 + +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ + +/* Description: state of 32k_wdt */ + +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 + +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ + +/* Description: DAC_XTAL_32k */ + +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 + +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ + +/* Description: XPD_XTAL_32k */ + +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 + +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ + +/* Description: DRES_XTAL_32k */ + +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 + +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ + +/* Description: xtal_32k gm control */ + +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 + +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: 0: single-end buffer 1: differential buffer */ + +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 + +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: apply an internal clock to help xtal 32k to start */ + +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 + +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ + +/* Description: Xtal 32k xpd control by sw or fsm */ + +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 + +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: xtal 32k switch back xtal when xtal is restarted */ + +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 + +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: xtal 32k restart xtal when xtal is dead */ + +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 + +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: xtal 32k switch to back up clock when xtal is dead */ + +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 + +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: xtal 32k external xtal clock force on */ + +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 + +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: xtal 32k watch dog sw reset */ + +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 + +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: xtal 32k watch dog clock force on */ + +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 + +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: xtal 32k watch dog enable */ + +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) + +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: enable filter for gpio wakeup event */ + +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(31)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 31 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) + +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: enable reject for deep sleep */ + +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 + +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: enable reject for light sleep */ + +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 + +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ + +/* Description: sleep reject enable */ + +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) + +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ + +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 + +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: CPU sel option */ + +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) + +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ + +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 + +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: fast_clk_rtc sel. 0: XTAL div 4 */ + +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 + +/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */ + +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (BIT(28)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 + +/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (BIT(27)) +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x1 +#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 + +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ + +/* Description: CK8M force power up */ + +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 + +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ + +/* Description: CK8M force power down */ + +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 + +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ + +/* Description: CK8M_DFREQ */ + +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 + +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ + +/* Description: CK8M force no gating during sleep */ + +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 + +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ + +/* Description: XTAL force no gating during sleep */ + +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 + +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ + +/* Description: divider = reg_ck8m_div_sel + 1 */ + +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 + +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ + +/* Description: enable CK8M for digital core + * (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 + +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ + +/* Description: enable CK8M_D256_OUT for digital core + * (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 + +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ + +/* Description: enable CK_XTAL_32K for digital core + * (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 + +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ + +/* Description: 1: CK8M_D256_OUT is actually CK8M */ + +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 + +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ + +/* Description: disable CK8M and CK8M_D256_OUT */ + +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 + +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ + +/* Description: CK8M_D256_OUT divider. 00: div128 */ + +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 + +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ + +/* Description: used to sync reg_ck8m_div_sel bus. + * Clear VLD before set reg_ck8m_div_sel + */ + +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 + +/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (BIT(2)) +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 + +/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (BIT(1)) +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x1 +#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) + +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 + +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ + +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 + +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ + +/* Description: used to sync div bus. + * Clear VLD before set reg_rtc_ana_clk_div + */ + +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) + +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ + +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 + +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ + +/* Description: SW option for DREFH_SDIO. + * Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 + +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ + +/* Description: SW option for DREFM_SDIO. + * Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 + +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ + +/* Description: SW option for DREFL_SDIO. + * Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 + +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ + +/* Description: read only register for REG1P8_READY */ + +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 + +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ + +/* Description: SW option for SDIO_TIEH. + * Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 + +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ + +/* Description: 1: use SW option to control SDIO_REG */ + +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 + +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ + +/* Description: power down SDIO_REG in sleep. + * Only active when reg_sdio_force = 0 + */ + +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 + +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ + +/* Description: enable current limit */ + +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 + +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ + +/* Description: select current limit mode */ + +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 + +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ + +/* Description: tune current limit threshold when tieh = 0. + * About 800mA/(8+d) + */ + +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 + +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ + +/* Description: 0 to set init[1:0]=0 */ + +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 + +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ + +/* Description: add resistor from ldo output to ground. 0: no res */ + +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 + +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ + +/* Description: ability to prevent LDO from overshoot */ + +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 + +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ + +/* Description: Tieh = 1 mode drive ability. + * Initially set to 0 to limit charge current + */ + +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 + +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ + +/* Description: timer count to apply reg_sdio_dcap after sdio power on */ + +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) + +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ + +/* Description: DBG_ATTEN when RTC in monitor state */ + +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 + +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ + +/* Description: DBG_ATTEN when RTC in sleep state */ + +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 + +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: bias_sleep when RTC in monitor state */ + +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 + +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ + +/* Description: bias_sleep when RTC in sleep_state */ + +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 + +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: xpd cur when RTC in monitor state */ + +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 + +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: xpd cur when RTC in sleep_state */ + +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 + +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 + +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 + +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ + +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 + +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M (BIT(8)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V 0x1 +#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S 8 + +/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ + +#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000FF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_M ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S)) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0xFF +#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 0 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0080) + +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ + +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 + +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ + +/* Description: RTC_REG force power down (for RTC_REG power down means + * decrease the voltage to 0.8v or lower) + */ + +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 + +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ + +/* Description: RTC_DBOOST force power up */ + +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 + +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ + +/* Description: RTC_DBOOST force power down */ + +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 + +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ + +/* Description: SCK_DCAP */ + +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_CAL_EN_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0084) + +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ + +/* Description: RTC pad force hold */ + +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) + +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 + +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: enable power down wifi in sleep */ + +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 + +/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_M (BIT(29)) +#define RTC_CNTL_CPU_TOP_PD_EN_V 0x1 +#define RTC_CNTL_CPU_TOP_PD_EN_S 29 + +/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_M (BIT(28)) +#define RTC_CNTL_DG_PERI_PD_EN_V 0x1 +#define RTC_CNTL_DG_PERI_PD_EN_S 28 + +/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +#define RTC_CNTL_BT_PD_EN (BIT(27)) +#define RTC_CNTL_BT_PD_EN_M (BIT(27)) +#define RTC_CNTL_BT_PD_EN_V 0x1 +#define RTC_CNTL_BT_PD_EN_S 27 + +/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ + +#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 + +/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 + +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ + +/* Description: digital core force power up */ + +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 + +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: digital core force power down */ + +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 + +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ + +/* Description: wifi force power up */ + +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 + +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: wifi force power down */ + +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 + +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */ + +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(16)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 16 + +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(15)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 15 + +/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */ + +#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 + +/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 + +/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +#define RTC_CNTL_BT_FORCE_PU (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_BT_FORCE_PU_V 0x1 +#define RTC_CNTL_BT_FORCE_PU_S 12 + +/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define RTC_CNTL_BT_FORCE_PD (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_BT_FORCE_PD_V 0x1 +#define RTC_CNTL_BT_FORCE_PD_S 11 + +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +/* Description: memories in digital core force no PD in sleep */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 + +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: memories in digital core force PD in sleep */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define RTC_CNTL_VDD_SPI_PWR_FORCE (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_M (BIT(2)) +#define RTC_CNTL_VDD_SPI_PWR_FORCE_V 0x1 +#define RTC_CNTL_VDD_SPI_PWR_FORCE_S 2 + +/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ + +#define RTC_CNTL_VDD_SPI_PWR_DRV 0x00000003 +#define RTC_CNTL_VDD_SPI_PWR_DRV_M ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S)) +#define RTC_CNTL_VDD_SPI_PWR_DRV_V 0x3 +#define RTC_CNTL_VDD_SPI_PWR_DRV_S 0 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x008C) + +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ + +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ + +/* Description: digital core force ISO */ + +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 + +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ + +/* Description: wifi force no ISO */ + +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 + +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ + +/* Description: wifi force ISO */ + +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 + +/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ + +/* Description: cpu force no ISO */ + +#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 + +/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ + +/* Description: cpu force ISO */ + +#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x1 +#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 + +/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ + +#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 + +/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ + +#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 + +/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ + +#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_BT_FORCE_NOISO_V 0x1 +#define RTC_CNTL_BT_FORCE_NOISO_S 23 + +/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ + +#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_BT_FORCE_ISO_V 0x1 +#define RTC_CNTL_BT_FORCE_ISO_S 22 + +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ + +/* Description: digital pad force hold */ + +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 + +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ + +/* Description: digital pad force un-hold */ + +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 + +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ + +/* Description: digital pad force ISO */ + +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 + +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +/* Description: digital pad force no ISO */ + +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 + +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ + +/* Description: digital pad enable auto-hold */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 + +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ + +/* Description: wtite only register to clear digital pad auto-hold */ + +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 + +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ + +/* Description: read only register to indicate digital pad auto-hold status */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 + +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ + +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 + +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ + +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0090) + +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 + +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ + +/* Description: 1: interrupt stage en */ + +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 + +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ + +/* Description: 1: interrupt stage en */ + +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 + +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ + +/* Description: 1: interrupt stage en */ + +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 + +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ + +/* Description: 1: interrupt stage en */ + +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 + +/* RTC_CNTL_WDT_STGX : */ + +/* Description: stage action selection values */ + +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ + +/* Description: CPU reset counter length */ + +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 + +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ + +/* Description: system reset counter length */ + +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 + +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ + +/* Description: enable WDT in flash boot */ + +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 + +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ + +/* Description: enable WDT reset PRO CPU */ + +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 + +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ + +/* Description: enable WDT reset APP CPU */ + +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 + +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ + +/* Description: pause WDT in sleep */ + +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 + +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: wdt reset whole chip enable */ + +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 + +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ + +/* Description: chip reset siginal pulse width */ + +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0094) + +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ + +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x0098) + +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ + +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x009C) + +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ + +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A0) + +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ + +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A4) + +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ + +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00A8) + +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ + +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00AC) + +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: automatically feed swd when int comes */ + +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 + +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: disabel SWD */ + +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 + +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Sw feed swd */ + +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 + +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: reset swd reset flag */ + +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 + +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ + +/* Description: adjust signal width send to swd */ + +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 + +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 + +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: swd interrupt for feeding */ + +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 + +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: swd reset flag */ + +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B0) + +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ + +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B4) + +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ + +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 + +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ + +/* Description: {reg_sw_stall_appcpu_c1[5:0] */ + +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00B8) + +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00BC) + +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C0) + +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C4) + +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00C8) + +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ + +/* Description: RTC main state machine status */ + +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 + +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in idle state */ + +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 + +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in sleep state */ + +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in wait xtal state */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in wait PLL state */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in wait 8m state */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 + +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in the states of low power */ + +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 + +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in the states of wakeup process */ + +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 + +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: RTC main state machine has been waited for some cycles */ + +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 + +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: RTC is ready to receive wake up trigger from wake up source */ + +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: RTC main state machine is in states that PLL + * should be running + */ + +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 + +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: no use any more */ + +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 + +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: ULP/COCPU is done */ + +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 + +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: ULP/COCPU is in sleep state */ + +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 + +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: ULP/COCPU is about to working. Switch RTC main state */ + +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 + +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: ULP/COCPU should start to work */ + +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 + +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: touch is done */ + +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 + +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: touch is in sleep state */ + +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 + +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: touch is about to working. Switch RTC main state */ + +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 + +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: touch should start to work */ + +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 + +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: digital wrap power down */ + +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 + +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: digital wrap iso */ + +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 + +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: wifi wrap power down */ + +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 + +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: wifi iso */ + +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 + +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: RTC peripheral power down */ + +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 + +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: RTC peripheral iso */ + +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 + +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: External DCDC power down */ + +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 + +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: rom0 power down */ + +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00CC) + +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ + +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D0) + +/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN5_HOLD (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN5_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN5_HOLD_S 5 + +/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN4_HOLD (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN4_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN4_HOLD_S 4 + +/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN3_HOLD (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN3_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN3_HOLD_S 3 + +/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN2_HOLD (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN2_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN2_HOLD_S 2 + +/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN1_HOLD (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_M (BIT(1)) +#define RTC_CNTL_GPIO_PIN1_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN1_HOLD_S 1 + +/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN0_HOLD (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_M (BIT(0)) +#define RTC_CNTL_GPIO_PIN0_HOLD_V 0x1 +#define RTC_CNTL_GPIO_PIN0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) + +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00D8) + +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 + +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ + +/* Description: enable brown out */ + +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 + +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: clear brown out counter */ + +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 + +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 + +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: 1: 4-pos reset */ + +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 + +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: enable brown out reset */ + +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 + +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ + +/* Description: brown out reset wait cycles */ + +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 + +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: enable power down RF when brown out happens */ + +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 + +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: enable close flash when brown out happens */ + +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ + +/* Description: brown out interrupt wait cycles */ + +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) + +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: RTC timer low 32 bits */ + +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00E0) + +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ + +/* Description: RTC timer high 16 bits */ + +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00E4) + +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: xtal 32k watch dog backup clock factor */ + +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00E8) + +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ + +/* Description: if restarted xtal32k period is smaller than this */ + +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 + +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ + +/* Description: If no clock detected for this amount of time */ + +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 + +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ + +/* Description: cycles to wait to repower on xtal 32k */ + +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 + +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ + +/* Description: cycles to wait to return noral xtal 32k */ + +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00EC) + +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ + +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F0) + +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ + +/* Description: sleep reject cause */ + +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x00F4) + +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ + +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x00F8) + +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ + +/* Description: sleep wakeup cause */ + +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x00FC) + +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ + +/* Description: sleep cycles for ULP-coprocessor timer */ + +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0100) + +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: enbale gitch det interrupt */ + +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: enable xtal32k_dead interrupt */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 + +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: enable super watch dog interrupt */ + +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: enable RTC main timer interrupt */ + +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: enable brown out interrupt */ + +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 + +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: enable RTC WDT interrupt */ + +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: enable sleep reject interrupt */ + +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: enable sleep wakeup interrupt */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0104) + +/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ + +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S 20 + +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: enbale gitch det interrupt */ + +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: enable xtal32k_dead interrupt */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 + +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: enable super watch dog interrupt */ + +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 + +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: enable RTC main timer interrupt */ + +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ + +/* Description: enable brown out interrupt */ + +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 + +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: enable RTC WDT interrupt */ + +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 + +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: enable sleep reject interrupt */ + +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: enable sleep wakeup interrupt */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0108) + +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ + +/* Description: wait cycles for retention operation */ + +#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x1F +#define RTC_CNTL_RETENTION_WAIT_S 27 + +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ + +#define RTC_CNTL_RETENTION_EN (BIT(26)) +#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 26 + +/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */ + +#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000F +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S)) +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0xF +#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 22 + +/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */ + +#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 +#define RTC_CNTL_RETENTION_DONE_WAIT_M ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S)) +#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x7 +#define RTC_CNTL_RETENTION_DONE_WAIT_S 19 + +/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +#define RTC_CNTL_RETENTION_CLK_SEL (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_M (BIT(18)) +#define RTC_CNTL_RETENTION_CLK_SEL_V 0x1 +#define RTC_CNTL_RETENTION_CLK_SEL_S 18 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x010C) + +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ + +/* Description: select use analog fib signal */ + +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) + +/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(31)) +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S 31 + +/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(30)) +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S 30 + +/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(29)) +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S 29 + +/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(28)) +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S 28 + +/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(27)) +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S 27 + +/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(26)) +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S 26 + +/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S 23 + +/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S 20 + +/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S 17 + +/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S 14 + +/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S 11 + +/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */ + +#define RTC_CNTL_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S)) +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S 8 + +/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN_CLK_GATE (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN_CLK_GATE_V 0x1 +#define RTC_CNTL_GPIO_PIN_CLK_GATE_S 7 + +/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M (BIT(6)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S 6 + +/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */ + +#define RTC_CNTL_GPIO_WAKEUP_STATUS 0x0000003F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_M ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S)) +#define RTC_CNTL_GPIO_WAKEUP_STATUS_V 0x3F +#define RTC_CNTL_GPIO_WAKEUP_STATUS_S 0 + +#define RTC_CNTL_DBG_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0114) + +/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_SEL4 0x0000001F +#define RTC_CNTL_DEBUG_SEL4_M ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S)) +#define RTC_CNTL_DEBUG_SEL4_V 0x1F +#define RTC_CNTL_DEBUG_SEL4_S 27 + +/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_SEL3 0x0000001F +#define RTC_CNTL_DEBUG_SEL3_M ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S)) +#define RTC_CNTL_DEBUG_SEL3_V 0x1F +#define RTC_CNTL_DEBUG_SEL3_S 22 + +/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_SEL2 0x0000001F +#define RTC_CNTL_DEBUG_SEL2_M ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S)) +#define RTC_CNTL_DEBUG_SEL2_V 0x1F +#define RTC_CNTL_DEBUG_SEL2_S 17 + +/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_SEL1 0x0000001F +#define RTC_CNTL_DEBUG_SEL1_M ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S)) +#define RTC_CNTL_DEBUG_SEL1_V 0x1F +#define RTC_CNTL_DEBUG_SEL1_S 12 + +/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_SEL0 0x0000001F +#define RTC_CNTL_DEBUG_SEL0_M ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S)) +#define RTC_CNTL_DEBUG_SEL0_V 0x1F +#define RTC_CNTL_DEBUG_SEL0_S 7 + +/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */ + +#define RTC_CNTL_DEBUG_BIT_SEL 0x0000001F +#define RTC_CNTL_DEBUG_BIT_SEL_M ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S)) +#define RTC_CNTL_DEBUG_BIT_SEL_V 0x1F +#define RTC_CNTL_DEBUG_BIT_SEL_S 2 + +/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define RTC_CNTL_DEBUG_12M_NO_GATING (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_M (BIT(1)) +#define RTC_CNTL_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_CNTL_DEBUG_12M_NO_GATING_S 1 + +#define RTC_CNTL_DBG_MAP_REG (DR_REG_RTCCNTL_BASE + 0x0118) + +/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN0_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S 28 + +/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN1_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S 24 + +/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN2_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S 20 + +/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN3_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S 16 + +/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN4_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S 12 + +/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ + +#define RTC_CNTL_GPIO_PIN5_FUN_SEL 0x0000000F +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S)) +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V 0xF +#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S 8 + +/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN0_MUX_SEL (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M (BIT(7)) +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S 7 + +/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN1_MUX_SEL (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M (BIT(6)) +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S 6 + +/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN2_MUX_SEL (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M (BIT(5)) +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S 5 + +/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN3_MUX_SEL (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M (BIT(4)) +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S 4 + +/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN4_MUX_SEL (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M (BIT(3)) +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S 3 + +/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define RTC_CNTL_GPIO_PIN5_MUX_SEL (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M (BIT(2)) +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V 0x1 +#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S 2 + +#define RTC_CNTL_SENSOR_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x011C) + +/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ + +#define RTC_CNTL_FORCE_XPD_SAR 0x00000003 +#define RTC_CNTL_FORCE_XPD_SAR_M ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S)) +#define RTC_CNTL_FORCE_XPD_SAR_V 0x3 +#define RTC_CNTL_FORCE_XPD_SAR_S 30 + +/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */ + +#define RTC_CNTL_SAR2_PWDET_CCT 0x00000007 +#define RTC_CNTL_SAR2_PWDET_CCT_M ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S)) +#define RTC_CNTL_SAR2_PWDET_CCT_V 0x7 +#define RTC_CNTL_SAR2_PWDET_CCT_S 27 + +#define RTC_CNTL_DBG_SAR_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0120) + +/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ + +#define RTC_CNTL_SAR_DEBUG_SEL 0x0000001F +#define RTC_CNTL_SAR_DEBUG_SEL_M ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S)) +#define RTC_CNTL_SAR_DEBUG_SEL_V 0x1F +#define RTC_CNTL_SAR_DEBUG_SEL_S 27 + +#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0124) + +/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_M (BIT(31)) +#define RTC_CNTL_POWER_GLITCH_EN_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EN_S 31 + +/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (BIT(30)) +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x1 +#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 + +/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 + +/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x1 +#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 + +/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ + +#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 +#define RTC_CNTL_POWER_GLITCH_DSENSE_M ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S)) +#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x3 +#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x01fc) + +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */ + +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h new file mode 100644 index 0000000000..c050d0b80c --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h @@ -0,0 +1,529 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Offset relative to each watchdog timer instance memory base */ + +#define MWDT_CONFIG0_OFFSET 0x0048 + +/* MWDT */ + +#define MWDT_CLK_PRESCALE_OFFSET 0x004c +#define MWDT_STAGE0_TIMEOUT_OFFSET 0x0050 +#define MWDT_STAGE1_TIMEOUT_OFFSET 0x0054 +#define MWDT_STAGE2_TIMEOUT_OFFSET 0x0058 +#define MWDT_STAGE3_TIMEOUT_OFFSET 0x005c +#define MWDT_FEED_OFFSET 0x0060 +#define MWDT_WP_REG 0x0064 +#define MWDT_INT_ENA_REG_OFFSET 0x0070 +#define MWDT_INT_CLR_REG_OFFSET 0x007c + +/* The value that needs to be written to TIMG_WDT_WKEY to + * write-enable the WDT registers. + */ + +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ + +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) + +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 + +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 + +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 + +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ + +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 + +/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */ + +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (BIT(12)) +#define TIMG_T0_DIVCNT_RST_V 0x1 +#define TIMG_T0_DIVCNT_RST_S 12 + +/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */ + +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 + +/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ + +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (BIT(9)) +#define TIMG_T0_USE_XTAL_V 0x1 +#define TIMG_T0_USE_XTAL_S 9 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) + +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) + +/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_HI 0x003FFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0x3FFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) + +/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (BIT(31)) +#define TIMG_T0_UPDATE_V 0x1 +#define TIMG_T0_UPDATE_S 31 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) + +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) + +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_ALARM_HI 0x003FFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0x3FFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) + +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) + +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_LOAD_HI 0x003FFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0x3FFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) + +/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) + +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 + +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 + +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 + +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 + +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 + +/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */ + +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x1 +#define TIMG_WDT_CONF_UPDATE_EN_S 22 + +/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */ + +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (BIT(21)) +#define TIMG_WDT_USE_XTAL_V 0x1 +#define TIMG_WDT_USE_XTAL_S 21 + +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ + +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 + +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ + +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 + +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ + +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ + +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 + +/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ + +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) + +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ + +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */ + +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_V 0x1 +#define TIMG_WDT_DIVCNT_RST_S 0 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) + +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ + +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) + +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ + +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) + +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) + +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) + +/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) + +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ + +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) + +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ + +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 + +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) + +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ + +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) + +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_ENA (BIT(1)) +#define TIMG_WDT_INT_ENA_M (BIT(1)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 1 + +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) + +/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_RAW (BIT(1)) +#define TIMG_WDT_INT_RAW_M (BIT(1)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 1 + +/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) + +/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_ST (BIT(1)) +#define TIMG_WDT_INT_ST_M (BIT(1)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 1 + +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) + +/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_CLR (BIT(1)) +#define TIMG_WDT_INT_CLR_M (BIT(1)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 1 + +/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) + +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ + +/* description: timeout if cali value counts over threshold */ + +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S)) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ + +/* description: Cycles that release calibration timeout reset */ + +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 + +/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ + +/* description: timeout indicator */ + +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_V 0x1 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) + +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */ + +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) + +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + +/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1 +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 + +/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1 +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt index cc0c936634..1e6c8c8bdf 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/README.txt +++ b/boards/risc-v/esp32c3/esp32c3-devkit/README.txt @@ -96,6 +96,33 @@ Configurations The pin is configured as a rising edge interrupt, so after issuing the above command, connect it to 3.3V. + watchdog + -------- + + This configuration tests the watchdog timers. It includes the 2 MWDTS, + adds driver support, registers the WDTs as devices and includes the watchdog + example application. + + To test it, just run the following command: + + `nsh> wdog -i /dev/watchdogX` + + Where X ix the watchdog instance. + + watcher + ------- + + This configuration tests the watchdog timers in the capture mode. + It includes the 2 MWDTS, adds driver support, registers the WDTs as devices + and includes the watcher and watched example applications. + + To test it, just run the following command: + + ``` + nsh> watcher + nsh> watched + ``` + Building and flashing ===================== diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig new file mode 100644 index 0000000000..67bda480ac --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_MWDT0=y +CONFIG_ESP32C3_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MAX_TASKS=8 +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig new file mode 100644 index 0000000000..881af555e1 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVER_NOTE=y +CONFIG_ESP32C3_MWDT0=y +CONFIG_ESP32C3_MWDT1=y +CONFIG_EXAMPLES_WATCHER=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MAX_TASKS=8 +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile index 30f927332d..74633f6342 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile @@ -34,6 +34,10 @@ ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += esp32c3_gpio.c endif +ifeq ($(CONFIG_WATCHDOG),y) +CSRCS += esp32c3_wdt.c +endif + SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32c3.template.ld SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h index e35f38dcb2..545312714c 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h @@ -25,9 +25,7 @@ * Included Files ****************************************************************************/ -#include #include -#include /**************************************************************************** * Pre-processor Definitions @@ -71,5 +69,21 @@ int esp32c3_bringup(void); int esp32c3_gpio_init(void); #endif +/**************************************************************************** + * Name: board_wdt_init + * + * Description: + * Configure the timer driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_WATCHDOG +int board_wdt_init(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_SRC_ESP32C3_DEVKIT_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c index cea847ac64..0db8143243 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c @@ -22,15 +22,6 @@ * Included Files ****************************************************************************/ -#include - -#include - -#include -#include - -#include "esp32c3-devkit.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index fdcd1401d2..bb651c6876 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -85,6 +85,18 @@ int esp32c3_bringup(void) } #endif +#ifdef CONFIG_WATCHDOG + /* Configure watchdog timer */ + + ret = board_wdt_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize watchdog drivers: %d\n", + ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c new file mode 100644 index 0000000000..f4d19a14cc --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_wdt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32c3_wdt_lowerhalf.h" +#include "esp32c3_wdt.h" + +#include "esp32c3-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_wdt_init + * + * Description: + * Configure the watchdog timer driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_wdt_init(void) +{ + int ret = OK; + +#ifdef CONFIG_ESP32C3_MWDT0 + ret = esp32c3_wdt_initialize("/dev/watchdog0", ESP32C3_WDT_MWDT0); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize watchdog driver: %d\n", + ret); + return ret; + } +#endif /* CONFIG_ESP32C3_MWDT0 */ + +#ifdef CONFIG_ESP32C3_MWDT1 + ret = esp32c3_wdt_initialize("/dev/watchdog1", ESP32C3_WDT_MWDT1); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize watchdog driver: %d\n", + ret); + return ret; + } +#endif /* CONFIG_ESP32C3_MWDT1 */ + +#ifdef CONFIG_ESP32C3_RWDT + ret = esp32c3_wdt_initialize("/dev/watchdog2", ESP32C3_WDT_RWDT); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize watchdog driver: %d\n", + ret); + return ret; + } +#endif /* CONFIG_ESP32C3_RWDT */ + + return ret; +} +