diff --git a/arch/arm/src/samd/chip/sam_fuses.h b/arch/arm/src/samd/chip/sam_fuses.h new file mode 100644 index 0000000000..ffd606e20f --- /dev/null +++ b/arch/arm/src/samd/chip/sam_fuses.h @@ -0,0 +1,258 @@ +/******************************************************************************************** + * arch/arm/src/samd/chip/sam_fuses.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * + * Fuse-related definitions derive from Atmel sample code: + * + * Copyright (c) 2013 Atmel Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H +#define __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* Fuse definitions *************************************************************************/ + +#define ADC_FUSES_BIASCAL_ADDR (SAM_AUX1_AREA4 + 4) +#define ADC_FUSES_BIASCAL_SHIFT (3) /* ADC Bias Calibration */ +#define ADC_FUSES_BIASCAL_MASK (7 << ADC_FUSES_BIASCAL_SHIFT) +# define ADC_FUSES_BIASCAL(n) ((n) << ADC_FUSES_BIASCAL_SHIFT) + +#define ADC_FUSES_BIAS_OPA_ADDR (SAM_AUX1_AREA2 + 4) +#define ADC_FUSES_BIAS_OPA_SHIFT (19) /* ADC OPA Bias */ +#define ADC_FUSES_BIAS_OPA_MASK (1 << ADC_FUSES_BIAS_OPA_SHIFT) + +#define ADC_FUSES_BOOSTEN_ADDR (SAM_AUX1_AREA2 + 4) +#define ADC_FUSES_BOOSTEN_SHIFT (17) /* ADC Boost Enable */ +#define ADC_FUSES_BOOSTEN_MASK (1 << ADC_FUSES_BOOSTEN_SHIFT) + +#define ADC_FUSES_CMPDELAY_ADDR (SAM_AUX1_AREA2 + 4) +#define ADC_FUSES_CMPDELAY_SHIFT (16) /* ADC Comparator Delay */ +#define ADC_FUSES_CMPDELAY_MASK (1 << ADC_FUSES_CMPDELAY_SHIFT) + +#define ADC_FUSES_DCFG_ADDR (SAM_AUX1_AREA2 + 4) +#define ADC_FUSES_DCFG_SHIFT (16) /* ADC Device Configuration */ +#define ADC_FUSES_DCFG_MASK (15 << ADC_FUSES_DCFG_SHIFT) +# define ADC_FUSES_DCFG(n) ((n) << ADC_FUSES_DCFG_SHIFT) + +#define ADC_FUSES_GAINCORR_ADDR (SAM_AUX1_AREA4 + 0) +#define ADC_FUSES_GAINCORR_SHIFT (3) /* ADC Gain Correction */ +#define ADC_FUSES_GAINCORR_MASK (0xfff << ADC_FUSES_GAINCORR_SHIFT) +# define ADC_FUSES_GAINCORR(n) ((n) << ADC_FUSES_GAINCORR_SHIFT) + +#define ADC_FUSES_LINEARITY_0_ADDR (SAM_AUX1_AREA4 + 0) +#define ADC_FUSES_LINEARITY_0_SHIFT (27) /* ADC Linearity bits 4:0 */ +#define ADC_FUSES_LINEARITY_0_MASK (0x1f << ADC_FUSES_LINEARITY_0_SHIFT) +# define ADC_FUSES_LINEARITY_0(n) ((n) << ADC_FUSES_LINEARITY_0_SHIFT) + +#define ADC_FUSES_LINEARITY_1_ADDR (SAM_AUX1_AREA4 + 4) +#define ADC_FUSES_LINEARITY_1_SHIFT (0) /* ADC Linearity bits 7:5 */ +#define ADC_FUSES_LINEARITY_1_MASK (7 << ADC_FUSES_LINEARITY_1_SHIFT) +# define ADC_FUSES_LINEARITY_1(n) ((n) << ADC_FUSES_LINEARITY_1_SHIFT) + +#define ADC_FUSES_OFFSETCORR_ADDR (SAM_AUX1_AREA4 + 0) +#define ADC_FUSES_OFFSETCORR_SHIFT (15) /* ADC Offset Correction */ +#define ADC_FUSES_OFFSETCORR_MASK (0xfff << ADC_FUSES_OFFSETCORR_SHIFT) +# define ADC_FUSES_OFFSETCORR(n) ((n) << ADC_FUSES_OFFSETCORR_SHIFT) + +#define ADC_FUSES_VCMPULSE_ADDR (SAM_AUX1_AREA2 + 4) +#define ADC_FUSES_VCMPULSE_SHIFT (18) /* ADC VCM Pulse */ +#define ADC_FUSES_VCMPULSE_MASK (1 << ADC_FUSES_VCMPULSE_SHIFT) + +#define DSU_FUSES_DCFG0_ADDR (SAM_AUX1_AREA2 + 0) +#define DSU_FUSES_DCFG0_SHIFT (0) /* Device Configuration 0 */ +#define DSU_FUSES_DCFG0_MASK (0xffffffff << DSU_FUSES_DCFG0_SHIFT) +# define DSU_FUSES_DCFG0(n) ((n) << DSU_FUSES_DCFG0_SHIFT) + +#define DSU_FUSES_DCFG1_ADDR (SAM_AUX1_AREA2 + 4) +#define DSU_FUSES_DCFG1_SHIFT (0) /* Device Configuration 1 */ +#define DSU_FUSES_DCFG1_MASK (0xffffffff << DSU_FUSES_DCFG1_SHIFT) +# define DSU_FUSES_DCFG1(n) ((n) << DSU_FUSES_DCFG1_SHIFT) + +#define DSU_FUSES_DEV_FAMILY_CFG_0_ADDR (SAM_AUX1_AREA2 + 0) +#define DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT (5) /* Device Family Configuration bits 26:0 */ +#define DSU_FUSES_DEV_FAMILY_CFG_0_MASK (0x7ffffff << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT) +# define DSU_FUSES_DEV_FAMILY_CFG_0(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT) + +#define DSU_FUSES_DEV_FAMILY_CFG_1_ADDR (SAM_AUX1_AREA2 + 4) +#define DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT (0) /* Device Family Configuration bits 42:27 */ +#define DSU_FUSES_DEV_FAMILY_CFG_1_MASK (0xffff << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT) +# define DSU_FUSES_DEV_FAMILY_CFG_1(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT) + +#define DSU_FUSES_DID_DEVSEL_ADDR (SAM_AUX1_AREA2 + 0) +#define DSU_FUSES_DID_DEVSEL_SHIFT (0) /* Device Number */ +#define DSU_FUSES_DID_DEVSEL_MASK (0x1f << DSU_FUSES_DID_DEVSEL_SHIFT) +# define DSU_FUSES_DID_DEVSEL(n) ((n) << DSU_FUSES_DID_DEVSEL_SHIFT) + +#define DSU_FUSES_RAM_BIAS_ADDR (SAM_AUX1_AREA2 + 4) +#define DSU_FUSES_RAM_BIAS_SHIFT (20) /* RAM Bias */ +#define DSU_FUSES_RAM_BIAS_MASK (3 << DSU_FUSES_RAM_BIAS_SHIFT) +# define DSU_FUSES_RAM_BIAS(n) ((n) << DSU_FUSES_RAM_BIAS_SHIFT) + +#define DSU_FUSES_RAM_READ_MARGIN_ADDR (SAM_AUX1_AREA2 + 4) +#define DSU_FUSES_RAM_READ_MARGIN_SHIFT (22) /* RAM Read Margin */ +#define DSU_FUSES_RAM_READ_MARGIN_MASK (15 << DSU_FUSES_RAM_READ_MARGIN_SHIFT) +# define DSU_FUSES_RAM_READ_MARGIN(n) ((n) << DSU_FUSES_RAM_READ_MARGIN_SHIFT) + +#define NVMCTRL_FUSES_BOOTPROT_ADDR (SAM_AUX0_BASE + 0) +#define NVMCTRL_FUSES_BOOTPROT_SHIFT (0) /* Bootloader Size */ +#define NVMCTRL_FUSES_BOOTPROT_MASK (7 << NVMCTRL_FUSES_BOOTPROT_SHIFT) +# define NVMCTRL_FUSES_BOOTPROT(n) ((n) << NVMCTRL_FUSES_BOOTPROT_SHIFT) + +#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR (SAM_AUX0_BASE + 0) +#define NVMCTRL_FUSES_EEPROM_SIZE_SHIFT (4) /* EEPROM Size */ +#define NVMCTRL_FUSES_EEPROM_SIZE_MASK (7 << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT) +# define NVMCTRL_FUSES_EEPROM_SIZE(n) ((n) << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT) + +#define NVMCTRL_FUSES_LOCKFIELD_ADDR (SAM_LOCKBIT_BASE + 0) +#define NVMCTRL_FUSES_LOCKFIELD_SHIFT (0) /* LOCK Region */ +#define NVMCTRL_FUSES_LOCKFIELD_MASK (0xff << NVMCTRL_FUSES_LOCKFIELD_SHIFT) +# define NVMCTRL_FUSES_LOCKFIELD(n) ((n) << NVMCTRL_FUSES_LOCKFIELD_SHIFT) + +#define NVMCTRL_FUSES_NVMP_ADDR (SAM_AUX1_AREA1 + 0) +#define NVMCTRL_FUSES_NVMP_SHIFT (16 /* Number of NVM Pages */ +#define NVMCTRL_FUSES_NVMP_MASK (0xffff << NVMCTRL_FUSES_NVMP_SHIFT) +# define NVMCTRL_FUSES_NVMP(n) ((n) << NVMCTRL_FUSES_NVMP_SHIFT) + +#define NVMCTRL_FUSES_NVM_LOCK_ADDR (SAM_AUX1_AREA1 + 0) +#define NVMCTRL_FUSES_NVM_LOCK_SHIFT (0) /* NVM Lock */ +#define NVMCTRL_FUSES_NVM_LOCK_MASK (0xff << NVMCTRL_FUSES_NVM_LOCK_SHIFT) +# define NVMCTRL_FUSES_NVM_LOCK(n) ((n) << NVMCTRL_FUSES_NVM_LOCK_SHIFT) + +#define NVMCTRL_FUSES_PSZ_ADDR (SAM_AUX1_AREA1 + 0) +#define NVMCTRL_FUSES_PSZ_SHIFT (8) /* NVM Page Size */ +#define NVMCTRL_FUSES_PSZ_MASK (15 << NVMCTRL_FUSES_PSZ_SHIFT) +# define NVMCTRL_FUSES_PSZ(n) ((n) << NVMCTRL_FUSES_PSZ_SHIFT) + +#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (SAM_AUX0_BASE + 4) +#define NVMCTRL_FUSES_REGION_LOCKS_SHIFT (16) /* NVM Region Locks */ +#define NVMCTRL_FUSES_REGION_LOCKS_MASK (0xffff << NVMCTRL_FUSES_REGION_LOCKS_SHIFT) +# define NVMCTRL_FUSES_REGION_LOCKS(n) ((n) << NVMCTRL_FUSES_REGION_LOCKS_SHIFT) + +#define SYSCTRL_FUSES_OSC32KCAL_ADDR (SAM_AUX1_AREA4 + 4) +#define SYSCTRL_FUSES_OSC32KCAL_SHIFT (6) /* OSC32K Calibration */ +#define SYSCTRL_FUSES_OSC32KCAL_MASK (0x7f << SYSCTRL_FUSES_OSC32KCAL_SHIFT) +# define SYSCTRL_FUSES_OSC32KCAL(n) ((n) << SYSCTRL_FUSES_OSC32KCAL_SHIFT) + +#define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR (SAM_AUX0_BASE + 0) +#define SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT (17) /* BOD12 User Level */ +#define SYSCTRL_FUSES_BOD12USERLEVEL_MASK (0x1f << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT) +# define SYSCTRL_FUSES_BOD12USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT) + +#define SYSCTRL_FUSES_BOD12_ACTION_ADDR (SAM_AUX0_BASE + 0) +#define SYSCTRL_FUSES_BOD12_ACTION_SHIFT (23) /* BOD12 Action */ +#define SYSCTRL_FUSES_BOD12_ACTION_MASK (3 << SYSCTRL_FUSES_BOD12_ACTION_SHIFT) +# define SYSCTRL_FUSES_BOD12_ACTION(n) ((n) << SYSCTRL_FUSES_BOD12_ACTION_SHIFT) + +#define SYSCTRL_FUSES_BOD12_EN_ADDR (SAM_AUX0_BASE + 0) +#define SYSCTRL_FUSES_BOD12_EN_SHIFT (22) /* BOD12 Enable */ +#define SYSCTRL_FUSES_BOD12_EN_MASK (1 << SYSCTRL_FUSES_BOD12_EN_SHIFT) + +#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR (SAM_AUX0_BASE + 8) +#define SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT (8) /* BOD33 User Level */ +#define SYSCTRL_FUSES_BOD33USERLEVEL_MASK (0x3f << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT) +# define SYSCTRL_FUSES_BOD33USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT) + +#define SYSCTRL_FUSES_BOD33_ACTION_ADDR (SAM_AUX0_BASE + 0) +#define SYSCTRL_FUSES_BOD33_ACTION_SHIFT (15) /* BOD33 Action */ +#define SYSCTRL_FUSES_BOD33_ACTION_MASK (3 << SYSCTRL_FUSES_BOD33_ACTION_SHIFT) +# define SYSCTRL_FUSES_BOD33_ACTION(n) ((n) << SYSCTRL_FUSES_BOD33_ACTION_SHIFT) + +#define SYSCTRL_FUSES_BOD33_EN_ADDR (SAM_AUX0_BASE + 0) +#define SYSCTRL_FUSES_BOD33_EN_SHIFT (14) /* BOD33 Enable */ +#define SYSCTRL_FUSES_BOD33_EN_MASK (1 << SYSCTRL_FUSES_BOD33_EN_SHIFT) + +#define SYSCTRL_FUSES_ULPVREG_ADDR (SAM_AUX1_AREA4 + 0) +#define SYSCTRL_FUSES_ULPVREG_SHIFT (0) /* ULP Regulator Fallback Mode */ +#define SYSCTRL_FUSES_ULPVREG_MASK (7 << SYSCTRL_FUSES_ULPVREG_SHIFT) +# define SYSCTRL_FUSES_ULPVREG(n) ((n) << SYSCTRL_FUSES_ULPVREG_SHIFT) + +#define WDT_FUSES_ALWAYSON_ADDR (SAM_AUX0_BASE + 0) +#define WDT_FUSES_ALWAYSON_SHIFT (26) /* WDT Always On */ +#define WDT_FUSES_ALWAYSON_MASK (1 << WDT_FUSES_ALWAYSON_SHIFT) + +#define WDT_FUSES_ENABLE_ADDR (SAM_AUX0_BASE + 0) +#define WDT_FUSES_ENABLE_SHIFT (25) /* WDT Enable */ +#define WDT_FUSES_ENABLE_MASK (1 << WDT_FUSES_ENABLE_SHIFT) + +#define WDT_FUSES_EWOFFSET_ADDR (SAM_AUX0_BASE + 4) +#define WDT_FUSES_EWOFFSET_SHIFT (3) /* WDT Early Warning Offset */ +#define WDT_FUSES_EWOFFSET_MASK (15 << WDT_FUSES_EWOFFSET_SHIFT) +# define WDT_FUSES_EWOFFSET(n) ((n) << WDT_FUSES_EWOFFSET_SHIFT) + +#define WDT_FUSES_PER_ADDR (SAM_AUX0_BASE + 0) +#define WDT_FUSES_PER_SHIFT (27) /* WDT Period */ +#define WDT_FUSES_PER_MASK (15 << WDT_FUSES_PER_SHIFT) +# define WDT_FUSES_PER(n) ((n) << WDT_FUSES_PER_SHIFT) + +#define WDT_FUSES_WEN_ADDR (SAM_AUX0_BASE + 4) +#define WDT_FUSES_WEN_SHIFT (7) /* WDT Window Mode Enable */ +#define WDT_FUSES_WEN_MASK (1 << WDT_FUSES_WEN_SHIFT) + +#define WDT_FUSES_WINDOW_0_ADDR (SAM_AUX0_BASE + 0) +#define WDT_FUSES_WINDOW_0_SHIFT (31) /* WDT Window bit 0 */ +#define WDT_FUSES_WINDOW_0_MASK (1 << WDT_FUSES_WINDOW_0_SHIFT) + +#define WDT_FUSES_WINDOW_1_ADDR (SAM_AUX0_BASE + 4) +#define WDT_FUSES_WINDOW_1_SHIFT (0) /* WDT Window bits 3:1 */ +#define WDT_FUSES_WINDOW_1_MASK (7 << WDT_FUSES_WINDOW_1_SHIFT) +# define WDT_FUSES_WINDOW_1(n) ((n) << WDT_FUSES_WINDOW_1_SHIFT) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_SAMD_CHIP_SAM_NVMCTRL_H */ diff --git a/arch/arm/src/samd/chip/sam_gclk.h b/arch/arm/src/samd/chip/sam_gclk.h index ded483ca83..312982a4ca 100644 --- a/arch/arm/src/samd/chip/sam_gclk.h +++ b/arch/arm/src/samd/chip/sam_gclk.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/chip/sam_nvmctrl.h b/arch/arm/src/samd/chip/sam_nvmctrl.h index 48437ab386..6bacb8c22d 100644 --- a/arch/arm/src/samd/chip/sam_nvmctrl.h +++ b/arch/arm/src/samd/chip/sam_nvmctrl.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -47,7 +51,7 @@ /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ -/* NVMCTRL register offsets ********************************************************************/ +/* NVMCTRL register offsets *****************************************************************/ #define SAM_NVMCTRL_CTRLA_OFFSET 0x0000 /* Control A register */ #define SAM_NVMCTRL_CTRLB_OFFSET 0x0004 /* Control B register */ @@ -59,7 +63,7 @@ #define SAM_NVMCTRL_ADDR_OFFSET 0x001c /* Address register */ #define SAM_NVMCTRL_LOCK_OFFSET 0x0020 /* Lock section register */ -/* NVMCTRL register addresses ******************************************************************/ +/* NVMCTRL register addresses ***************************************************************/ #define SAM_NVMCTRL_CTRLA (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLA_OFFSET) #define SAM_NVMCTRL_CTRLB (SAM_NVMCTRL_BASE+SAM_NVMCTRL_CTRLB_OFFSET) @@ -71,7 +75,7 @@ #define SAM_NVMCTRL_ADDR (SAM_NVMCTRL_BASE+SAM_NVMCTRL_ADDR_OFFSET) #define SAM_NVMCTRL_LOCK (SAM_NVMCTRL_BASE+SAM_NVMCTRL_LOCK_OFFSET) -/* NVMCTRL register bit definitions ************************************************************/ +/* NVMCTRL register bit definitions *********************************************************/ /* Control A register */ @@ -150,193 +154,6 @@ #define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */ -/* Fuse definitions *************************************************************************/ - -#define ADC_FUSES_BIASCAL_ADDR (SAM_AUX1_AREA4 + 4) -#define ADC_FUSES_BIASCAL_SHIFT (3) /* ADC Bias Calibration */ -#define ADC_FUSES_BIASCAL_MASK (7 << ADC_FUSES_BIASCAL_SHIFT) -# define ADC_FUSES_BIASCAL(n) ((n) << ADC_FUSES_BIASCAL_SHIFT) - -#define ADC_FUSES_BIAS_OPA_ADDR (SAM_AUX1_AREA2 + 4) -#define ADC_FUSES_BIAS_OPA_SHIFT (19) /* ADC OPA Bias */ -#define ADC_FUSES_BIAS_OPA_MASK (1 << ADC_FUSES_BIAS_OPA_SHIFT) - -#define ADC_FUSES_BOOSTEN_ADDR (SAM_AUX1_AREA2 + 4) -#define ADC_FUSES_BOOSTEN_SHIFT (17) /* ADC Boost Enable */ -#define ADC_FUSES_BOOSTEN_MASK (1 << ADC_FUSES_BOOSTEN_SHIFT) - -#define ADC_FUSES_CMPDELAY_ADDR (SAM_AUX1_AREA2 + 4) -#define ADC_FUSES_CMPDELAY_SHIFT (16) /* ADC Comparator Delay */ -#define ADC_FUSES_CMPDELAY_MASK (1 << ADC_FUSES_CMPDELAY_SHIFT) - -#define ADC_FUSES_DCFG_ADDR (SAM_AUX1_AREA2 + 4) -#define ADC_FUSES_DCFG_SHIFT (16) /* ADC Device Configuration */ -#define ADC_FUSES_DCFG_MASK (15 << ADC_FUSES_DCFG_SHIFT) -# define ADC_FUSES_DCFG(n) ((n) << ADC_FUSES_DCFG_SHIFT) - -#define ADC_FUSES_GAINCORR_ADDR (SAM_AUX1_AREA4 + 0) -#define ADC_FUSES_GAINCORR_SHIFT (3) /* ADC Gain Correction */ -#define ADC_FUSES_GAINCORR_MASK (0xfff << ADC_FUSES_GAINCORR_SHIFT) -# define ADC_FUSES_GAINCORR(n) ((n) << ADC_FUSES_GAINCORR_SHIFT) - -#define ADC_FUSES_LINEARITY_0_ADDR (SAM_AUX1_AREA4 + 0) -#define ADC_FUSES_LINEARITY_0_SHIFT (27) /* ADC Linearity bits 4:0 */ -#define ADC_FUSES_LINEARITY_0_MASK (0x1f << ADC_FUSES_LINEARITY_0_SHIFT) -# define ADC_FUSES_LINEARITY_0(n) ((n) << ADC_FUSES_LINEARITY_0_SHIFT) - -#define ADC_FUSES_LINEARITY_1_ADDR (SAM_AUX1_AREA4 + 4) -#define ADC_FUSES_LINEARITY_1_SHIFT (0) /* ADC Linearity bits 7:5 */ -#define ADC_FUSES_LINEARITY_1_MASK (7 << ADC_FUSES_LINEARITY_1_SHIFT) -# define ADC_FUSES_LINEARITY_1(n) ((n) << ADC_FUSES_LINEARITY_1_SHIFT) - -#define ADC_FUSES_OFFSETCORR_ADDR (SAM_AUX1_AREA4 + 0) -#define ADC_FUSES_OFFSETCORR_SHIFT (15) /* ADC Offset Correction */ -#define ADC_FUSES_OFFSETCORR_MASK (0xfff << ADC_FUSES_OFFSETCORR_SHIFT) -# define ADC_FUSES_OFFSETCORR(n) ((n) << ADC_FUSES_OFFSETCORR_SHIFT) - -#define ADC_FUSES_VCMPULSE_ADDR (SAM_AUX1_AREA2 + 4) -#define ADC_FUSES_VCMPULSE_SHIFT (18) /* ADC VCM Pulse */ -#define ADC_FUSES_VCMPULSE_MASK (1 << ADC_FUSES_VCMPULSE_SHIFT) - -#define DSU_FUSES_DCFG0_ADDR (SAM_AUX1_AREA2 + 0) -#define DSU_FUSES_DCFG0_SHIFT (0) /* Device Configuration 0 */ -#define DSU_FUSES_DCFG0_MASK (0xffffffff << DSU_FUSES_DCFG0_SHIFT) -# define DSU_FUSES_DCFG0(n) ((n) << DSU_FUSES_DCFG0_SHIFT) - -#define DSU_FUSES_DCFG1_ADDR (SAM_AUX1_AREA2 + 4) -#define DSU_FUSES_DCFG1_SHIFT (0) /* Device Configuration 1 */ -#define DSU_FUSES_DCFG1_MASK (0xffffffff << DSU_FUSES_DCFG1_SHIFT) -# define DSU_FUSES_DCFG1(n) ((n) << DSU_FUSES_DCFG1_SHIFT) - -#define DSU_FUSES_DEV_FAMILY_CFG_0_ADDR (SAM_AUX1_AREA2 + 0) -#define DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT (5) /* Device Family Configuration bits 26:0 */ -#define DSU_FUSES_DEV_FAMILY_CFG_0_MASK (0x7ffffff << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT) -# define DSU_FUSES_DEV_FAMILY_CFG_0(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT) - -#define DSU_FUSES_DEV_FAMILY_CFG_1_ADDR (SAM_AUX1_AREA2 + 4) -#define DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT (0) /* Device Family Configuration bits 42:27 */ -#define DSU_FUSES_DEV_FAMILY_CFG_1_MASK (0xffff << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT) -# define DSU_FUSES_DEV_FAMILY_CFG_1(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT) - -#define DSU_FUSES_DID_DEVSEL_ADDR (SAM_AUX1_AREA2 + 0) -#define DSU_FUSES_DID_DEVSEL_SHIFT (0) /* Device Number */ -#define DSU_FUSES_DID_DEVSEL_MASK (0x1f << DSU_FUSES_DID_DEVSEL_SHIFT) -# define DSU_FUSES_DID_DEVSEL(n) ((n) << DSU_FUSES_DID_DEVSEL_SHIFT) - -#define DSU_FUSES_RAM_BIAS_ADDR (SAM_AUX1_AREA2 + 4) -#define DSU_FUSES_RAM_BIAS_SHIFT (20) /* RAM Bias */ -#define DSU_FUSES_RAM_BIAS_MASK (3 << DSU_FUSES_RAM_BIAS_SHIFT) -# define DSU_FUSES_RAM_BIAS(n) ((n) << DSU_FUSES_RAM_BIAS_SHIFT) - -#define DSU_FUSES_RAM_READ_MARGIN_ADDR (SAM_AUX1_AREA2 + 4) -#define DSU_FUSES_RAM_READ_MARGIN_SHIFT (22) /* RAM Read Margin */ -#define DSU_FUSES_RAM_READ_MARGIN_MASK (15 << DSU_FUSES_RAM_READ_MARGIN_SHIFT) -# define DSU_FUSES_RAM_READ_MARGIN(n) ((n) << DSU_FUSES_RAM_READ_MARGIN_SHIFT) - -#define NVMCTRL_FUSES_BOOTPROT_ADDR (SAM_AUX0_BASE + 0) -#define NVMCTRL_FUSES_BOOTPROT_SHIFT (0) /* Bootloader Size */ -#define NVMCTRL_FUSES_BOOTPROT_MASK (7 << NVMCTRL_FUSES_BOOTPROT_SHIFT) -# define NVMCTRL_FUSES_BOOTPROT(n) ((n) << NVMCTRL_FUSES_BOOTPROT_SHIFT) - -#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR (SAM_AUX0_BASE + 0) -#define NVMCTRL_FUSES_EEPROM_SIZE_SHIFT (4) /* EEPROM Size */ -#define NVMCTRL_FUSES_EEPROM_SIZE_MASK (7 << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT) -# define NVMCTRL_FUSES_EEPROM_SIZE(n) ((n) << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT) - -#define NVMCTRL_FUSES_LOCKFIELD_ADDR (SAM_LOCKBIT_BASE + 0) -#define NVMCTRL_FUSES_LOCKFIELD_SHIFT (0) /* LOCK Region */ -#define NVMCTRL_FUSES_LOCKFIELD_MASK (0xff << NVMCTRL_FUSES_LOCKFIELD_SHIFT) -# define NVMCTRL_FUSES_LOCKFIELD(n) ((n) << NVMCTRL_FUSES_LOCKFIELD_SHIFT) - -#define NVMCTRL_FUSES_NVMP_ADDR (SAM_AUX1_AREA1 + 0) -#define NVMCTRL_FUSES_NVMP_SHIFT (16 /* Number of NVM Pages */ -#define NVMCTRL_FUSES_NVMP_MASK (0xffff << NVMCTRL_FUSES_NVMP_SHIFT) -# define NVMCTRL_FUSES_NVMP(n) ((n) << NVMCTRL_FUSES_NVMP_SHIFT) - -#define NVMCTRL_FUSES_NVM_LOCK_ADDR (SAM_AUX1_AREA1 + 0) -#define NVMCTRL_FUSES_NVM_LOCK_SHIFT (0) /* NVM Lock */ -#define NVMCTRL_FUSES_NVM_LOCK_MASK (0xff << NVMCTRL_FUSES_NVM_LOCK_SHIFT) -# define NVMCTRL_FUSES_NVM_LOCK(n) ((n) << NVMCTRL_FUSES_NVM_LOCK_SHIFT) - -#define NVMCTRL_FUSES_PSZ_ADDR (SAM_AUX1_AREA1 + 0) -#define NVMCTRL_FUSES_PSZ_SHIFT (8) /* NVM Page Size */ -#define NVMCTRL_FUSES_PSZ_MASK (15 << NVMCTRL_FUSES_PSZ_SHIFT) -# define NVMCTRL_FUSES_PSZ(n) ((n) << NVMCTRL_FUSES_PSZ_SHIFT) - -#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (SAM_AUX0_BASE + 4) -#define NVMCTRL_FUSES_REGION_LOCKS_SHIFT (16) /* NVM Region Locks */ -#define NVMCTRL_FUSES_REGION_LOCKS_MASK (0xffff << NVMCTRL_FUSES_REGION_LOCKS_SHIFT) -# define NVMCTRL_FUSES_REGION_LOCKS(n) ((n) << NVMCTRL_FUSES_REGION_LOCKS_SHIFT) - -#define SYSCTRL_FUSES_OSC32KCAL_ADDR (SAM_AUX1_AREA4 + 4) -#define SYSCTRL_FUSES_OSC32KCAL_SHIFT (6) /* OSC32K Calibration */ -#define SYSCTRL_FUSES_OSC32KCAL_MASK (0x7f << SYSCTRL_FUSES_OSC32KCAL_SHIFT) -# define SYSCTRL_FUSES_OSC32KCAL(n) ((n) << SYSCTRL_FUSES_OSC32KCAL_SHIFT) - -#define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR (SAM_AUX0_BASE + 0) -#define SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT (17) /* BOD12 User Level */ -#define SYSCTRL_FUSES_BOD12USERLEVEL_MASK (0x1f << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT) -# define SYSCTRL_FUSES_BOD12USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT) - -#define SYSCTRL_FUSES_BOD12_ACTION_ADDR (SAM_AUX0_BASE + 0) -#define SYSCTRL_FUSES_BOD12_ACTION_SHIFT (23) /* BOD12 Action */ -#define SYSCTRL_FUSES_BOD12_ACTION_MASK (3 << SYSCTRL_FUSES_BOD12_ACTION_SHIFT) -# define SYSCTRL_FUSES_BOD12_ACTION(n) ((n) << SYSCTRL_FUSES_BOD12_ACTION_SHIFT) - -#define SYSCTRL_FUSES_BOD12_EN_ADDR (SAM_AUX0_BASE + 0) -#define SYSCTRL_FUSES_BOD12_EN_SHIFT (22) /* BOD12 Enable */ -#define SYSCTRL_FUSES_BOD12_EN_MASK (1 << SYSCTRL_FUSES_BOD12_EN_SHIFT) - -#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR (SAM_AUX0_BASE + 8) -#define SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT (8) /* BOD33 User Level */ -#define SYSCTRL_FUSES_BOD33USERLEVEL_MASK (0x3f << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT) -# define SYSCTRL_FUSES_BOD33USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT) - -#define SYSCTRL_FUSES_BOD33_ACTION_ADDR (SAM_AUX0_BASE + 0) -#define SYSCTRL_FUSES_BOD33_ACTION_SHIFT (15) /* BOD33 Action */ -#define SYSCTRL_FUSES_BOD33_ACTION_MASK (3 << SYSCTRL_FUSES_BOD33_ACTION_SHIFT) -# define SYSCTRL_FUSES_BOD33_ACTION(n) ((n) << SYSCTRL_FUSES_BOD33_ACTION_SHIFT) - -#define SYSCTRL_FUSES_BOD33_EN_ADDR (SAM_AUX0_BASE + 0) -#define SYSCTRL_FUSES_BOD33_EN_SHIFT (14) /* BOD33 Enable */ -#define SYSCTRL_FUSES_BOD33_EN_MASK (1 << SYSCTRL_FUSES_BOD33_EN_SHIFT) - -#define SYSCTRL_FUSES_ULPVREG_ADDR (SAM_AUX1_AREA4 + 0) -#define SYSCTRL_FUSES_ULPVREG_SHIFT (0) /* ULP Regulator Fallback Mode */ -#define SYSCTRL_FUSES_ULPVREG_MASK (7 << SYSCTRL_FUSES_ULPVREG_SHIFT) -# define SYSCTRL_FUSES_ULPVREG(n) ((n) << SYSCTRL_FUSES_ULPVREG_SHIFT) - -#define WDT_FUSES_ALWAYSON_ADDR (SAM_AUX0_BASE -#define WDT_FUSES_ALWAYSON_SHIFT (26) /* WDT Always On */ -#define WDT_FUSES_ALWAYSON_MASK (1 << WDT_FUSES_ALWAYSON_SHIFT) - -#define WDT_FUSES_ENABLE_ADDR (SAM_AUX0_BASE + 0) -#define WDT_FUSES_ENABLE_SHIFT (25) /* WDT Enable */ -#define WDT_FUSES_ENABLE_MASK (1 << WDT_FUSES_ENABLE_SHIFT) - -#define WDT_FUSES_EWOFFSET_ADDR (SAM_AUX0_BASE + 4) -#define WDT_FUSES_EWOFFSET_SHIFT (3) /* WDT Early Warning Offset */ -#define WDT_FUSES_EWOFFSET_MASK (15 << WDT_FUSES_EWOFFSET_SHIFT) -# define WDT_FUSES_EWOFFSET(n) ((n) << WDT_FUSES_EWOFFSET_SHIFT) - -#define WDT_FUSES_PER_ADDR (SAM_AUX0_BASE + 0) -#define WDT_FUSES_PER_SHIFT (27) /* WDT Period */ -#define WDT_FUSES_PER_MASK (15 << WDT_FUSES_PER_SHIFT) -# define WDT_FUSES_PER(n) ((n) << WDT_FUSES_PER_SHIFT) - -#define WDT_FUSES_WEN_ADDR (SAM_AUX0_BASE + 4) -#define WDT_FUSES_WEN_SHIFT (7) /* WDT Window Mode Enable */ -#define WDT_FUSES_WEN_MASK (1 << WDT_FUSES_WEN_SHIFT) - -#define WDT_FUSES_WINDOW_0_ADDR (SAM_AUX0_BASE + 0) -#define WDT_FUSES_WINDOW_0_SHIFT (31) /* WDT Window bit 0 */ -#define WDT_FUSES_WINDOW_0_MASK (1 << WDT_FUSES_WINDOW_0_SHIFT) - -#define WDT_FUSES_WINDOW_1_ADDR (SAM_AUX0_BASE + 4) -#define WDT_FUSES_WINDOW_1_SHIFT (0) /* WDT Window bits 3:1 */ -#define WDT_FUSES_WINDOW_1_MASK (7 << WDT_FUSES_WINDOW_1_SHIFT) -# define WDT_FUSES_WINDOW_1(n) ((n) << WDT_FUSES_WINDOW_1_SHIFT) - /******************************************************************************************** * Public Types ********************************************************************************************/ diff --git a/arch/arm/src/samd/chip/sam_pm.h b/arch/arm/src/samd/chip/sam_pm.h index 607667e0f4..67f1d6b370 100644 --- a/arch/arm/src/samd/chip/sam_pm.h +++ b/arch/arm/src/samd/chip/sam_pm.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/chip/sam_port.h b/arch/arm/src/samd/chip/sam_port.h index 082e845e40..806948ea67 100644 --- a/arch/arm/src/samd/chip/sam_port.h +++ b/arch/arm/src/samd/chip/sam_port.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/chip/sam_sysctrl.h b/arch/arm/src/samd/chip/sam_sysctrl.h index 41c36059eb..2196636af1 100644 --- a/arch/arm/src/samd/chip/sam_sysctrl.h +++ b/arch/arm/src/samd/chip/sam_sysctrl.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/chip/samd20_memorymap.h b/arch/arm/src/samd/chip/samd20_memorymap.h index e915cfc9b9..ba276034c2 100644 --- a/arch/arm/src/samd/chip/samd20_memorymap.h +++ b/arch/arm/src/samd/chip/samd20_memorymap.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/chip/samd20_pinmap.h b/arch/arm/src/samd/chip/samd20_pinmap.h index 0ed9be3837..155358f3fd 100644 --- a/arch/arm/src/samd/chip/samd20_pinmap.h +++ b/arch/arm/src/samd/chip/samd20_pinmap.h @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/arch/arm/src/samd/sam_clockconfig.c b/arch/arm/src/samd/sam_clockconfig.c index 39a9c9b382..070209697f 100644 --- a/arch/arm/src/samd/sam_clockconfig.c +++ b/arch/arm/src/samd/sam_clockconfig.c @@ -4,6 +4,15 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * 1. "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * 2. Atmel sample code. This code has an ASF license with is compatible + * with the NuttX BSD license, but includes the provision that this + * code not be used in non-Atmel products. That sample code was used + * only as a reference so I believe that only the NuttX BSD license + * applies. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -48,6 +57,7 @@ #include "chip/sam_sysctrl.h" #include "chip/sam_gclk.h" #include "chip/sam_nvmctrl.h" +#include "chip/sam_fuses.h" #include diff --git a/arch/arm/src/samd/sam_port.c b/arch/arm/src/samd/sam_port.c index d936fd7f1f..6241ae0228 100644 --- a/arch/arm/src/samd/sam_port.c +++ b/arch/arm/src/samd/sam_port.c @@ -4,6 +4,10 @@ * Copyright (C) 2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * References: + * "Atmel SAM D20J / SAM D20G / SAM D20E ARM-Based Microcontroller + * Datasheet", 42129J–SAM–12/2013 + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/configs/samd20-xplained/include/board.h b/configs/samd20-xplained/include/board.h index 5fc844082e..e0058b067c 100644 --- a/configs/samd20-xplained/include/board.h +++ b/configs/samd20-xplained/include/board.h @@ -203,11 +203,11 @@ /* Resulting frequencies */ #define BOARD_MCK_FREQUENCY (BOARD_GLCK_MAIN_FREQUENCY) -#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY / 1) -#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY / 1) -#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY / 1) -#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY / 1) -#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY / 1) +#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY) +#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY) /* FLASH wait states */