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Review and update of SAM3/4 header files and conditional logic for SAM3X/A support

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This commit is contained in:
Gregory Nutt 2013-06-27 11:06:13 -06:00
parent bc7ac20616
commit 293e46e435
16 changed files with 464 additions and 140 deletions
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9
arch/arm/src/sam34/chip/sam3u_eefc.h
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@ -1,6 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_eefc.h
* Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U and SAM4S
* Enhanced Embedded Flash Controller (EEFC) defintions for the SAM3U, SAM3X, SAM3A and
* SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -80,6 +81,7 @@
#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
#define EEFC_FMR_FWS_SHIFT (8) /* Bits 8-11: Flash Wait State */
#define EEFC_FMR_FWS_MASK (15 << EEFC_FMR_FWS_SHIFT)
# define EEFC_FMR_FWS(n) ((n) << EEFC_FMR_FWS_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define EEFC_FMR_SCOD (1 << 16) /* Bit 16: Sequential Code Optimization Disable */
@ -116,8 +118,11 @@
# define EEFC_FCR_FCMD_STUI (14 << EEFC_FCR_FCMD_SHIFT) /* Start Read Unique Identifier */
# define EEFC_FCR_FCMD_SPUI (15 << EEFC_FCR_FCMD_SHIFT) /* Stop Read Unique Identifier */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define EEFC_FCR_FCMD_GCALB (16 << EEFC_FCR_FCMD_SHIFT) /* Get CALIB Bit */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define EEFC_FCR_FCMD_ES (17 << EEFC_FCR_FCMD_SHIFT) /* Erase Sector */
# define EEFC_FCR_FCMD_WUS (18 << EEFC_FCR_FCMD_SHIFT) /* Write User Signature */
# define EEFC_FCR_FCMD_EUS (19 << EEFC_FCR_FCMD_SHIFT) /* Erase User Signature */

109
arch/arm/src/sam34/chip/sam3u_matrix.h
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@ -1,6 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_34matrix.h
* Bux matrix definitions for the SAM3U and SAM4S
* Bux matrix definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -58,54 +58,56 @@
#define SAM_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
#define SAM_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
#define SAM_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
/* 0x0014-0x003c: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_MCFG5_OFFSET 0x0014 /* Master Configuration Register 5 */
#endif
/* 0x0018-0x003c: Reserved */
#define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
#define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
#define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
#define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
#define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
#define SAM_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
# define SAM_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
# define SAM_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
# define SAM_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
/* 0x0068-0x007c: Reserved (SAM3U) */
#endif
/* 0x0054-0x007c: Reserved (SAM4S) */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
#endif
#define SAM_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
#define SAM_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
/* 0x0084: Reserved */
#define SAM_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
/* 0x008c: Reserved */
#define SAM_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
/* 0x0094: Reserved */
#define SAM_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
/* 0x009c: Reserved */
#define SAM_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
/* 0x00a4: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
/* 0x00ac: Reserved */
# define SAM_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
/* 0x00b4: Reserved */
# define SAM_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
/* 0x00bc: Reserved */
# define SAM_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
/* 0x00c4: Reserved */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
/* 0x00cc-0x00fc: Reserved */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
/* 0x0104-0x01e0: Reserved */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
/* 0x00a4-0x110: Reserved */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MATRIX_CCFG_SYSIO_OFFSET 0x0114 /* System I/O Configuration Register */
/* 0x0118: Reserved */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MATRIX_CCFG_SMCNFCS_OFFSET 0x011c /* SMC Chip Select NAND Flash Assignment Register */
/* 0x0120-0x01e0: Reserved */
#endif
#define SAM_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
@ -120,18 +122,24 @@
#define SAM_MATRIX_MCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG2_OFFSET)
#define SAM_MATRIX_MCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG3_OFFSET)
#define SAM_MATRIX_MCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG4_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_MCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG5_OFFSET)
#endif
#define SAM_MATRIX_SCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_SCFG_OFFSET(n))
#define SAM_MATRIX_SCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG0_OFFSET)
#define SAM_MATRIX_SCFG1 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG1_OFFSET)
#define SAM_MATRIX_SCFG2 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG2_OFFSET)
#define SAM_MATRIX_SCFG3 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG3_OFFSET)
#define SAM_MATRIX_SCFG4 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG4_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_SCFG5 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG5_OFFSET)
# define SAM_MATRIX_SCFG6 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG6_OFFSET)
# define SAM_MATRIX_SCFG7 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG7_OFFSET)
# define SAM_MATRIX_SCFG8 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG8_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_MATRIX_SCFG9 (SAM_MATRIX_BASE+SAM_MATRIX_SCFG9_OFFSET)
#endif
@ -141,18 +149,28 @@
#define SAM_MATRIX_PRAS2 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS2_OFFSET)
#define SAM_MATRIX_PRAS3 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS3_OFFSET)
#define SAM_MATRIX_PRAS4 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS4_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_PRAS5 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS5_OFFSET)
# define SAM_MATRIX_PRAS6 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS6_OFFSET)
# define SAM_MATRIX_PRAS7 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS7_OFFSET)
# define SAM_MATRIX_PRAS8 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS8_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SAM_MATRIX_PRAS9 (SAM_MATRIX_BASE+SAM_MATRIX_PRAS9_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_MATRIX_MRCR (SAM_MATRIX_BASE+SAM_MATRIX_MRCR_OFFSET)
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MATRIX_CCFG_SYSIO (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SYSIO_OFFSET)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MATRIX_CCFG_SMCNFCS (SAM_MATRIX_BASE+SAM_MATRIX_CCFG_SMCNFCS_OFFSET)
#endif
@ -202,16 +220,20 @@
#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
#define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
#define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
#define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
#define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
#define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
#define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
#define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
#define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
#define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17 Master 4 Priority */
#define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
# define MATRIX_PRAS_M0PR_SHIFT (0) /* Bits 0-1: Master 0 Priority */
# define MATRIX_PRAS_M0PR_MASK (3 << MATRIX_PRAS_M0PR_SHIFT)
# define MATRIX_PRAS_M1PR_SHIFT (4) /* Bits 4-5: Master 1 Priority */
# define MATRIX_PRAS_M1PR_MASK (3 << MATRIX_PRAS_M1PR_SHIFT)
# define MATRIX_PRAS_M2PR_SHIFT (8) /* Bits 8-9: Master 2 Priority */
# define MATRIX_PRAS_M2PR_MASK (3 << MATRIX_PRAS_M2PR_SHIFT)
# define MATRIX_PRAS_M3PR_SHIFT (12) /* Bits 12-13: Master 3 Priority */
# define MATRIX_PRAS_M3PR_MASK (3 << MATRIX_PRAS_M3PR_SHIFT)
# define MATRIX_PRAS_M4PR_SHIFT (16) /* Bits 16-17: Master 4 Priority */
# define MATRIX_PRAS_M4PR_MASK (3 << MATRIX_PRAS_M4PR_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define MATRIX_PRAS_M5PR_SHIFT (20) /* Bits 20-21: Master 5 Priority */
# define MATRIX_PRAS_M5PR_MASK (3 << MATRIX_PRAS_M5PR_SHIFT)
#endif
/* System I/O Configuration Register */
@ -225,6 +247,10 @@
# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PB12 or ERASE Assignment */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define MATRIX_CCFG_SYSIO_SYSIO12 (1 << 12) /* Bit 12: PC0 or ERASE Assignment */
#endif
/* SMC Chip Select NAND Flash Assignment Register */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
@ -236,13 +262,16 @@
/* Master Remap Control Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define MATRIX_MRCR_RCB(x) (1 << (x))
# define MATRIX_MRCR_RCB0 (1 << 0) /* Bit 0: Remap Command Bit for AHB Master 0 */
# define MATRIX_MRCR_RCB1 (1 << 1) /* Bit 1: Remap Command Bit for AHB Master 1 */
# define MATRIX_MRCR_RCB2 (1 << 2) /* Bit 2: Remap Command Bit for AHB Master 2 */
# define MATRIX_MRCR_RCB3 (1 << 3) /* Bit 3: Remap Command Bit for AHB Master 3 */
# define MATRIX_MRCR_RCB4 (1 << 4) /* Bit 4: Remap Command Bit for AHB Master 4 */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define MATRIX_MRCR_RCB5 (1 << 5) /* Bit 5: Remap Command Bit for AHB Master 5 */
#endif
#endif
/* Write Protect Mode Register */

145
arch/arm/src/sam34/chip/sam3u_pio.h
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@ -1,6 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_pio.h
* Parallel Input/Output (PIO) Controller definitions for the SAM3U
* Parallel Input/Output (PIO) Controller definitions for the SAM3U, SAM3X, and SAM3A.
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -114,7 +114,14 @@
#define PIOA (0)
#define PIOB (1)
#define PIOC (2)
#define NPIO (3)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define PIOD (3)
# define PIOE (4)
# define PIOF (5)
# define NPIO (6)
#else
# define NPIO (3)
#endif
#define SAM_PIO_PER(n) (SAM_PIO_BASE(n)+SAM_PIO_PER_OFFSET)
#define SAM_PIO_PDR(n) (SAM_PIO_BASE(n)+SAM_PIO_PDR_OFFSET)
@ -292,6 +299,140 @@
#define SAM_PIOC_WPMR (SAM_PIOC_BASE+SAM_PIO_WPMR_OFFSET)
#define SAM_PIOC_WPSR (SAM_PIOC_BASE+SAM_PIO_WPSR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PIOD_PER (SAM_PIOD_BASE+SAM_PIO_PER_OFFSET)
# define SAM_PIOD_PDR (SAM_PIOD_BASE+SAM_PIO_PDR_OFFSET)
# define SAM_PIOD_PSR (SAM_PIOD_BASE+SAM_PIO_PSR_OFFSET)
# define SAM_PIOD_OER (SAM_PIOD_BASE+SAM_PIO_OER_OFFSET)
# define SAM_PIOD_ODR (SAM_PIOD_BASE+SAM_PIO_ODR_OFFSET)
# define SAM_PIOD_OSR (SAM_PIOD_BASE+SAM_PIO_OSR_OFFSET)
# define SAM_PIOD_IFER (SAM_PIOD_BASE+SAM_PIO_IFER_OFFSET)
# define SAM_PIOD_IFDR (SAM_PIOD_BASE+SAM_PIO_IFDR_OFFSET)
# define SAM_PIOD_IFSR (SAM_PIOD_BASE+SAM_PIO_IFSR_OFFSET)
# define SAM_PIOD_SODR (SAM_PIOD_BASE+SAM_PIO_SODR_OFFSET)
# define SAM_PIOD_CODR (SAM_PIOD_BASE+SAM_PIO_CODR_OFFSET)
# define SAM_PIOD_ODSR (SAM_PIOD_BASE+SAM_PIO_ODSR_OFFSET)
# define SAM_PIOD_PDSR (SAM_PIOD_BASE+SAM_PIO_PDSR_OFFSET)
# define SAM_PIOD_IER (SAM_PIOD_BASE+SAM_PIO_IER_OFFSET)
# define SAM_PIOD_IDR (SAM_PIOD_BASE+SAM_PIO_IDR_OFFSET)
# define SAM_PIOD_IMR (SAM_PIOD_BASE+SAM_PIO_IMR_OFFSET)
# define SAM_PIOD_ISR (SAM_PIOD_BASE+SAM_PIO_ISR_OFFSET)
# define SAM_PIOD_MDER (SAM_PIOD_BASE+SAM_PIO_MDER_OFFSET)
# define SAM_PIOD_MDDR (SAM_PIOD_BASE+SAM_PIO_MDDR_OFFSET)
# define SAM_PIOD_MDSR (SAM_PIOD_BASE+SAM_PIO_MDSR_OFFSET)
# define SAM_PIOD_PUDR (SAM_PIOD_BASE+SAM_PIO_PUDR_OFFSET)
# define SAM_PIOD_PUER (SAM_PIOD_BASE+SAM_PIO_PUER_OFFSET)
# define SAM_PIOD_PUSR (SAM_PIOD_BASE+SAM_PIO_PUSR_OFFSET)
# define SAM_PIOD_ABSR (SAM_PIOD_BASE+SAM_PIO_ABSR_OFFSET)
# define SAM_PIOD_SCIFSR (SAM_PIOD_BASE+SAM_PIO_SCIFSR_OFFSET)
# define SAM_PIOD_DIFSR (SAM_PIOD_BASE+SAM_PIO_DIFSR_OFFSET)
# define SAM_PIOD_IFDGSR (SAM_PIOD_BASE+SAM_PIO_IFDGSR_OFFSET)
# define SAM_PIOD_SCDR (SAM_PIOD_BASE+SAM_PIO_SCDR_OFFSET)
# define SAM_PIOD_OWER (SAM_PIOD_BASE+SAM_PIO_OWER_OFFSET)
# define SAM_PIOD_OWDR (SAM_PIOD_BASE+SAM_PIO_OWDR_OFFSET)
# define SAM_PIOD_OWSR (SAM_PIOD_BASE+SAM_PIO_OWSR_OFFSET)
# define SAM_PIOD_AIMER (SAM_PIOD_BASE+SAM_PIO_AIMER_OFFSET)
# define SAM_PIOD_AIMDR (SAM_PIOD_BASE+SAM_PIO_AIMDR_OFFSET)
# define SAM_PIOD_AIMMR (SAM_PIOD_BASE+SAM_PIO_AIMMR_OFFSET)
# define SAM_PIOD_ESR (SAM_PIOD_BASE+SAM_PIO_ESR_OFFSET)
# define SAM_PIOD_LSR (SAM_PIOD_BASE+SAM_PIO_LSR_OFFSET)
# define SAM_PIOD_ELSR (SAM_PIOD_BASE+SAM_PIO_ELSR_OFFSET)
# define SAM_PIOD_FELLSR (SAM_PIOD_BASE+SAM_PIO_FELLSR_OFFSET)
# define SAM_PIOD_REHLSR (SAM_PIOD_BASE+SAM_PIO_REHLSR_OFFSET)
# define SAM_PIOD_FRLHSR (SAM_PIOD_BASE+SAM_PIO_FRLHSR_OFFSET)
# define SAM_PIOD_LOCKSR (SAM_PIOD_BASE+SAM_PIO_LOCKSR_OFFSET)
# define SAM_PIOD_WPMR (SAM_PIOD_BASE+SAM_PIO_WPMR_OFFSET)
# define SAM_PIOD_WPSR (SAM_PIOD_BASE+SAM_PIO_WPSR_OFFSET)
# define SAM_PIOE_PER (SAM_PIOE_BASE+SAM_PIO_PER_OFFSET)
# define SAM_PIOE_PDR (SAM_PIOE_BASE+SAM_PIO_PDR_OFFSET)
# define SAM_PIOE_PSR (SAM_PIOE_BASE+SAM_PIO_PSR_OFFSET)
# define SAM_PIOE_OER (SAM_PIOE_BASE+SAM_PIO_OER_OFFSET)
# define SAM_PIOE_ODR (SAM_PIOE_BASE+SAM_PIO_ODR_OFFSET)
# define SAM_PIOE_OSR (SAM_PIOE_BASE+SAM_PIO_OSR_OFFSET)
# define SAM_PIOE_IFER (SAM_PIOE_BASE+SAM_PIO_IFER_OFFSET)
# define SAM_PIOE_IFDR (SAM_PIOE_BASE+SAM_PIO_IFDR_OFFSET)
# define SAM_PIOE_IFSR (SAM_PIOE_BASE+SAM_PIO_IFSR_OFFSET)
# define SAM_PIOE_SODR (SAM_PIOE_BASE+SAM_PIO_SODR_OFFSET)
# define SAM_PIOE_CODR (SAM_PIOE_BASE+SAM_PIO_CODR_OFFSET)
# define SAM_PIOE_ODSR (SAM_PIOE_BASE+SAM_PIO_ODSR_OFFSET)
# define SAM_PIOE_PDSR (SAM_PIOE_BASE+SAM_PIO_PDSR_OFFSET)
# define SAM_PIOE_IER (SAM_PIOE_BASE+SAM_PIO_IER_OFFSET)
# define SAM_PIOE_IDR (SAM_PIOE_BASE+SAM_PIO_IDR_OFFSET)
# define SAM_PIOE_IMR (SAM_PIOE_BASE+SAM_PIO_IMR_OFFSET)
# define SAM_PIOE_ISR (SAM_PIOE_BASE+SAM_PIO_ISR_OFFSET)
# define SAM_PIOE_MDER (SAM_PIOE_BASE+SAM_PIO_MDER_OFFSET)
# define SAM_PIOE_MDDR (SAM_PIOE_BASE+SAM_PIO_MDDR_OFFSET)
# define SAM_PIOE_MDSR (SAM_PIOE_BASE+SAM_PIO_MDSR_OFFSET)
# define SAM_PIOE_PUDR (SAM_PIOE_BASE+SAM_PIO_PUDR_OFFSET)
# define SAM_PIOE_PUER (SAM_PIOE_BASE+SAM_PIO_PUER_OFFSET)
# define SAM_PIOE_PUSR (SAM_PIOE_BASE+SAM_PIO_PUSR_OFFSET)
# define SAM_PIOE_ABSR (SAM_PIOE_BASE+SAM_PIO_ABSR_OFFSET)
# define SAM_PIOE_SCIFSR (SAM_PIOE_BASE+SAM_PIO_SCIFSR_OFFSET)
# define SAM_PIOE_DIFSR (SAM_PIOE_BASE+SAM_PIO_DIFSR_OFFSET)
# define SAM_PIOE_IFDGSR (SAM_PIOE_BASE+SAM_PIO_IFDGSR_OFFSET)
# define SAM_PIOE_SCDR (SAM_PIOE_BASE+SAM_PIO_SCDR_OFFSET)
# define SAM_PIOE_OWER (SAM_PIOE_BASE+SAM_PIO_OWER_OFFSET)
# define SAM_PIOE_OWDR (SAM_PIOE_BASE+SAM_PIO_OWDR_OFFSET)
# define SAM_PIOE_OWSR (SAM_PIOE_BASE+SAM_PIO_OWSR_OFFSET)
# define SAM_PIOE_AIMER (SAM_PIOE_BASE+SAM_PIO_AIMER_OFFSET)
# define SAM_PIOE_AIMDR (SAM_PIOE_BASE+SAM_PIO_AIMDR_OFFSET)
# define SAM_PIOE_AIMMR (SAM_PIOE_BASE+SAM_PIO_AIMMR_OFFSET)
# define SAM_PIOE_ESR (SAM_PIOE_BASE+SAM_PIO_ESR_OFFSET)
# define SAM_PIOE_LSR (SAM_PIOE_BASE+SAM_PIO_LSR_OFFSET)
# define SAM_PIOE_ELSR (SAM_PIOE_BASE+SAM_PIO_ELSR_OFFSET)
# define SAM_PIOE_FELLSR (SAM_PIOE_BASE+SAM_PIO_FELLSR_OFFSET)
# define SAM_PIOE_REHLSR (SAM_PIOE_BASE+SAM_PIO_REHLSR_OFFSET)
# define SAM_PIOE_FRLHSR (SAM_PIOE_BASE+SAM_PIO_FRLHSR_OFFSET)
# define SAM_PIOE_LOCKSR (SAM_PIOE_BASE+SAM_PIO_LOCKSR_OFFSET)
# define SAM_PIOE_WPMR (SAM_PIOE_BASE+SAM_PIO_WPMR_OFFSET)
# define SAM_PIOE_WPSR (SAM_PIOE_BASE+SAM_PIO_WPSR_OFFSET)
# define SAM_PIOF_PER (SAM_PIOF_BASE+SAM_PIO_PER_OFFSET)
# define SAM_PIOF_PDR (SAM_PIOF_BASE+SAM_PIO_PDR_OFFSET)
# define SAM_PIOF_PSR (SAM_PIOF_BASE+SAM_PIO_PSR_OFFSET)
# define SAM_PIOF_OER (SAM_PIOF_BASE+SAM_PIO_OER_OFFSET)
# define SAM_PIOF_ODR (SAM_PIOF_BASE+SAM_PIO_ODR_OFFSET)
# define SAM_PIOF_OSR (SAM_PIOF_BASE+SAM_PIO_OSR_OFFSET)
# define SAM_PIOF_IFER (SAM_PIOF_BASE+SAM_PIO_IFER_OFFSET)
# define SAM_PIOF_IFDR (SAM_PIOF_BASE+SAM_PIO_IFDR_OFFSET)
# define SAM_PIOF_IFSR (SAM_PIOF_BASE+SAM_PIO_IFSR_OFFSET)
# define SAM_PIOF_SODR (SAM_PIOF_BASE+SAM_PIO_SODR_OFFSET)
# define SAM_PIOF_CODR (SAM_PIOF_BASE+SAM_PIO_CODR_OFFSET)
# define SAM_PIOF_ODSR (SAM_PIOF_BASE+SAM_PIO_ODSR_OFFSET)
# define SAM_PIOF_PDSR (SAM_PIOF_BASE+SAM_PIO_PDSR_OFFSET)
# define SAM_PIOF_IER (SAM_PIOF_BASE+SAM_PIO_IER_OFFSET)
# define SAM_PIOF_IDR (SAM_PIOF_BASE+SAM_PIO_IDR_OFFSET)
# define SAM_PIOF_IMR (SAM_PIOF_BASE+SAM_PIO_IMR_OFFSET)
# define SAM_PIOF_ISR (SAM_PIOF_BASE+SAM_PIO_ISR_OFFSET)
# define SAM_PIOF_MDER (SAM_PIOF_BASE+SAM_PIO_MDER_OFFSET)
# define SAM_PIOF_MDDR (SAM_PIOF_BASE+SAM_PIO_MDDR_OFFSET)
# define SAM_PIOF_MDSR (SAM_PIOF_BASE+SAM_PIO_MDSR_OFFSET)
# define SAM_PIOF_PUDR (SAM_PIOF_BASE+SAM_PIO_PUDR_OFFSET)
# define SAM_PIOF_PUER (SAM_PIOF_BASE+SAM_PIO_PUER_OFFSET)
# define SAM_PIOF_PUSR (SAM_PIOF_BASE+SAM_PIO_PUSR_OFFSET)
# define SAM_PIOF_ABSR (SAM_PIOF_BASE+SAM_PIO_ABSR_OFFSET)
# define SAM_PIOF_SCIFSR (SAM_PIOF_BASE+SAM_PIO_SCIFSR_OFFSET)
# define SAM_PIOF_DIFSR (SAM_PIOF_BASE+SAM_PIO_DIFSR_OFFSET)
# define SAM_PIOF_IFDGSR (SAM_PIOF_BASE+SAM_PIO_IFDGSR_OFFSET)
# define SAM_PIOF_SCDR (SAM_PIOF_BASE+SAM_PIO_SCDR_OFFSET)
# define SAM_PIOF_OWER (SAM_PIOF_BASE+SAM_PIO_OWER_OFFSET)
# define SAM_PIOF_OWDR (SAM_PIOF_BASE+SAM_PIO_OWDR_OFFSET)
# define SAM_PIOF_OWSR (SAM_PIOF_BASE+SAM_PIO_OWSR_OFFSET)
# define SAM_PIOF_AIMER (SAM_PIOF_BASE+SAM_PIO_AIMER_OFFSET)
# define SAM_PIOF_AIMDR (SAM_PIOF_BASE+SAM_PIO_AIMDR_OFFSET)
# define SAM_PIOF_AIMMR (SAM_PIOF_BASE+SAM_PIO_AIMMR_OFFSET)
# define SAM_PIOF_ESR (SAM_PIOF_BASE+SAM_PIO_ESR_OFFSET)
# define SAM_PIOF_LSR (SAM_PIOF_BASE+SAM_PIO_LSR_OFFSET)
# define SAM_PIOF_ELSR (SAM_PIOF_BASE+SAM_PIO_ELSR_OFFSET)
# define SAM_PIOF_FELLSR (SAM_PIOF_BASE+SAM_PIO_FELLSR_OFFSET)
# define SAM_PIOF_REHLSR (SAM_PIOF_BASE+SAM_PIO_REHLSR_OFFSET)
# define SAM_PIOF_FRLHSR (SAM_PIOF_BASE+SAM_PIO_FRLHSR_OFFSET)
# define SAM_PIOF_LOCKSR (SAM_PIOF_BASE+SAM_PIO_LOCKSR_OFFSET)
# define SAM_PIOF_WPMR (SAM_PIOF_BASE+SAM_PIO_WPMR_OFFSET)
# define SAM_PIOF_WPSR (SAM_PIOF_BASE+SAM_PIO_WPSR_OFFSET)
#endif
/* PIO register bit definitions *********************************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */

2
arch/arm/src/sam34/chip/sam3u_pmc.h
View File

@ -1,6 +1,6 @@
/********************************************************************************************
* arch/arm/src/sam34/chip/sam3u_pmc.h
* Power Management Controller (PMC) for the SAM3U and SAM4S
* Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>

158
arch/arm/src/sam34/chip/sam_smc.h → arch/arm/src/sam34/chip/sam3u_smc.h
View File

@ -1,5 +1,5 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_smc.h
* arch/arm/src/sam34/chip/sam3u_smc.h
* Static Memory Controller (SMC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
@ -34,8 +34,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H
/****************************************************************************************
* Included Files
@ -52,7 +52,8 @@
/* SMC register offsets *****************************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMC_CFG_OFFSET 0x0000 /* SMC NFC Configuration Register */
# define SAM_SMC_CTRL_OFFSET 0x0004 /* SMC NFC Control Register */
# define SAM_SMC_SR_OFFSET 0x0008 /* SMC NFC Status Register */
@ -124,7 +125,8 @@
/* SMC register adresses ****************************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMC_CFG (SAM_SMC_BASE+SAM_SMC_CFG_OFFSET)
# define SAM_SMC_CTRL (SAM_SMC_BASE+SAM_SMC_CTRL_OFFSET)
# define SAM_SMC_SR (SAM_SMC_BASE+SAM_SMC_SR_OFFSET)
@ -164,41 +166,56 @@
#define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET)
#define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET)
#define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMCCS_TIMINGS(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_TIMINGS_OFFSET)
#endif
#define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET)
# define SAM_SMCCS0_SETUP (SAM_SMC_CS0_BASE+SAM_SMCCS_SETUP_OFFSET)
# define SAM_SMCCS0_PULSE (SAM_SMC_CS0_BASE+SAM_SMCCS_PULSE_OFFSET)
# define SAM_SMCCS0_CYCLE (SAM_SMC_CS0_BASE+SAM_SMCCS_CYCLE_OFFSET)
# if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMCCS0_TIMINGS (SAM_SMC_CS0_BASE+SAM_SMCCS_TIMINGS_OFFSET)
# endif
# define SAM_SMCCS0_MODE (SAM_SMC_CS0_BASE+SAM_SMCCS_MODE_OFFSET)
# define SAM_SMCCS1_SETUP (SAM_SMC_CS1_BASE+SAM_SMCCS_SETUP_OFFSET)
# define SAM_SMCCS1_PULSE (SAM_SMC_CS1_BASE+SAM_SMCCS_PULSE_OFFSET)
# define SAM_SMCCS1_CYCLE (SAM_SMC_CS1_BASE+SAM_SMCCS_CYCLE_OFFSET)
# if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMCCS1_TIMINGS (SAM_SMC_CS1_BASE+SAM_SMCCS_TIMINGS_OFFSET)
# endif
# define SAM_SMCCS1_MODE (SAM_SMC_CS1_BASE+SAM_SMCCS_MODE_OFFSET)
# define SAM_SMCCS2_SETUP (SAM_SMC_CS2_BASE+SAM_SMCCS_SETUP_OFFSET)
# define SAM_SMCCS2_PULSE (SAM_SMC_CS2_BASE+SAM_SMCCS_PULSE_OFFSET)
# define SAM_SMCCS2_CYCLE (SAM_SMC_CS2_BASE+SAM_SMCCS_CYCLE_OFFSET)
# if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMCCS2_TIMINGS (SAM_SMC_CS2_BASE+SAM_SMCCS_TIMINGS_OFFSET)
# endif
# define SAM_SMCCS2_MODE (SAM_SMC_CS2_BASE+SAM_SMCCS_MODE_OFFSET)
# define SAM_SMCCS3_SETUP (SAM_SMC_CS3_BASE+SAM_SMCCS_SETUP_OFFSET)
# define SAM_SMCCS3_PULSE (SAM_SMC_CS3_BASE+SAM_SMCCS_PULSE_OFFSET)
# define SAM_SMCCS3_CYCLE (SAM_SMC_CS3_BASE+SAM_SMCCS_CYCLE_OFFSET)
# if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SMCCS3_TIMINGS (SAM_SMC_CS3_BASE+SAM_SMCCS_TIMINGS_OFFSET)
# endif
# define SAM_SMCCS3_MODE (SAM_SMC_CS3_BASE+SAM_SMCCS_MODE_OFFSET)
#define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET)
@ -211,13 +228,14 @@
/* SMC NFC Configuration Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_CFG_PAGESIZE_SHIFT (0) /* Bits 0-1: Page size of NAND Flash device */
# define SMC_CFG_PAGESIZE_MASK (3 << SMC_CFG_PAGESIZE_SHIFT)
# define SMC_CFG_PAGESIZE_16 BYTES (0 << SMC_CFG_PAGESIZE_SHIFT) /* 528 Bytes 16 byte */
# define SMC_CFG_PAGESIZE_ 2 BYTES (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1056 Bytes 32 bytes */
# define SMC_CFG_PAGESIZE_64 BYTES (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2112 Bytes 64 bytes */
# define SMC_CFG_PAGESIZE_128 BYTES (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4224 Bytes 128 bytes */
# define SMC_CFG_PAGESIZE_528 (0 << SMC_CFG_PAGESIZE_SHIFT) /* 512 bytes + 16 byte spare */
# define SMC_CFG_PAGESIZE_1056 (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */
# define SMC_CFG_PAGESIZE_2122 (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */
# define SMC_CFG_PAGESIZE_4224 (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */
# define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */
# define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */
# define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */
@ -238,7 +256,8 @@
/* SMC NFC Control Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_CTRL_NFCEN (1 << 0) /* Bit 0: NAND Flash Controller Enable */
# define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
#endif
@ -247,19 +266,22 @@
* Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_SR_SMCSTS (1 << 0) /* Bit 0: NAND Flash Controller status (SR only) */
# define SMC_INT_RBRISE (1 << 4) /* Bit 4: Ready Busy Rising Edge Detection Interrupt */
# define SMC_INT_RBFALL (1 << 5) /* Bit 5: Ready Busy Falling Edge Detection Interrupt */
# define SMC_SR_NFCBUSY (1 << 8) /* Bit 8: NFC Busy (SR only) */
# define SMC_SR_NFCWR (1 << 11) /* Bit 11: NFC Write/Read Operation (SR only) */
# define SMC_SR_NFCSID (1 << 12) /* Bit 13: NFC Chip Select ID (SR only) */
# define SMC_SR_NFCSID_SHIFT (12) /* Bits 12-14: NFC Chip Select ID (SR only) */
# define SMC_SR_NFCSID_MASK (7 << SMC_SR_NFCSID_SHIFT)
# define SMC_INT_XFRDONE (1 << 16) /* Bit 16: Transfer Done Interrupt */
# define SMC_INT_CMDDONE (1 << 17) /* Bit 17: Command Done Interrupt */
# define SMC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error Interrupt */
# define SMC_INT_UNDEF (1 << 21) /* Bit 21: Undefined Area Access Interrupt */
# define SMC_INT_AWB (1 << 22) /* Bit 22: Accessing While Busy Interrupt */
# define SMC_INT_NFCASE (1 << 23) /* Bit 23: NFC Access Size Error Interrupt */
#ifdef CONFIG_ARCH_CHIP_SAM3U
# define SMC_INT_RBEDGE(n) (1<<((n)+24))
# define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
# define SMC_INT_RB_EDGE1 (1 << 25) /* Bit 25: Ready/Busy Line 1 Interrupt */
@ -269,48 +291,56 @@
# define SMC_INT_RB_EDGE5 (1 << 29) /* Bit 29: Ready/Busy Line 5 Interrupt */
# define SMC_INT_RB_EDGE6 (1 << 30) /* Bit 30: Ready/Busy Line 6 Interrupt */
# define SMC_INT_RB_EDGE7 (1 << 31) /* Bit 31: Ready/Busy Line 7 Interrupt */
#else
# define SMC_INT_RB_EDGE0 (1 << 24) /* Bit 24: Ready/Busy Line 0 Interrupt */
#endif
#endif
/* SMC NFC Address Cycle Zero Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ADDR_CYCLE0_SHIFT (3) /* Bits 0-7: NAND Flash Array Address cycle 0 */
# define SMC_ADDR_CYCLE0_MASK (0xff << SMC_ADDR_CYCLE0_SHIFT)
#endif
/* SMC NFC Bank Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_BANK_SHIFT (0) /* Bits 0-2: Bank identifier */
# define SMC_BANK_MASK (7 << SMC_BANK_SHIFT)
#endif
/* SMC ECC Control Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCCTRL_RST (1 << 0) /* Bit 0: Reset ECC */
# define SMC_ECCCTRL_SWRST (1 << 1) /* Bit 1: Software Reset */
#endif
/* SMC ECC MODE Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */
# define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */
# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCMD_ECC_PAGESIZE_SHIFT (0) /* Bits 0-1 */
# define SMC_ECCMD_ECC_PAGESIZE_MASK (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT)
# define SMC_ECCMD_ECC_PAGESIZE_528 (0 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 512 bytes + 16 byte spare */
# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */
# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */
# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */
# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
# define SMC_ECCMD_TYPCORREC_256 (1 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 256 bytes */
# define SMC_ECCMD_TYPCORREC_512 (2 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for 512 bytes */
#endif
/* SMC ECC Status Register 1 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define _RECERR (0) /* Recoverable Error */
# define _ECCERR (1) /* ECC Error */
# define _MULERR (2) /* Multiple Error */
@ -347,7 +377,8 @@
/* SMC ECC Status Register 2 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCSR2_RECERR(n) (1 << ((((n)-8)<<4)+_RECERR))
# define SMC_ECCSR2_ECCERR(n) (1 << ((((n)-8)<<4)+_ECCERR))
# define SMC_ECCSR2_MULERR(n) (1 << ((((n)-8)<<4)+_MULERR))
@ -381,19 +412,23 @@
/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */
/* SMC_ECC_PR0 */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCPR0_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
# define SMC_ECCPR0_BITADDR_MASK (15 << SMC_ECCPR0_BITADDR_SHIFT)
# define SMC_ECCPR0_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
# define SMC_ECCPR0_WORDADDR_MASK (0xfff << SMC_ECCPR0_WORDADDR_SHIFT)
#ifdef CONFIG_ARCH_CHIP_SAM3U
# define SMC_ECCPR1_NPARITY_SHIFT (0) /* Bits 0-15 */
# define SMC_ECCPR1_NPARITY_MASK (0xffff << SMC_ECCPR1_NPARITY_SHIFT)
#endif
#endif
/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCPR512_BITADDR_SHIFT (0) /* Bits 0-3: Bit Address */
# define SMC_ECCPR512_BITADDR_MASK (15 << SMC_ECCPR512_BITADDR_SHIFT)
# define SMC_ECCPR512_WORDADDR_SHIFT (4) /* Bits 4-15: Word Address */
@ -404,7 +439,8 @@
/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_ECCPR256_BITADDR_SHIFT (0) /* Bits 0-2: Bit Address */
# define SMC_ECCPR256_BITADDR_MASK (7 << SMC_ECCPR256_BITADDR_SHIFT)
# define SMC_ECCPR256_WORDADDR_SHIFT (4) /* Bits 4-10: Word Address */
@ -454,7 +490,8 @@
/* SMC Timings Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMCCS_TIMINGS_TCLR_SHIFT (0) /* Bits 0-3: CLE to REN Low Delay */
# define SMCCS_TIMINGS_TCLR_MASK (15 << SMCCS_TIMINGS_TCLR_SHIFT)
# define SMCCS_TIMINGS_TADL_SHIFT (4) /* Bits 4-7: ALE to Data Start */
@ -481,7 +518,8 @@
# define SMCCS_EXNWMODE_FROZEN (2 << SMCCS_MODE_EXNWMODE_SHIFT)
# define SMCCS_EXNWMODE_READY (3 << SMCCS_MODE_EXNWMODE_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMCCS_MODE_BAT (1 << 8) /* Bit 8: Byte Access Type */
# define SMCCS_MODE_DBW_SHIFT (12) /* Bits 12-13: Data Bus Width */
# define SMCCS_MODE_DBW_MASK (3 << SMCCS_MODE_DBW_SHIFT)
@ -493,13 +531,16 @@
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
#define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
#define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
# define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
# define SMCCS_MODE_PS_SIZE_16BYTES (2 << SMCCS_MODE_PS_SHIFT) /* 16 bytes */
# define SMCCS_MODE_PS_SIZE_32BYTES (3 << SMCCS_MODE_PS_SHIFT) /* 32 bytes */
#endif
/* SMC OCMS Mode Register */
@ -525,19 +566,20 @@
/* SMC Write Protection Status */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
# define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
# define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT)
# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */
# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SMC_WPSR_PVS_SHIFT (0) /* Bits 0-3: Write Protection Violation Status */
# define SMC_WPSR_PVS_MASK (15 << SMC_WPSR_PVS_SHIFT)
# define SMC_WPSR_PVS_NONE (0 << SMC_WPSR_PVS_SHIFT) /* No Write Protection Violation */
# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
#endif
#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types
@ -551,4 +593,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H */
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H */

18
arch/arm/src/sam34/chip/sam3u_supc.h
View File

@ -1,6 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_supc.h
* Supply Controller (SUPC) definitions for the SAM3U and SAM4S
* Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -82,7 +82,7 @@
#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */
#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
# if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */
# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */
# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */
@ -99,7 +99,7 @@
# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */
# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */
# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */
# elif defined(CONFIG_ARCH_CHIP_SAM3U)
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */
# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */
# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */
@ -133,9 +133,11 @@
#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */
#elif defined(CONFIG_ARCH_CHIP_SAM3U)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */
#endif
@ -157,7 +159,7 @@
# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */
# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */
# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */
#elif defined(CONFIG_ARCH_CHIP_SAM3U)
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
@ -201,7 +203,7 @@
/* Supply Controller Status Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */
#endif
@ -213,7 +215,7 @@
#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */

103
arch/arm/src/sam34/chip/sam3u_uart.h
View File

@ -1,7 +1,7 @@
/************************************************************************************************
* arch/arm/src/sam34/chip/sam3u_uart.h
* Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
* Receiver Transmitter (USART) definitions for the SAM3U and SAM4S
* Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -71,6 +71,12 @@
/* 0x0048: Reserved (USART) */
#define SAM_UART_IFR_OFFSET 0x004c /* IrDA Filter Register (USART only) */
#define SAM_UART_MAN_OFFSET 0x0050 /* Manchester Encoder Decoder Register (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_UART_LINMR_OFFSET 0x0054 /* LIN Mode Register (USART only) */
# define SAM_UART_LINIR_OFFSET 0x0058 /* LIN Identifier Register (USART only) */
#endif
#define SAM_UART_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register (USART only) */
#define SAM_UART_WPSR_OFFSET 0x00e8 /* Write Protect Status Register (USART only) */
/* 0x005c-0xf8: Reserved (USART) */
@ -114,6 +120,12 @@
#define SAM_USART_NER(n) (SAM_USARTN_BASE(n)+SAM_UART_NER_OFFSET)
#define SAM_USART_IFR(n) (SAM_USARTN_BASE(n)+SAM_UART_IFR_OFFSET)
#define SAM_USART_MAN(n) (SAM_USARTN_BASE(n)+SAM_UART_MAN_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_USART_LINMR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINMR_OFFSET)
# define SAM_USART_LINIR(n) (SAM_USARTN_BASE(n)+SAM_UART_LINIR_OFFSET)
#endif
#define SAM_USART_WPMR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPMR_OFFSET)
#define SAM_USART_WPSR(n) (SAM_USARTN_BASE(n)+SAM_UART_WPSR_OFFSET)
#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET)
@ -133,6 +145,12 @@
#define SAM_USART0_NER (SAM_USART0_BASE+SAM_UART_NER_OFFSET)
#define SAM_USART0_IFR (SAM_USART0_BASE+SAM_UART_IFR_OFFSET)
#define SAM_USART0_MAN (SAM_USART0_BASE+SAM_UART_MAN_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_USART0_LINMR (SAM_USART0_BASE+SAM_UART_LINMR_OFFSET)
# define SAM_USART0_LINIR (SAM_USART0_BASE+SAM_UART_LINIR_OFFSET)
#endif
#define SAM_USART0_WPMR (SAM_USART0_BASE+SAM_UART_WPMR_OFFSET)
#define SAM_USART0_WPSR (SAM_USART0_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET)
@ -152,6 +170,12 @@
#define SAM_USART1_NER (SAM_USART1_BASE+SAM_UART_NER_OFFSET)
#define SAM_USART1_IFR (SAM_USART1_BASE+SAM_UART_IFR_OFFSET)
#define SAM_USART1_MAN (SAM_USART1_BASE+SAM_UART_MAN_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_USART1_LINMR (SAM_USART1_BASE+SAM_UART_LINMR_OFFSET)
# define SAM_USART1_LINIR (SAM_USART1_BASE+SAM_UART_LINIR_OFFSET)
#endif
#define SAM_USART1_WPMR (SAM_USART1_BASE+SAM_UART_WPMR_OFFSET)
#define SAM_USART1_WPSR (SAM_USART1_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET)
@ -171,6 +195,12 @@
#define SAM_USART2_NER (SAM_USART2_BASE+SAM_UART_NER_OFFSET)
#define SAM_USART2_IFR (SAM_USART2_BASE+SAM_UART_IFR_OFFSET)
#define SAM_USART2_MAN (SAM_USART2_BASE+SAM_UART_MAN_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_USART2_LINMR (SAM_USART2_BASE+SAM_UART_LINMR_OFFSET)
# define SAM_USART2_LINIR (SAM_USART2_BASE+SAM_UART_LINIR_OFFSET)
#endif
#define SAM_USART2_WPMR (SAM_USART2_BASE+SAM_UART_WPMR_OFFSET)
#define SAM_USART2_WPSR (SAM_USART2_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET)
@ -190,6 +220,12 @@
#define SAM_USART3_NER (SAM_USART3_BASE+SAM_UART_NER_OFFSET)
#define SAM_USART3_IFR (SAM_USART3_BASE+SAM_UART_IFR_OFFSET)
#define SAM_USART3_MAN (SAM_USART3_BASE+SAM_UART_MAN_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_USART3_LINMR (SAM_USART3_BASE+SAM_UART_LINMR_OFFSET)
# define SAM_USART3_LINIR (SAM_USART3_BASE+SAM_UART_LINIR_OFFSET)
#endif
#define SAM_USART3_WPMR (SAM_USART3_BASE+SAM_UART_WPMR_OFFSET)
#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET)
@ -217,6 +253,11 @@
#define UART_CR_RTSDIS (1 << 19) /* Bit 19: Request to Send Disable (USART only) */
#define UART_CR_RCS (1 << 19) /* Bit 19: Release SPI Chip Select (USART SPI mode only) */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_CR_LINABT (1 << 20) /* Bit 20: Abort LIN Transmission */
# define UART_CR_LINWKUP (1 << 21) /* Bit 21: Send LIN Wakeup Signal */
#endif
/* UART Mode Register and USART Mode Register (UART MODE) */
#define UART_MR_MODE_SHIFT (0) /* Bits 0-3: (USART only) */
@ -227,6 +268,10 @@
# define UART_MR_MODE_ISO7816_0 (4 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 0 */
# define UART_MR_MODE_ISO7816_1 (6 << UART_MR_MODE_SHIFT) /* IS07816 Protocol: T = 1 */
# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_MR_MODE_LINMSTR (10 << UART_MR_MODE_SHIFT) /* LIN Master */
# define UART_MR_MODE_LINSLV (11 << UART_MR_MODE_SHIFT) /* LIN Slave */
#endif
# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master (SPI mode only) */
# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave (SPI mode only) */
#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection (USART only) */
@ -302,10 +347,16 @@
#define UART_INT_RXBUFF (1 << 12) /* Bit 12: Buffer Full Interrupt (Common) */
#define UART_INT_NACK (1 << 13) /* Bit 13: Non Acknowledge Interrupt (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_INT_LINBK (1 << 13) /* Bit 13: LIN Break Sent or Break Received Interrupt */
# define UART_INT_LINID (1 << 14) /* Bit 14: LIN Identifier Sent or Identifier Received Interrupt */
# define UART_INT_LINTC (1 << 15) /* Bit 15: LIN Transfer Completed Interrupt */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S)
# define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change Enable */
# define UART_INT_DSRIC (1 << 17) /* Bit 17: Data Set Ready Input Change Enable */
# define UART_INT_DCDIC (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt Enable */
# define UART_INT_RIIC (1 << 16) /* Bit 16: Ring Indicator Input Change */
# define UART_INT_DSRIC (1 << 17) /* Bit 17: Data Set Ready Input Change */
# define UART_INT_DCDIC (1 << 18) /* Bit 18: Data Carrier Detect Input Change Interrupt */
#endif
#define UART_INT_CTSIC (1 << 19) /* Bit 19: Clear to Send Input Change Interrupt (USART only) */
@ -317,9 +368,24 @@
# define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_SR_CTS (1 << 23) /* Bit 23: Image of CTS Input */
# define UART_SR_LINBLS (1 << 23) /* Bit 23: LIN Bus Line Status */
#endif
#define UART_INT_MANE (1 << 24) /* Bit 24: Manchester Error Interrupt (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_INT_LINBE (1 << 25) /* Bit 25: LIN Bus Error Interrupt */
# define UART_INT_LINISFE (1 << 26) /* Bit 26: LIN Inconsistent Synch Field Error Interrupt */
# define UART_INT_LINIPE (1 << 27) /* Bit 27: LIN Identifier Parity Interrupt */
# define UART_INT_LINCE (1 << 28) /* Bit 28: LIN Checksum Error Interrupt */
# define UART_INT_LINSNRE (1 << 29) /* Bit 29: LIN Slave Not Responding Error Interrupt */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_INT_ALLINTS 0x3f08ffff
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# define UART_INT_ALLINTS 0x010f3fff
#else
# define UART_INT_ALLINTS 0x01083fff
@ -404,6 +470,33 @@
#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation (USART only) */
/* LIN Mode Register (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_LINMR_
# define UART_LINMR_NACT_SHIFT (0) /* Bits 0-1: LIN Node Action */
# define UART_LINMR_NACT_MASK (3 << UART_LINMR_NACT_SHIFT)
# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */
# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */
# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does not transmit or receive response */
# define UART_LINMR_PARDIS (1 << 2) /* Bit 2: Parity Disable */
# define UART_LINMR_CHKDIS (1 << 3) /* Bit 3: Checksum Disable */
# define UART_LINMR_CHKTYP (1 << 4) /* Bit 4: Checksum Type */
# define UART_LINMR_DLM (1 << 5) /* Bit 5: Data Length Mode */
# define UART_LINMR_FSDIS (1 << 6) /* Bit 6: Frame Slot Mode Disable */
# define UART_LINMR_WKUPTYP (1 << 7) /* Bit 7: Wakeup Signal Type */
# define UART_LINMR_DLC_SHIFT (8) /* Bits 8-15: Data Length Control */
# define UART_LINMR_DLC_MASK (0xff << UART_LINMR_DLC_SHIFT)
# define UART_LINMR_PDCM (1 << 0) /* Bit 0: PDC Mode */
#endif
/* LIN Identifier Register (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
# define UART_LINIR_MASK 0xff /* Bits 0-7: Identifier Character */
#endif
/* USART Write Protect Mode Register (USART only) */
#define UART_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable (USART only) */

3
arch/arm/src/sam34/chip/sam3u_wdt.h
View File

@ -1,6 +1,6 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_wdt.h
* Watchdog Timer (WDT) definitions for the SAM3U and SAM4S
* Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -68,6 +68,7 @@
#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT)
/* Watchdog Timer Mode Register */

5
arch/arm/src/sam34/sam3u_clockconfig.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/chip/sam3u_clockconfig.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -66,7 +66,8 @@
#define BOARD_CKGR_MOR (PMC_CKGR_MOR_KEY | BOARD_CKGR_MOR_MOSCXTST | \
PMC_CKGR_MOR_MOSCRCEN | PMC_CKGR_MOR_MOSCXTEN)
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
defined(CONFIG_ARCH_CHIP_SAM3X)
# define BOARD_CKGR_PLLAR (PMC_CKGR_PLLAR_ONE | BOARD_CKGR_PLLAR_MUL | \
BOARD_CKGR_PLLAR_STMODE | BOARD_CKGR_PLLAR_COUNT | \
BOARD_CKGR_PLLAR_DIV)

8
arch/arm/src/sam34/sam_allocateheap.c
View File

@ -54,9 +54,6 @@
#include "chip.h"
#include "sam_mpuinit.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
#endif
/****************************************************************************
* Private Definitions
****************************************************************************/
@ -97,9 +94,10 @@
# define CONFIG_ARCH_EXTSRAM3SIZE 0
#endif
/* SAM3U Unique memory configurations */
/* SAM3U, SAM3X, and SAM3A Unique memory configurations */
#ifdef CONFIG_ARCH_CHIP_SAM3U
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# ifdef CONFIG_SAM34_NAND
# undef SAM34_NFCSRAM_SIZE
# define SAM34_NFCSRAM_SIZE 0

11
arch/arm/src/sam34/sam_lowputc.c
View File

@ -51,12 +51,11 @@
#include "sam_periphclks.h"
#include "sam_lowputc.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam3u_uart.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "chip/sam4l_usart.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam3u_uart.h"
#else
# error Unknown UART
#endif
@ -143,12 +142,14 @@
/* Select MCU-specific settings
*
* For the SAM3U, the USARTs are driven by the main clock.
* For the SAM3U, SAM3A, and SAM3X the USARTs are driven by the main clock
* (This could be the MCK/8 but that option has not yet been necessary).
* For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
* selected by the PBADIVMASK register.
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
#elif defined(CONFIG_ARCH_CHIP_SAM4L)

10
arch/arm/src/sam34/sam_serial.c
View File

@ -60,7 +60,9 @@
#include "os_internal.h"
#include "chip.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# include "chip/sam3u_uart.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "chip/sam4l_usart.h"
@ -309,12 +311,14 @@
/* Select MCU-specific settings
*
* For the SAM3U, the USARTs are driven by the main clock.
* For the SAM3U, SAM3A, and SAM3X the USARTs are driven by the main clock
* (This could be the MCK/8 but that option has not yet been necessary).
* For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
* selected by the PBADIVMASK register.
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
# define SAM_USART_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
#elif defined(CONFIG_ARCH_CHIP_SAM4L)

13
arch/arm/src/sam34/sam_spi.c
View File

@ -63,7 +63,7 @@
#include "chip/sam_spi.h"
#include "chip/sam_pinmap.h"
#ifdef CONFIG_SAM34_SPI0
#if defined(CONFIG_SAM34_SPI0) || defined(CONFIG_SAM34_SPI1)
/****************************************************************************
* Definitions
@ -71,11 +71,12 @@
/* Configuration ************************************************************/
/* Select MCU-specific settings
*
* For the SAM3U, SPI is driven by the main clock.
* For the SAM4L, SPI driven by CLK_SPI which is the PBB clock.
* For the SAM3U, SAM3A, and SAM3X SPI is driven by the main clock.
* For the SAM4L, SPI is driven by CLK_SPI which is the PBB clock.
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
defined(CONFIG_ARCH_CHIP_SAM3X)
# define SAM_SPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# define SAM_SPI_CLOCK BOARD_PBB_FREQUENCY /* PBB frequency */
@ -83,6 +84,10 @@
# error Unrecognized SAM architecture
#endif
#ifdef CONFIG_SAM34_SPI1
# error Support for SPI1 has not yet been implemented
#endif
/* Debug *******************************************************************/
/* Check if SPI debut is enabled (non-standard.. no support in
* include/debug.h

6
arch/arm/src/sam34/sam_timerisr.c
View File

@ -57,12 +57,14 @@
****************************************************************************/
/* Select MCU-specific settings
*
* For the SAM3U, Systick is driven by the main clock.
* For the SAM3U, SAM3A, and SAM3X, Systickis driven by the main clock
* (This could be the MCK/8 but that option has not yet been necessary).
* For the SAM4L, Systick is driven by the CPU clock which is just the main
* clock divided down.
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_SYSTICK_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */
#elif defined(CONFIG_ARCH_CHIP_SAM4L) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* CPU frequency */

2
configs/sam3u-ek/src/up_lcd.c
View File

@ -126,7 +126,7 @@
#include "up_arch.h"
#include "sam_gpio.h"
#include "chip/sam3u_pmc.h"
#include "chip/sam_smc.h"
#include "chip/sam3u_smc.h"
#include "sam3u-ek.h"
/**************************************************************************************

2
configs/sam4s-xplained/src/sam_sram.c
View File

@ -43,7 +43,7 @@
#include "up_arch.h"
#include "sam4s_periphclks.h"
#include "chip/sam_smc.h"
#include "chip/sam3u_smc.h"
#include "sam4s-xplained.h"
#ifdef CONFIG_ARCH_EXTSRAM0