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arch: mips: nxstyle fixes

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Nxstyle fixed to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-30 16:53:11 +02:00 committed by David Sidrane
parent f3f10a3b96
commit 29529e8758
63 changed files with 1405 additions and 1012 deletions
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96
arch/mips/include/mips32/cp0.h
View File

@ -31,6 +31,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
@ -83,19 +84,22 @@
* Function: Randomly generated index into the TLB array
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing a random TLB index. The valid width is some fixed
* number, 'n', but the upper bits are padded so that no fields need be defined for this
* register.
* This is a 32-bit register containing a random TLB index.
* The valid width is some fixed number, 'n', but the upper bits are
* padded so that no fields need be defined for this register.
*/
/* Register Number: 2 Sel: 0 Name: EntryLo0
* Function: Low-order portion of the TLB entry for even-numbered virtual pages
* Function: Low-order portion of the TLB entry for even-numbered virtual
* pages
* Compliance Level: EntryLo0 is Required for a TLB-based MMU; Optional
* otherwise.
* otherwise.
*
* Register Number: 3 Sel: 0 Name: EntryLo1
* Function: Low-order portion of the TLB entry for odd-numbered virtual pages
* Compliance Level: EntryLo1 is Required for a TLB-based MMU; Optional otherwise.
* Function: Low-order portion of the TLB entry for odd-numbered virtual
* pages
* Compliance Level: EntryLo1 is Required for a TLB-based MMU; Optional
* otherwise.
*/
#define CP0_ENTRYLO_G (1 << 0) /* Bit 0: Global bit */
@ -139,25 +143,26 @@
* Function: Controls the number of fixed (“wired”) TLB entries
* Compliance Level: Required for TLB-based MMUs; Optional otherwise.
*
* This is a 32-bit register containing the TLB wired boundary. The valid width is some
* fixed number, 'n', but the upper bits are padded so that no fields need be defined for
* this register.
* This is a 32-bit register containing the TLB wired boundary.
* The valid width is some fixed number, 'n', but the upper bits are
* padded so that no fields need be defined for this register.
*
* Register Number: 7 Sel: all (Reserved for future extensions)
*
* Register Number: 8 Sel: 0 Name: BadVAddr
* Function: Reports the address for the most recent address-related exception
* Function: Reports the address for the most recent address-related
* exception
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be
* defined for this register.
*
* Register Number: 9 Sel: 0 Name: Count
* Function: Processor cycle count
* Compliance Level: Required.
*
* This register contains a 32-bit count value; No fields need be defined for this
* register.
* This register contains a 32-bit count value; No fields need be
* defined for this register.
*
* Register Number: 9 Sel: 6-7 (Available for implementation dependent user)
*/
@ -176,8 +181,8 @@
* Function: Timer interrupt control
* Compliance Level: Required.
*
* This register contains a 32-bit compare value; No fields need be defined for this
* register.
* This register contains a 32-bit compare value; No fields need be defined
* for this register.
*
* Register Number: 11 Sel: 6-7 (Available for implementation dependent user)
*/
@ -262,6 +267,7 @@
# define CP0_CAUSE_EXCCODE_WATCH (23 << CP0_CAUSE_EXCCODE_SHIFT) /* WatchHi/WatchLo address */
# define CP0_CAUSE_EXCCODE_MCHECK (24 << CP0_CAUSE_EXCCODE_SHIFT) /* Machine check */
# define CP0_CAUSE_EXCCODE_CACHEERR (30 << CP0_CAUSE_EXCCODE_SHIFT) /* Cache error */
#define CP0_CAUSE_IP0 (1 << 8) /* Bit 8: Controls request for software interrupt 0 */
#define CP0_CAUSE_IP1 (1 << 9) /* Bit 9: Controls request for software interrupt 1 */
#define CP0_CAUSE_IP_SHIFT (10) /* Bits 10-15: Pending external interrupts */
@ -272,6 +278,7 @@
# define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */
# define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */
# define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */
#define CP0_CAUSE_WP (1 << 22) /* Watch exception was deferred */
#define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */
#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */
@ -282,8 +289,8 @@
* Function: Program counter at last exception
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be defined
* for this register.
*/
/* Register Number: 15 Sel: 0 Name: PRId
@ -315,6 +322,7 @@
# define CP0_CONFIG_MT_TLB (1 << CP0_CONFIG_MT_SHIFT) /* Standard TLB */
# define CP0_CONFIG_MT_BAT (2 << CP0_CONFIG_MT_SHIFT) /* Standard BAT */
# define CP0_CONFIG_MT_FIXED (3 << CP0_CONFIG_MT_SHIFT) /* Standard fixed mapping */
#define CP0_CONFIG_AR_SHIFT (10) /* Bits 10-12: Architecture revision level */
#define CP0_CONFIG_AR_MASK (7 << CP0_CONFIG_AR_SHIFT)
# define CP0_CONFIG_AR_REV1 (0 << CP0_CONFIG_AR_SHIFT)
@ -324,6 +332,7 @@
# define CP0_CONFIG_AT_MIPS32 (0 << CP0_CONFIG_AT_SHIFT) /* MIPS32 */
# define CP0_CONFIG_AT_MIPS64CMP (0 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with 32-bit compatibility segments */
# define CP0_CONFIG_AT_MIPS64 (1 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with access to all address segments */
#define CP0_CONFIG_BE (1 << 15) /* Bit 15: Processor is running in big-endian mode */
#define CP0_CONFIG_IMPL_SHIFT (16) /* Bits 16-30: Implementation dependent */
#define CP0_CONFIG_IMPL_MASK (0x7fff << CP0_CONFIG_IMPL_SHIFT)
@ -353,6 +362,7 @@
# define CP0_CONFIG1_DA_6WAY (5 << CP0_CONFIG1_DA_SHIFT) /* 6-way */
# define CP0_CONFIG1_DA_7WAY (6 << CP0_CONFIG1_DA_SHIFT) /* 7-way */
# define CP0_CONFIG1_DA_8WAY (7 << CP0_CONFIG1_DA_SHIFT) /* 8-way */
#define CP0_CONFIG1_DL_SHIFT (10) /* Bits 10-12: Dcache line size */
#define CP0_CONFIG1_DL_MASK (7 << CP0_CONFIG1_DL_SHIFT)
# define CP0_CONFIG1_DL_NONE (0 << CP0_CONFIG1_DL_SHIFT) /* No Dcache present */
@ -362,6 +372,7 @@
# define CP0_CONFIG1_DL_32BYTES (4 << CP0_CONFIG1_DL_SHIFT) /* 32 bytes */
# define CP0_CONFIG1_DL_64BYTES (5 << CP0_CONFIG1_DL_SHIFT) /* 64 bytes */
# define CP0_CONFIG1_DL_128BYTES (6 << CP0_CONFIG1_DL_SHIFT) /* 128 bytes */
#define CP0_CONFIG1_DS_SHIFT (13) /* Bits 13-15: Dcache sets per way */
#define CP0_CONFIG1_DS_MASK (7 << CP0_CONFIG1_DS_SHIFT)
# define CP0_CONFIG1_DS_64SETS (0 << CP0_CONFIG1_DS_SHIFT)
@ -381,6 +392,7 @@
# define CP0_CONFIG1_IA_6WAY (5 << CP0_CONFIG1_IA_SHIFT) /* 6-way */
# define CP0_CONFIG1_IA_7WAY (6 << CP0_CONFIG1_IA_SHIFT) /* 7-way */
# define CP0_CONFIG1_IA_8WAY (7 << CP0_CONFIG1_IA_SHIFT) /* 8-way */
#define CP0_CONFIG1_IL_SHIFT (19) /* Bits 19-21: Icache line size */
#define CP0_CONFIG1_IL_MASK (7 << CP0_CONFIG1_IL_SHIFT)
# define CP0_CONFIG1_IL_NONE (0 << CP0_CONFIG1_IL_SHIFT) /* No Dcache present */
@ -390,6 +402,7 @@
# define CP0_CONFIG1_IL_32BYTES (4 << CP0_CONFIG1_IL_SHIFT) /* 32 bytes */
# define CP0_CONFIG1_IL_64BYTES (5 << CP0_CONFIG1_IL_SHIFT) /* 64 bytes */
# define CP0_CONFIG1_IL_128BYTES (6 << CP0_CONFIG1_IL_SHIFT) /* 128 bytes */
#define CP0_CONFIG1_IS_SHIFT (22) /* Bits 22-24: Icache sets per way */
#define CP0_CONFIG1_IS_MASK (7 << CP0_CONFIG1_IS_SHIFT)
# define CP0_CONFIG1_IS_64SETS (0 << CP0_CONFIG1_IS_SHIFT)
@ -413,8 +426,8 @@
#define CP0_CONFIG2_M (1 << 31) /* Bit 31: Config3 register is present */
/* Register Number: 16 Sel: 3 Name: Config3
* Function: Configuration register 3 (Section 50: "CPU for Devices with MIPS32
* microAptive and M-Class Cores")
* Function: Configuration register 3 (Section 50: "CPU for Devices with
* MIPS32 microAptive and M-Class Cores")
* Compliance Level: Optional.
*/
@ -435,25 +448,30 @@
# define CP0_CONFIG3_ISA_MICROMIPS (1 << CP0_CONFIG3_ISA_SHIFT) /* Only microMIPS is implemented */
# define CP0_CONFIG3_ISA_BOTHMIP32 (2 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, MIPS32 on reset */
# define CP0_CONFIG3_ISA_BOTHUMIPS (3 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, microMIPS on reset */
#define CP0_CONFIG3_ISAONEXC (1 << 16) /* Bit 16: ISA on Exception bit */
#define CP0_CONFIG3_MCU (1 << 17) /* Bit 17: MIPS MCU ASE Implemented bit */
#define CP0_CONFIG3_MMAR_SHIFT (18) /* Bits 18-20: microMIPS Architecture Revision level bits */
#define CP0_CONFIG3_MMAR_MASK (7 << CP0_CONFIG3_MMAR_SHIFT)
# define CP0_CONFIG3_MMAR_REL1 (0 << CP0_CONFIG3_MMAR_SHIFT) /* Release 1 */
#define CP0_CONFIG3_IPLW_SHIFT (21) /* Bits 21-22: Width of the Status IPL and Cause RIPL bits */
#define CP0_CONFIG3_IPLW_MASK (3 << CP0_CONFIG3_IPLW_SHIFT)
# define CP0_CONFIG3_IPLW_6BITS (0 << CP0_CONFIG3_IPLW_SHIFT) /* 6 bits */
# define CP0_CONFIG3_IPLW_8BITS (1 << CP0_CONFIG3_IPLW_SHIFT) /* 8 bits */
#define CP0_CONFIG3_M (1 << 31) /* Bit 31: Config4 register is present */
/* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */
/* Register Number: 16 Sel: 6-7
* (Available for implementation dependent use)
*/
/* Register Number: 17 Sel: 0 Name: LLAddr
* Function: Load linked address
* Compliance Level: Optional.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be defined
* for this register.
*/
/* Register Number: 18 Sel: 0-n Name: WatchLo
@ -494,8 +512,8 @@
* Function: Program counter at last EJTAG debug exception
* Compliance Level: Optional, part of the EJTAG specification.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be defined
* for this register.
*/
/* Register Number: 25 Sel: 0-n Name: PerfCnt
@ -516,19 +534,22 @@
* Function: Parity/ECC error control and status
* Compliance Level: Optional.
*
* The bit definitions within the ErrCtl register are implementation dependent.
* The bit definitions within the ErrCtl register are implementation
* dependent.
*
* Register Number: 27 Sel: 0-3 Name: CacheErr
* Function: Cache parity error control and status
* Compliance Level: Optional.
*
* The bit definitions within the CacheErr register are implementation dependent.
* The bit definitions within the CacheErr register are implementation
* dependent.
*
* Register Number: 28 Sel: 0 Name: TagLo
* Function: Low-order portion of cache tag interface
* Compliance Level: Required if a cache is implemented; Optional otherwise.
*
* The bit definitions within the TagLo register are implementation dependent.
* The bit definitions within the TagLo register are implementation
* dependent.
*
* Register Number: 28 Sel: 1, 3 Name: DataLo
* Function: The DataLo and DataHi registers are read-only registers that
@ -536,13 +557,15 @@
* diagnostic operation only.
* Compliance Level: Optional.
*
* The bit definitions within the DataLo register are implementation dependent.
* The bit definitions within the DataLo register are implementation
* dependent.
*
* Register Number: 29 Sel: 0 Name: TagHi
* Function: High-order portion of cache tag interface
* Compliance Level: Required if a cache is implemented; Optional otherwise.
*
* The bit definitions within the TagHi register are implementation dependent.
* The bit definitions within the TagHi register are implementation
* dependent.
*
* Register Number: 29 Sel: 1, 3 Name: DataHi
* Function: The DataLo and DataHi registers are read-only registers that
@ -550,21 +573,22 @@
* diagnostic operation only.
* Compliance Level: Optional.
*
* The bit definitions within the DataHi register are implementation dependent.
* The bit definitions within the DataHi register are implementation
* dependent.
*
* Register Number: 30 Sel: 0 Name: ErrorEPC
* Function: Program counter at last error
* Compliance Level: Required.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be defined
* for this register.
*
* Register Number: 31 Sel: 0 Name: DESAVE
* Function: EJTAG debug exception save register
* Compliance Level: Optional, part of the EJTAG specification.
*
* This register contains a 32-bit address value; No fields need be defined for this
* register.
* This register contains a 32-bit address value; No fields need be defined
* for this register.
*/
/****************************************************************************

15
arch/mips/include/mips32/irq.h
View File

@ -35,7 +35,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* The global pointer (GP) does not need to be saved in the "normal," flat
* NuttX build. However, it would be necessary to save the GP if this is
* a KERNEL build or if NXFLAT is supported.
@ -46,13 +48,16 @@
# define MIPS32_SAVE_GP 1
#endif
/* If this is a kernel build, how many nested system calls should we support? */
/* If this is a kernel build,
* how many nested system calls should we support?
*/
#ifndef CONFIG_SYS_NNEST
# define CONFIG_SYS_NNEST 2
#endif
/* Register save state structure ********************************************/
/* Co processor registers */
#define REG_MFLO_NDX 0
@ -61,7 +66,9 @@
#define REG_STATUS_NDX 3
/* General pupose registers */
/* $0: Zero register does not need to be saved */
/* $1: at_reg, assembler temporary */
#define REG_R1_NDX 4
@ -508,7 +515,8 @@ extern "C"
*
* NOTE: This function should never be called from application code and,
* as a general rule unless you really know what you are doing, this
* function should not be called directly from operation system code either:
* function should not be called directly from operation system code
* either:
* Typically, the wrapper functions, enter_critical_section() is probably
* what you really want.
*
@ -531,7 +539,8 @@ irqstate_t up_irq_save(void);
*
* NOTE: This function should never be called from application code and,
* as a general rule unless you really know what you are doing, this
* function should not be called directly from operation system code either:
* function should not be called directly from operation system code
* either:
* Typically, the wrapper functions, leave_critical_section() is probably
* what you really want.
*

4
arch/mips/include/mips32/registers.h
View File

@ -91,7 +91,9 @@
#define sp $29
/* Register 30 may be either an additional static register or a frame pointer */
/* Register 30 may be either an additional static register or a frame
* pointer
*/
#define s8 $30
#define fp $30

9
arch/mips/include/mips32/syscall.h
View File

@ -42,10 +42,11 @@
#define SYS_syscall 0x00
/* Configuration ************************************************************/
/* SYS call 1 and 2 are defined for internal use by the PIC32MX port (see
* arch/mips/include/mips32/syscall.h). In addition, SYS call 3 is the
* return from a SYS call in kernel mode. The first four syscall values must,
* therefore, be reserved (0 is not used).
* return from a SYS call in kernel mode. The first four syscall values
* must, therefore, be reserved (0 is not used).
*/
#ifdef CONFIG_BUILD_KERNEL
@ -57,11 +58,13 @@
#endif
/* sys_call macros **********************************************************/
/* System calls with 3 parameters and fewer are handled by sys_call0
* (sys_call1, sys_call2, and sys_call3 are aliases for sys_call0).
* This is because the parameters are passed in a0-a3. a0 is reserved for
* the syscall number leaving up to three additional parameters that can be
* passed in registers. The remainder would have to be pushed onto the stack.
* passed in registers. The remainder would have to be pushed onto the
* stack.
*
* Instead, these macros are provided which handle parameters four, five and
* six in a non-standard way: The use s0 ($7), s1 ($8), and s2 ($9) to pass

4
arch/mips/include/pic32mx/chip.h
View File

@ -30,6 +30,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#if defined(CONFIG_ARCH_CHIP_PIC32MX110F016B)
@ -2385,7 +2386,8 @@
# error "Unrecognized PIC32 device
#endif
/* IPL priority levels *****************************************************/
/* IPL priority levels ******************************************************/
/* These priorities will be used by the core to properly disable/mask
* interrupts.
*/

9
arch/mips/include/pic32mx/cp0.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
@ -107,8 +108,10 @@
* NOTES:
* 1. The following are reserved bits in the PIC32:
* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space
* (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space
* (Not MIPS32)
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
@ -201,7 +204,7 @@
#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit */.
/* Register Number: 14 Sel: 0 Name: EPC
* Function: Program counter at last exception

27
arch/mips/include/pic32mz/chip.h
View File

@ -31,9 +31,9 @@
* Pre-processor Definitions
****************************************************************************/
/* Available in 64/100/124/144 pin packages. Description here is specifically
* for the 144 pin package (PIC32MZ2048ECH144) and should be reviewed for
* other parts.
/* Available in 64/100/124/144 pin packages. Description here is
* specifically for the 144 pin package (PIC32MZ2048ECH144) and should be
* reviewed for other parts.
*/
#if defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECH)
@ -66,9 +66,9 @@
# define CHIP_NJTAG 1 /* Has JTAG */
# define CHIP_NTRACE 1 /* Has trace capability */
/* Available in 64/100/124/144 pin packages. Description here is specifically
* for the 144 pin package (PIC32MZ2048ECM144) and should be reviewed for
* other parts.
/* Available in 64/100/124/144 pin packages. Description here is
* specifically for the 144 pin package (PIC32MZ2048ECM144) and should
* be reviewed for other parts.
*/
#elif defined(CONFIG_ARCH_CHIP_PIC32MZ2048ECM)
@ -101,11 +101,11 @@
# define CHIP_NJTAG 1 /* Has JTAG */
# define CHIP_NTRACE 1 /* Has trace capability */
/* Available in 64/100/124/144 pin packages. Description here is specifically
* for the 124 and 144 pin packages (PIC32MZ2048EFH1100, and
/* Available in 64/100/124/144 pin packages. Description here is
* specifically for the 124 and 144 pin packages (PIC32MZ2048EFH1100, and
* PIC32MZ2048EFH144). The PIC32MZ2048EFH1100 differs in that it has only
* 40 ADC channels. The PIC32MZ2048EFH1064 differs in that it has only 24 ADC
* channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are
* 40 ADC channels. The PIC32MZ2048EFH1064 differs in that it has only 24
* ADC channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are
* additional differences between all family members in the number of pins
* how they may be mapped.
*/
@ -140,8 +140,8 @@
# define CHIP_NJTAG 1 /* Has JTAG */
# define CHIP_NTRACE 1 /* Has trace capability */
/* Available in 64/100/124/144 pin packages. Description here is specifically
* for the 124, and 144 pin packages (PIC32MZ2048EFM124, and
/* Available in 64/100/124/144 pin packages. Description here is
* specifically for the 124, and 144 pin packages (PIC32MZ2048EFM124, and
* PIC32MZ2048EFH144). The PIC32MZ2048EFM100 differs in that it has only 40
* ADC channels. The PIC32MZ2048EFM064 differs in that it has only 24 ADC
* channels, two fewer SPI/I2S, one fewer I2C, and no EBI. There are
@ -183,7 +183,8 @@
# error "Unrecognized PIC32MZ device"
#endif
/* IPL priority levels *****************************************************/
/* IPL priority levels ******************************************************/
/* These priorities will be used by the core to properly disable/mask
* interrupts.
*/

11
arch/mips/include/pic32mz/cp0.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
@ -191,11 +192,14 @@
* NOTES:
* 1. The following are reserved bits in the PIC32MZ:
* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space
* (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space
* (Not MIPS32)
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
* CP0_STATUS_FR Bit 26: Controls the floating point register mode (Not MIPS32)
* CP0_STATUS_FR Bit 26: Controls the floating point register mode
* (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX (Not MIPS32)
* CP0_STATUS_CU1 Bit 29: Controls access to coprocessor 1
* CP0_STATUS_CU2 Bit 30: Controls access to coprocessor 2
@ -357,6 +361,7 @@
#define CP0_CONFIG_MM_MASK (3 << CP0_CONFIG_MM_SHIFT)
# define CP0_CONFIG_MM_PROHIBITED (0 << CP0_CONFIG_MM_SHIFT) /* Merging is not allowed */
# define CP0_CONFIG_MM_ALLOWED (2 << CP0_CONFIG_MM_SHIFT) /* Merging is allowed */
#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */

1
arch/mips/src/pic32mx/chip.h
View File

@ -31,6 +31,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/

477
arch/mips/src/pic32mx/excptmacros.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/excptmacros.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
#define __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,320 +32,329 @@
#ifdef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Symbols
********************************************************************************************/
****************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.global g_intstackbase
.global g_intstackbase
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
.global g_nestlevel
.global g_nestlevel
#endif
#endif
/********************************************************************************************
/****************************************************************************
* Assembly Language Macros
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* General Usage Example:
*
* my_exception:
* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
* move a0, sp - Pass register save structure as the parameter 1
* USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack
* jal handler - Handle the exception IN=old regs OUT=new regs
* di - Disable interrupts
* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
* move a0, sp - Pass register save structure as the parameter 1
* USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack
* jal handler - Handle the exception IN=old regs OUT=new regs
* di - Disable interrupts
* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
*
********************************************************************************************/
/********************************************************************************************
****************************************************************************/
/****************************************************************************
* Name: EXCPT_PROLOGUE
*
* Description:
* Provides the "prologue" logic that should appear at the beginning of every exception
* handler.
* Provides the "prologue" logic that should appear at the beginning of
* every exception handler.
*
* On Entry:
* sp - Points to the top of the stack
* tmp - Is a register the can be modified for scratch usage (after it has been saved)
* k0 and k1 - Since we are in an exception handler, these are available for use
* tmp - Is a register the can be modified for scratch usage (after it has
* been saved)
* k0 and k1 - Since we are in an exception handler,
* these are available for use
*
* At completion:
* Register state is saved on the stack; All registers are available for usage except sp
* and k1:
* Register state is saved on the stack; All registers are available for
* usage except sp and k1:
*
* - sp points the beginning of the register save area
* - k1 holds the value of the STATUS register
*
* The following registers are modified: k0, k1, sp, a0
*
********************************************************************************************/
****************************************************************************/
.macro EXCPT_PROLOGUE, tmp
.set noat
.macro EXCPT_PROLOGUE, tmp
.set noat
/* Get the SP from the previous shadow set */
/* Get the SP from the previous shadow set */
#if 0
rdpgpr sp, sp
rdpgpr sp, sp
#endif
/* "When entering the interrupt handler routine, the interrupt controller must first
* save the current priority and exception PC counter from Interrupt Priority (IPL)
* bits (Status<15:10>) and the ErrorEPC register, respectively, on the stack. ..."
*/
/* "When entering the interrupt handler routine, the interrupt controller
* must first save the current priority and exception PC counter from
* Interrupt Priority (IPL) bits (Status<15:10>) and the ErrorEPC
* register, respectively, on the stack. ..."
*/
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS // Does not work!
mfc0 k0, MIPS32_CP0_CAUSE
mfc0 k1, MIPS32_CP0_EPC
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS /* Does not work! */
mfc0 k0, MIPS32_CP0_CAUSE
mfc0 k1, MIPS32_CP0_EPC
/* Isolate the pending interrupt level in bits 0-5 of k0 */
/* Isolate the pending interrupt level in bits 0-5 of k0 */
srl k0, k0, CP0_CAUSE_IP_SHIFT
srl k0, k0, CP0_CAUSE_IP_SHIFT
/* Create the register context stack frame large enough to hold the entire register save
* array.
*/
/* Create the register context stack frame large enough to hold the entire
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
addiu sp, sp, -XCPTCONTEXT_SIZE
/* Save the EPC and STATUS in the register context array */
/* Save the EPC and STATUS in the register context array */
sw k1, REG_EPC(sp)
mfc0 k1, MIPS32_CP0_STATUS
sw k1, REG_STATUS(sp)
sw k1, REG_EPC(sp)
mfc0 k1, MIPS32_CP0_STATUS
sw k1, REG_STATUS(sp)
/* Then insert pending interrupt level as the current mask level in the CP0 status
* register. Also clear bits 1-4 in new value of the status register:
*
* Bit 1: Exception Level
* Bit 2: Error Level
* Bit 3: (not used in PIC32MX)
* Bit 4: Operating mode == USER
*/
/* Then insert pending interrupt level as the current mask level in the CP0
* status register.
* Also clear bits 1-4 in new value of the status register:
*
* Bit 1: Exception Level
* Bit 2: Error Level
* Bit 3: (not used in PIC32MX)
* Bit 4: Operating mode == USER
*/
ins k1, k0, CP0_STATUS_IPL_SHIFT, 6
ins k1, zero, 1, 4
ins k1, k0, CP0_STATUS_IPL_SHIFT, 6
ins k1, zero, 1, 4
/* And Enable interrupts */
/* And Enable interrupts */
mtc0 k1, MIPS32_CP0_STATUS
mtc0 k1, MIPS32_CP0_STATUS
#else
/* Get the EPC and STATUS register (Don't bother with the CAUSE register if we are
* not supporting nested interrupts)
*/
/* Get the EPC and STATUS register (Don't bother with the CAUSE register if
* we are not supporting nested interrupts)
*/
mfc0 k0, MIPS32_CP0_EPC
mfc0 k1, MIPS32_CP0_STATUS
mfc0 k0, MIPS32_CP0_EPC
mfc0 k1, MIPS32_CP0_STATUS
/* Create the register context stack frame large enough to hold the entire register
* save array.
*/
/* Create the register context stack frame large enough to hold the entire
* register save array.
*/
addiu sp, sp, -XCPTCONTEXT_SIZE
addiu sp, sp, -XCPTCONTEXT_SIZE
/* Save the EPC and STATUS in the register context array */
/* Save the EPC and STATUS in the register context array */
sw k0, REG_EPC(sp)
sw k1, REG_STATUS(sp)
sw k0, REG_EPC(sp)
sw k1, REG_STATUS(sp)
#endif
/* Save floating point registers */
/* Save floating point registers */
mfhi k0
sw k0, REG_MFHI(sp)
mflo k0
sw k0, REG_MFLO(sp)
mfhi k0
sw k0, REG_MFHI(sp)
mflo k0
sw k0, REG_MFLO(sp)
/* Save general purpose registers */
/* $1: at_reg, assembler temporary */
/* Save general purpose registers */
sw $1, REG_AT(sp)
/* $1: at_reg, assembler temporary */
/* $2-$3 = v0-v1: Return value registers */
sw $1, REG_AT(sp)
sw v0, REG_V0(sp)
sw v1, REG_V1(sp)
/* $2-$3 = v0-v1: Return value registers */
/* $4-$7 = a0-a3: Argument registers */
sw v0, REG_V0(sp)
sw v1, REG_V1(sp)
sw a0, REG_A0(sp)
sw a1, REG_A1(sp)
sw a2, REG_A2(sp)
sw a3, REG_A3(sp)
/* $4-$7 = a0-a3: Argument registers */
/* $8-$15 = t0-t7: Volatile registers */
sw a0, REG_A0(sp)
sw a1, REG_A1(sp)
sw a2, REG_A2(sp)
sw a3, REG_A3(sp)
sw t0, REG_T0(sp)
sw t1, REG_T1(sp)
sw t2, REG_T2(sp)
sw t3, REG_T3(sp)
sw t4, REG_T4(sp)
sw t5, REG_T5(sp)
sw t6, REG_T6(sp)
sw t7, REG_T7(sp)
/* $8-$15 = t0-t7: Volatile registers */
/* $16-$23 = s0-s7: Static registers */
sw t0, REG_T0(sp)
sw t1, REG_T1(sp)
sw t2, REG_T2(sp)
sw t3, REG_T3(sp)
sw t4, REG_T4(sp)
sw t5, REG_T5(sp)
sw t6, REG_T6(sp)
sw t7, REG_T7(sp)
sw s0, REG_S0(sp)
sw s1, REG_S1(sp)
sw s2, REG_S2(sp)
sw s3, REG_S3(sp)
sw s4, REG_S4(sp)
sw s5, REG_S5(sp)
sw s6, REG_S6(sp)
sw s7, REG_S7(sp)
/* $16-$23 = s0-s7: Static registers */
/* $24-25 = t8-t9: More Volatile registers */
sw s0, REG_S0(sp)
sw s1, REG_S1(sp)
sw s2, REG_S2(sp)
sw s3, REG_S3(sp)
sw s4, REG_S4(sp)
sw s5, REG_S5(sp)
sw s6, REG_S6(sp)
sw s7, REG_S7(sp)
sw t8, REG_T8(sp)
sw t9, REG_T9(sp)
/* $24-25 = t8-t9: More Volatile registers */
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do not need to be
* saved.
*
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
* thread values for the GP.
*/
sw t8, REG_T8(sp)
sw t9, REG_T9(sp)
/* $26-$27 = ko-k1: Reserved for use in exception handers.
* These do not need to be saved.
*
* $28 = gp: Only needs to be saved under conditions where there are
* multiple, per- thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
sw gp, REG_GP(sp)
sw gp, REG_GP(sp)
#endif
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
sw s8, REG_S8(sp)
sw s8, REG_S8(sp)
/* $31 = ra: Return address */
/* $31 = ra: Return address */
sw ra, REG_RA(sp)
sw ra, REG_RA(sp)
/* $29 = sp: The value of the stack pointer on return from the exception. a0 is
* used as a temporary
*/
/* $29 = sp: The value of the stack pointer on return from the exception.
* a0 is used as a temporary
*/
addiu \tmp, sp, XCPTCONTEXT_SIZE
sw \tmp, REG_SP(sp)
.endm
addiu \tmp, sp, XCPTCONTEXT_SIZE
sw \tmp, REG_SP(sp)
.endm
/********************************************************************************************
/****************************************************************************
* Name: EXCPT_EPILOGUE
*
* Description:
* Provides the "epilogue" logic that should appear at the end of every exception handler.
* Provides the "epilogue" logic that should appear at the end of every
* exception handler.
*
* On input:
* regs - points to the register save structure. NOTE: This *may not* be an address
* lying in a stack! It might be an address in a TCB!
* regs - points to the register save structure.
* NOTE: This *may not* be an address lying in a stack!
* It might be an address in a TCB!
* Interrupts are disabled (via 'di')
*
* On completion:
* All registers restored
* eret is executed to return from the exception
* eret is executed to return from the exception
*
********************************************************************************************/
****************************************************************************/
.macro EXCPT_EPILOGUE, regs
.set noat
.macro EXCPT_EPILOGUE, regs
.set noat
/* Since interrupts are disabled via di can now use k0 and k1 again. Use k1 as the
* pointer to the register save array.
*/
/* Since interrupts are disabled via di can now use k0 and k1 again.
* Use k1 as the pointer to the register save array.
*/
move k1, \regs
move k1, \regs
/* Restore the floating point register state */
/* Restore the floating point register state */
lw k0, REG_MFLO(k1)
mtlo k0
lw k0, REG_MFHI(k1)
mthi k0
lw k0, REG_MFLO(k1)
mtlo k0
lw k0, REG_MFHI(k1)
mthi k0
/* Restore general purpose registers */
/* $1: at_reg, assembler temporary */
/* Restore general purpose registers */
lw $1, REG_AT(k1)
/* $1: at_reg, assembler temporary */
/* $2-$3 = v0-v1: Return value registers */
lw $1, REG_AT(k1)
lw v0, REG_V0(k1)
lw v1, REG_V1(k1)
/* $2-$3 = v0-v1: Return value registers */
/* $4-$7 = a0-a3: Argument registers */
lw v0, REG_V0(k1)
lw v1, REG_V1(k1)
lw a0, REG_A0(k1)
lw a1, REG_A1(k1)
lw a2, REG_A2(k1)
lw a3, REG_A3(k1)
/* $4-$7 = a0-a3: Argument registers */
/* $8-$15 = t0-t7: Volatile registers */
lw a0, REG_A0(k1)
lw a1, REG_A1(k1)
lw a2, REG_A2(k1)
lw a3, REG_A3(k1)
lw t0, REG_T0(k1)
lw t1, REG_T1(k1)
lw t2, REG_T2(k1)
lw t3, REG_T3(k1)
lw t4, REG_T4(k1)
lw t5, REG_T5(k1)
lw t6, REG_T6(k1)
lw t7, REG_T7(k1)
/* $8-$15 = t0-t7: Volatile registers */
/* $16-$23 = s0-s7: Static registers */
lw t0, REG_T0(k1)
lw t1, REG_T1(k1)
lw t2, REG_T2(k1)
lw t3, REG_T3(k1)
lw t4, REG_T4(k1)
lw t5, REG_T5(k1)
lw t6, REG_T6(k1)
lw t7, REG_T7(k1)
lw s0, REG_S0(k1)
lw s1, REG_S1(k1)
lw s2, REG_S2(k1)
lw s3, REG_S3(k1)
lw s4, REG_S4(k1)
lw s5, REG_S5(k1)
lw s6, REG_S6(k1)
lw s7, REG_S7(k1)
/* $16-$23 = s0-s7: Static registers */
/* $24-25 = t8-t9: More Volatile registers */
lw s0, REG_S0(k1)
lw s1, REG_S1(k1)
lw s2, REG_S2(k1)
lw s3, REG_S3(k1)
lw s4, REG_S4(k1)
lw s5, REG_S5(k1)
lw s6, REG_S6(k1)
lw s7, REG_S7(k1)
lw t8, REG_T8(k1)
lw t9, REG_T9(k1)
/* $24-25 = t8-t9: More Volatile registers */
/* $26-$27 = ko-k1: Reserved for use in exception handers. These do not need to be
* saved.
*
* $28 = gp: Only needs to be saved under conditions where there are multiple, per-
* thread values for the GP.
*/
lw t8, REG_T8(k1)
lw t9, REG_T9(k1)
/* $26-$27 = ko-k1: Reserved for use in exception handers.
* These do not need to be saved.
*
* $28 = gp: Only needs to be saved under conditions where there
* are multiple, per- thread values for the GP.
*/
#ifdef MIPS32_SAVE_GP
lw gp, REG_GP(k1)
lw gp, REG_GP(k1)
#endif
/* $29 = sp: Stack pointer */
/* $29 = sp: Stack pointer */
lw sp, REG_SP(k1)
lw sp, REG_SP(k1)
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
/* $30 = either s8 or fp: Depends if a frame pointer is used or not */
lw s8, REG_S8(k1)
lw s8, REG_S8(k1)
/* $31 = ra: Return address */
/* $31 = ra: Return address */
lw ra, REG_RA(k1)
lw ra, REG_RA(k1)
/* Finally, restore CP status and the EPC */
/* Finally, restore CP status and the EPC */
lw k0, REG_STATUS(k1)
lw k1, REG_EPC(k1)
mtc0 k0, MIPS32_CP0_STATUS
ehb
mtc0 k1, MIPS32_CP0_EPC
eret
nop
.endm
lw k0, REG_STATUS(k1)
lw k1, REG_EPC(k1)
mtc0 k0, MIPS32_CP0_STATUS
ehb
mtc0 k1, MIPS32_CP0_EPC
eret
nop
.endm
/********************************************************************************************
/****************************************************************************
* Name: USE_INTSTACK
*
* Description:
@ -357,52 +366,54 @@
* All interrupts should still be disabled.
*
* At completion:
* If the nesting level is 0, then (1) the user stack pointer is saved at the base of the
* interrupt stack and sp points to the interrupt stack.
* If the nesting level is 0, then (1) the user stack pointer is saved
* at the base of the interrupt stack and sp points to the interrupt stack.
* The values of tmp1, tmp2, tmp3, and sp have been altered
*
********************************************************************************************/
****************************************************************************/
.macro USE_INTSTACK, tmp1, tmp2, tmp3, tmp4
.macro USE_INTSTACK, tmp1, tmp2, tmp3, tmp4
#if CONFIG_ARCH_INTERRUPTSTACK > 3
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
/* Check the nesting level. If there are no nested interrupts, then we can
* claim the interrupt stack.
*/
/* Check the nesting level. If there are no nested interrupts, then we can
* claim the interrupt stack.
*/
la \tmp1, g_nestlevel
lw \tmp2, (\tmp1)
bne 1f
nop
la \tmp1, g_nestlevel
lw \tmp2, (\tmp1)
bne 1f
nop
#endif
/* Use the interrupt stack, pushing the user stack pointer onto the interrupt
* stack first.
*/
/* Use the interrupt stack, pushing the user stack pointer onto the
* interrupt stack first.
*/
la \tmp3, g_intstackbase
lw \tmp4, (\tmp3)
sw sp, (\tmp4)
move sp, \tmp4
la \tmp3, g_intstackbase
lw \tmp4, (\tmp3)
sw sp, (\tmp4)
move sp, \tmp4
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
1:
/* Increment the interrupt nesting level */
addiu \tmp2, \tmp2, 1
sw \tmp2, 0(\tmp1)
/* Increment the interrupt nesting level */
addiu \tmp2, \tmp2, 1
sw \tmp2, 0(\tmp1)
#endif
#endif
.endm
.endm
/********************************************************************************************
/****************************************************************************
* Name: RESTORE_STACK
*
* Description:
* Restore the user stack. Not really.. actually only decrements the nesting level. We
* always get the new stack pointer for the register save array.
* Restore the user stack. Not really.. actually only decrements the
* nesting level. We always get the new stack pointer for the register
* save array.
*
* On Entry:
* tmp1 and tmp2 are registers that can be used temporarily.
@ -412,23 +423,23 @@
* Current nesting level is decremented
* The values of tmp1 and tmp2 have been altered
*
********************************************************************************************/
****************************************************************************/
.macro RESTORE_STACK, tmp1, tmp2
.macro RESTORE_STACK, tmp1, tmp2
#if CONFIG_ARCH_INTERRUPTSTACK > 3
#ifdef CONFIG_PIC32MX_NESTED_INTERRUPTS
/* Decrement the nesting level */
/* Decrement the nesting level */
la \tmp1, g_nestlevel
lw \tmp2, (\tmp1)
addiu \tmp2, \tmp2, -1
sw \tmp2, 0(\tmp1)
la \tmp1, g_nestlevel
lw \tmp2, (\tmp1)
addiu \tmp2, \tmp2, -1
sw \tmp2, 0(\tmp1)
#endif
#endif
.endm
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_EXCPTMACROS_H */

37
arch/mips/src/pic32mx/pic32mx_adc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ADC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_ADC_CON1_OFFSET 0x0000 /* ADC control register 1 */
#define PIC32MX_ADC_CON1CLR_OFFSET 0x0004 /* ADC control clear register 1 */
@ -78,7 +78,7 @@
#define PIC32MX_ADC_BUF14_OFFSET 0x0150 /* ADC result word 14 */
#define PIC32MX_ADC_BUF15_OFFSET 0x0160 /* ADC result word 15 */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_ADC_CON1 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1_OFFSET)
#define PIC32MX_ADC_CON1CLR (PIC32MX_ADC_K1BASE+PIC32MX_ADC_CON1CLR_OFFSET)
@ -123,7 +123,7 @@
#define PIC32MX_ADC_BUF14 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF14_OFFSET)
#define PIC32MX_ADC_BUF15 (PIC32MX_ADC_K1BASE+PIC32MX_ADC_BUF15_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* ADC control register 1 */
@ -137,6 +137,7 @@
# define ADC_CON1_SSRC_INT0 (1 << ADC_CON1_SSRC_SHIFT) /* INT0 transition starts */
# define ADC_CON1_SSRC_TIMER3 (2 << ADC_CON1_SSRC_SHIFT) /* Timer3 match starts */
# define ADC_CON1_SSRC_COUNT (7 << ADC_CON1_SSRC_SHIFT) /* Internal counter starts */
#define ADC_CON1_FORM_SHIFT (8) /* Bits 8-10: Data output format */
#define ADC_CON1_FORM_MASK (7 << ADC_CON1_FORM_SHIFT)
# define ADC_CON1_FORM_UINT16 (0 << ADC_CON1_FORM_SHIFT) /* Integer 16-bit */
@ -147,6 +148,7 @@
# define ADC_CON1_FORM_SINT32 (5 << ADC_CON1_FORM_SHIFT) /* Signed integer 32-bit */
# define ADC_CON1_FORM_FRAC32 (6 << ADC_CON1_FORM_SHIFT) /* Fractional 32-bit */
# define ADC_CON1_FORM_SFRAC32 (7 << ADC_CON1_FORM_SHIFT) /* Signed fractional 32-bit */
#define ADC_CON1_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define ADC_CON1_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define ADC_CON1_ON (1 << 15) /* Bit 14: ADC operating mode */
@ -158,6 +160,7 @@
#define ADC_CON2_SMPI_SHIFT (2) /* Bits 2-5: Sample/sequences per interrupt */
#define ADC_CON2_SMPI_MASK (15 << ADC_CON2_SMPI_SHIFT)
# define ADC_CON2_SMPI(n) ((n-1) << ADC_CON2_SMPI_SHIFT) /* Interrupt after nth conversion */
#define ADC_CON2_BUFS (1 << 7) /* Bit 7: Buffer fill status */
#define ADC_CON2_CSCNA (1 << 10) /* Bit 10: Scan input selections */
#define ADC_CON2_OFFCAL (1 << 12) /* Bit 12: Input offset calibration mode select */
@ -173,9 +176,11 @@
#define ADC_CON3_ADCS_SHIFT (0) /* Bits 0-7: ADC conversion clock select */
#define ADC_CON3_ADCS_MASK (0xff << ADC_CON3_ADCS_SHIFT)
# define ADC_CON3_ADCS(n) ((((n)>>1)-1) << ADC_CON3_ADCS_SHIFT) /* n*Tpb = Tad, n=2,4,..,512 */
#define ADC_CON3_SAMC_SHIFT (8) /* Bits 8-12: Auto-sample time bits */
#define ADC_CON3_SAMC_MASK (31 << ADC_CON3_SAMC_SHIFT)
# define ADC_CON3_SAMC(n) ((n) << ADC_CON3_SAMC_SHIFT) /* Tad = n, n=1..15 */
#define ADC_CON3_ADRC (1 << 15) /* Bit 15: ADC conversion clock source */
/* ADC input pin selection register */
@ -183,10 +188,12 @@
#define ADC_CHS_CH0SA_SHIFT (16) /* Bits 16-19: MUX A positive input select */
#define ADC_CHS_CH0SA_MASK (15 << ADC_CHS_CH0SA_SHIFT)
# define ADC_CHS_CH0SA(n) ((n) << ADC_CHS_CH0SA_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
#define ADC_CHS_CH0NA (1 << 23) /* Bit 23: MUX A negative input select */
#define ADC_CHS_CH0SB_SHIFT (24) /* Bits 24-27: MUX B positive input select */
#define ADC_CHS_CH0SB_MASK (15 << ADC_CHS_CH0SB_SHIFT)
# define ADC_CHS_CH0SB(n) ((n) << ADC_CHS_CH0SB_SHIFT) /* Channel 0 positive input ANn, n=0..15 */
#define ADC_CHS_CH0NB (1 << 31) /* Bit 31: MUX B negative input select */
/* ADC sequentially scanned input register */
@ -199,19 +206,19 @@
/* ADC result word 0-15 -- 32-bits of ADC result data */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

31
arch/mips/src/pic32mx/pic32mx_bmx.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_bmx.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */
#define PIC32MX_BMX_CONCLR_OFFSET 0x0004 /* Configuration Clear Register */
@ -59,7 +59,7 @@
#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */
#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET)
#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET)
@ -85,13 +85,14 @@
#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET)
#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET)
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Configuration Register */
#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */
#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT)
# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */
#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */
#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */
#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */
@ -122,19 +123,19 @@
/* Boot Flash Size Register -- 32-bit size value */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

34
arch/mips/src/pic32mx/pic32mx_che.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_che.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CHE_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_CHE_CON_OFFSET 0x0000 /* Pre-fetch cache control register */
#define PIC32MX_CHE_CONCLR_OFFSET 0x0004 /* Pre-fetch cache control clear register */
@ -59,7 +60,7 @@
#define PIC32MX_CHE_MIS_OFFSET 0x00a0 /* Cache miss statistics register */
#define PIC32MX_CHE_PFABT_OFFSET 0x00c0 /* Pre-fetch cache abort statistics register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_CHE_CON (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CON_OFFSET)
#define PIC32MX_CHE_CONCLR (PIC32MX_CHE_K1BASE+PIC32MX_CHE_CONCLR_OFFSET)
@ -86,25 +87,28 @@
#define PIC32MX_CHE_MIS (PIC32MX_CHE_K1BASE+PIC32MX_CHE_MIS_OFFSET)
#define PIC32MX_CHE_PFABT (PIC32MX_CHE_K1BASE+PIC32MX_CHE_PFABT_OFFSET)
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Pre-fetch cache control register */
#define CHE_CON_PFMWS_SHIFT (0) /* Bits 0-2: PFM access time (SYSCLK wait states) */
#define CHE_CON_PFMWS_MASK (7 << CHE_CON_PFMWS_SHIFT)
# define CHE_CON_PFMWS(n) ((n) << CHE_CON_PFMWS_SHIFT) /* n wait states, n=0-7 */
#define CHE_CON_PREFEN_SHIFT (4) /* Bits 4-5: Predictive pre-fetch cache enable */
#define CHE_CON_PREFEN_MASK (3 << CHE_CON_PREFEN_SHIFT)
# define CHE_CON_PREFEN_DISABLE (0 << CHE_CON_PREFEN_SHIFT) /* Disable predictive pre-fetch cache */
# define CHE_CON_PREFEN_CACHE (1 << CHE_CON_PREFEN_SHIFT) /* Enable for cacheable regions only */
# define CHE_CON_PREFEN_NONCACHE (2 << CHE_CON_PREFEN_SHIFT) /* Enable for non-cacheable regions only */
# define CHE_CON_PREFEN_ALL (3 << CHE_CON_PREFEN_SHIFT) /* Enable for both regions */
#define CHE_CON_DCSZ_SHIFT (8) /* Bits 8-9: Data cache size (lines) */
#define CHE_CON_DCSZ_MASK (3 << CHE_CON_DCSZ_SHIFT)
# define CHE_CON_DCSZ_DISABLE (0 << CHE_CON_DCSZ_SHIFT) /* Disable data caching */
# define CHE_CON_DCSZ_1LINE (1 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 1 line */
# define CHE_CON_DCSZ_2LINES (2 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 2 lines */
# define CHE_CON_DCSZ_4LINES (3 << CHE_CON_DCSZ_SHIFT) /* Enable with size of 4 lines */
#define CHE_CON_CHECOH (1 << 16) /* Bit 16: Cache coherency setting */
/* Pre-fetch cache access register */
@ -139,19 +143,19 @@
/* Pre-fetch cache abort statistics register -- 32 bit counter value */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

32
arch/mips/src/pic32mx/pic32mx_cm.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_cm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,11 +32,11 @@
#if CHIP_NCM > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_CM_CON_OFFSET 0x0000 /* Comparator control register */
#define PIC32MX_CM_CONCLR_OFFSET 0x0004 /* Comparator control clear register */
@ -47,7 +47,7 @@
#define PIC32MX_CM_STATSET_OFFSET 0x0068 /* Comparator status set register */
#define PIC32MX_CM_STATINV_OFFSET 0x006c /* Comparator status invert register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_CM1_CON (PIC32MX_CM1_K1BASE+PIC32MX_CM_CON_OFFSET)
#define PIC32MX_CM1_CONCLR (PIC32MX_CM1_K1BASE+PIC32MX_CM_CONCLR_OFFSET)
@ -66,7 +66,7 @@
#define PIC32MX_CM_STATSET (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATSET_OFFSET)
#define PIC32MX_CM_STATINV (PIC32MX_CM1_K1BASE+PIC32MX_CM_STATINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Comparator control register */
@ -76,6 +76,7 @@
# define CM_CON_CCH_CXINP (1 << CM_CON_CCH_SHIFT) /* Inverting input connected to CxIN+ */
# define CM_CON_CCH_CYINP (2 << CM_CON_CCH_SHIFT) /* Inverting input connected to CyIN+ */
# define CM_CON_CCH_IVREF (3 << CM_CON_CCH_SHIFT) /* Inverting input connected to IVREF */
#define CM_CON_CREF (1 << 4) /* Bit 4: Comparator positive input configure */
#define CM_CON_EVPOL_SHIFT (6) /* Bits 6-7: Interrupt event polarity select */
#define CM_CON_EVPOL_MASK (3 << CM_CON_EVPOL_SHIFT)
@ -83,6 +84,7 @@
# define CM_CON_EVPOL_RISING (1 << CM_CON_EVPOL_SHIFT) /* Interrupt on low-to-high transition */
# define CM_CON_EVPOL_FALLING (2 << CM_CON_EVPOL_SHIFT) /* Interrupt on high-to-low transition */
# define CM_CON_EVPOL_BOTH (3 << CM_CON_EVPOL_SHIFT) /* Interrupt on a both transitions */
#define CM_CON_COUT (1 << 8) /* Bit 8: Comparator output */
#define CM_CON_CPOL (1 << 13) /* Bit 13: Comparator output inversion */
#define CM_CON_COE (1 << 14) /* Bit 14: Comparator output enable */
@ -95,19 +97,19 @@
#define CM_STAT_SIDL (1 << 13) /* Bit 13: Stop in idle control */
#define CM_STAT_FRZ (1 << 14) /* Bit 14: Freeze control */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

31
arch/mips/src/pic32mx/pic32mx_cvr.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_cvr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,39 +16,39 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_CVR_CON_OFFSET 0x0000 /* Comparator voltage reference control register */
#define PIC32MX_CVR_CONCLR_OFFSET 0x0004 /* Comparator voltage reference control clear register */
#define PIC32MX_CVR_CONSET_OFFSET 0x0008 /* Comparator voltage reference control set register */
#define PIC32MX_CVR_CONINV_OFFSET 0x000c /* Comparator voltage reference control invert register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_CVR_CON (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CON_OFFSET)
#define PIC32MX_CVR_CONCLR (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONCLR_OFFSET)
#define PIC32MX_CVR_CONSET (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONSET_OFFSET)
#define PIC32MX_CVR_CONINV (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Comparator voltage reference control register */
@ -65,23 +65,24 @@
# define CVR_CON_BGSEL_0p6V (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
# define CVR_CON_BGSEL_0p2V (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
# define CVR_CON_BGSEL_VREF (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
# define CVR_CON_VREFSEL (1 << 10) /* Bit 10: Voltage reference select */
#endif
#define CVR_CON_ON (1 << 15) /* Bit 15: Comparator voltage reference on */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

31
arch/mips/src/pic32mx/pic32mx_ddp.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_ddp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,52 +16,53 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DDP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_DDP_CON_OFFSET 0x0000 /* Control Register for the Diagnostic Module */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_DDP_CON (PIC32MX_DDP_K1BASE+PIC32MX_DDP_CON_OFFSET)
/* See also the ICESEL, DEBUG, and DEBUG0 in the DEVCFG0 register */
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Control Register for the Diagnostic Module */
#define DDP_CON_TROEN (1 << 2) /* Bit 2: Trace output enable */
#define DDP_CON_JTAGEN (1 << 3) /* Bit 3: JTAG port enable */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

10
arch/mips/src/pic32mx/pic32mx_devcfg.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_DEVCFG3_OFFSET 0x0000 /* Device configuration word 3 */
@ -135,6 +136,7 @@
# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* Secondary oscillator */
# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* Low power RC oscillator */
# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator with FRCDIV */
#define DEVCFG1_FSOSCEN (1 << 5) /* Bit 5: Secondary oscillator (sosc) enable bit */
#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal external switch over */
#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary oscillator (posc) configuration */
@ -143,6 +145,7 @@
# define DEVCFG1_POSCMOD_XT (1 << DEVCFG1_POSCMOD_SHIFT) /* XT mode */
# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS mode */
# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* Primary Oscillator disabled */
#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO (clock-out) enable configuration */
#define DEVCFG1_FPBDIV_SHIFT (12) /* Bits 12-13: Peripheral bus clock divisor default value */
#define DEVCFG1_FPBDIV_MASK (3 << DEVCFG1_FPBDIV_SHIFT)
@ -150,11 +153,13 @@
# define DEVCFG1_FPBDIV_DIV2 (1 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/2 */
# define DEVCFG1_FPBDIV_DIV4 (2 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/4 */
# define DEVCFG1_FPBDIV_DIV8 (3 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK /8 */
#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock switching and monitor selection configuration */
#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT)
# define DEVCFG1_FCKSM_BOTH (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are enabled */
# define DEVCFG1_FCKSM_CSONLY (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching is enabled, FSCM is disabled */
# define DEVCFG1_FCKSM_NONE (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are disabled */
#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: WDT postscaler select */
#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT)
# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */
@ -178,6 +183,7 @@
# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: WDT enable */
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
@ -188,6 +194,7 @@
# define DEVCFG1_FWDTWINSZ_37p5 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* 37.5% */
# define DEVCFG1_FWDTWINSZ_50 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* 50% */
# define DEVCFG1_FWDTWINSZ_75 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* 75% */
# define DEVCFG1_UNUSED 0xfc200858 /* Bits 3-4, 6, 11, 21, 26-31 */
#else
# define DEVCFG1_UNUSED 0xff600858 /* Bits 3-4, 6, 11, 21-22, 24-31 */
@ -209,10 +216,12 @@
# define DEVCFG0_ICESEL_CHAN3 (1 << DEVCFG0_ICESEL_SHIFT) /* PGEC3/PGED3 pair is used */
# define DEVCFG0_ICESEL_CHAN2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */
# define DEVCFG0_ICESEL_CHAN1 (3 << DEVCFG0_ICESEL_SHIFT) /* PGEC1/PGED1 pair is used */
# define DEVCFG0_PWP_SHIFT (10) /* Bits 10-15: Program flash write-protect */
# define DEVCFG0_PWP_MASK (0x3ff << DEVCFG0_PWP_SHIFT)
# define DEVCFG0_PWP_DISABLE (0x3ff << DEVCFG0_PWP_SHIFT)
# define DEVCFG0_PWP(code) ((code) << DEVCFG0_PWP_SHIFT) /* See PWP_CODE above */
# define DEVCFG0_BWP (1 << 24) /* Bit 24: Boot flash write-protect */
# define DEVCFG0_CP (1 << 28) /* Bit 28: Code-protect */
# define DEVCFG0_SIGN (1 << 31) /* Bit 31: Signature */
@ -230,6 +239,7 @@
# define DEVCFG0_PWP_MASK (0xff << DEVCFG0_PWP_SHIFT)
# define DEVCFG0_PWP_DISABLE (0xff << DEVCFG0_PWP_SHIFT)
# define DEVCFG0_PWP(code) ((code) << DEVCFG0_PWP_SHIFT) /* See PWP_CODE above */
# define DEVCFG0_BWP (1 << 24) /* Bit 24: Boot flash write-protect */
# define DEVCFG0_CP (1 << 28) /* Bit 28: Code-protect */
# define DEVCFG0_SIGN (1 << 31) /* Bit 31: Signature */

73
arch/mips/src/pic32mx/pic32mx_dma.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DMA_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,10 +32,12 @@
#if CHIP_NDMACH > 0
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
/* Global DMA Registers */
#define PIC32MX_DMA_CON_OFFSET 0x0000 /* DMA Controller Control Register */
@ -99,7 +101,8 @@
#define PIC32MX_DMACH_DATSET_OFFSET 0x00b8 /* DMA Channel Pattern Data Set Register */
#define PIC32MX_DMACH_DATINV_OFFSET 0x00bc /* DMA Channel Pattern Data Invert Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
/* Global DMA Registers */
#define PIC32MX_DMA_CON (PIC32MX_DMA_K1BASE+PIC32MX_DMA_CON_OFFSET)
@ -498,8 +501,10 @@
# define PIC32MX_DMACH7_DATINV (PIC32MX_DMACH7_K1BASE+PIC32MX_DMACH_DATINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Global DMA Registers */
/* DMA Controller Control Register */
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
@ -580,6 +585,7 @@
/* DMA CRCXOR Enable Register -- 16 or 32-bits of data */
/* Per-Channel DMA Registers */
/* DMA Channel Control Register */
#define DMACH_CON_CHPRI_SHIFT (0) /* Bits 0-1: Channel priority */
@ -607,6 +613,7 @@
#define DMACH_ECON_CHSIRQ_SHIFT (8) /* Bits 8-15: Channel Transfer Start IRQ */
#define DMACH_ECON_CHSIRQ_MASK (0xff << DMACH_ECON_CHSIRQ_SHIFT)
# define DMACH_ECON_CHSIRQ(n) ((n) << DMACH_ECON_CHSIRQ_SHIFT) /* Interrupt n will initiate a DMA transfer */
#define DMACH_ECON_CHAIRQ_SHIFT (16) /* Bits 16-23: Channel transfer abort irq */
#define DMACH_ECON_CHAIRQ_MASK (0xff << DMACH_ECON_CHAIRQ_SHIFT)
# define DMACH_ECON_CHAIRQ(n) ((n) << DMACH_ECON_CHAIRQ_SHIFT) /* Interrupt n will abort any transfers in progress and set CHAIF */
@ -630,39 +637,57 @@
#define DMACH_INT_CHSHIE (1 << 22) /* Bit 22: Channel source half empty interrupt enable */
#define DMACH_INT_CHSDIE (1 << 23) /* Bit 23: Channel source done interrupt enable */
/* DMA Channel Source Start Address Register -- This register contains a 32-bit address value */
/* DMA Channel Source Start Address Register --
* This register contains a 32-bit address value
*/
/* DMA Channel Destination Start Address Register -- This register contains a 32-bit address value */
/* DMA Channel Destination Start Address Register --
* This register contains a 32-bit address value
*/
/* DMA Channel Source Size Register -- 8 or 16 bits of byte size data */
/* DMA Channel Source Size Register --
* 8 or 16 bits of byte size data
*/
/* DMA Channel Destination Size Register -- 8 or 16 bits of byte size data */
/* DMA Channel Destination Size Register --
* 8 or 16 bits of byte size data
*/
/* DMA Channel Source Pointer Register -- 8 or 16 bits of byte index data */
/* DMA Channel Source Pointer Register --
* 8 or 16 bits of byte index data
*/
/* DMA Channel Destination Pointer Register -- 8 or 16 bits of byte index data */
/* DMA Channel Destination Pointer Register --
* 8 or 16 bits of byte index data
*/
/* DMA Channel Cell-Size Register -- 8 or 16 bits of byte transferred data */
/* DMA Channel Cell-Size Register --
* 8 or 16 bits of byte transferred data
*/
/* DMA Channel Cell Pointer Register -- 8 or 16 bits of byte transferred data */
/* DMA Channel Cell Pointer Register --
* 8 or 16 bits of byte transferred data
*/
/* DMA Channel Pattern Data Register -- 8-bits of pattern data */
/* DMA Channel Pattern Data Register --
* 8-bits of pattern data
*/
#define DMACH_DAT_MASK 0xff
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

88
arch/mips/src/pic32mx/pic32mx_ethernet.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_ethernet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ETHERNET_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_ETHERNET_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
/* Controller and DMA Engine Configuration/Status Registers */
@ -208,7 +209,7 @@
#define PIC32MX_EMAC1_MINDSET_OFFSET 0x02d8
#define PIC32MX_EMAC1_MINDINV_OFFSET 0x02dc
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
/* Controller and DMA Engine Configuration/Status Registers */
@ -381,9 +382,10 @@
#define PIC32MX_EMAC1_MINDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDSET_OFFSET)
#define PIC32MX_EMAC1_MINDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDINV_OFFSET)
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Controller and DMA Engine Configuration/Status Registers */
/* Ethernet Controller Control 1 Register */
#define ETH_CON1_BUFCDEC (1 << 0) /* Bit 0: : Descriptor Buffer Count Decrement bit */
@ -401,16 +403,24 @@
#define ETH_CON1_PTV_MASK (0xffff << ETH_CON1_PTV_SHIFT)
/* Ethernet Controller Control 2 Register */
/* Bits 0-3: Reserved */
#define ETH_CON2_RXBUFSZ_SHIFT (4) /* Bits 4-10: RX Data Buffer Size for All RX Descriptors */
#define ETH_CON2_RXBUFSZ_MASK (0x7f << ETH_CON2_RXBUFSZ_SHIFT)
# define ETH_CON2_RXBUFSZ(n) (((n) >> 4) << ETH_CON2_RXBUFSZ_SHIFT) /* n=16, 32, 48, ... 2032 */
/* Bits 11-31: Reserved */
/* Ethernet Controller TX Packet Descriptor Start Address Register (32-bit address) */
/* Ethernet Controller RX Packet Descriptor Start Address Register (32-bit address) */
/* Ethernet Controller TX Packet Descriptor Start Address Register
* (32-bit address)
*/
/* Ethernet Controller RX Packet Descriptor Start Address Register
* (32-bit address)
*/
/* Ethernet Controller Interrupt Enable Register */
/* Ethernet Controller Interrupt Request Register */
#define ETH_INT_RXOVFLW (1 << 0) /* Bit 0: Receive FIFO overflow interrupt */
@ -441,6 +451,7 @@
/* Bits 24-31: Reserved */
/* RX Filtering Configuration Registers */
/* Ethernet Controller Receive Filter Configuration Register */
#define ETH_RXFC_BCEN (1 << 0) /* Bit 0: Broadcast filter enable */
@ -456,18 +467,30 @@
# define ETH_RXFC_PMMODE_DISABLED (0 << ETH_RXFC_PMMODE_SHIFT) /* Pattern match is always unsuccessful */
# define ETH_RXFC_PMMODE_PMCKSUM (1 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches */
# define ETH_RXFC_PMMODE_DASTA (2 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==STA */
/* #define ETH_RXFC_PMMODE_DASTA (3 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==STA */
/* #define ETH_RXFC_PMMODE_DASTA (3 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==STA
*/
# define ETH_RXFC_PMMODE_DAUCAST (4 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==Unicast address */
/* #define ETH_RXFC_PMMODE_DAUCAST (5 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==Unicast address */
/* #define ETH_RXFC_PMMODE_DAUCAST (5 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==Unicast address
*/
# define ETH_RXFC_PMMODE_DABCAST (6 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==Broadcast address */
/* #define ETH_RXFC_PMMODE_DABCAST (7 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==Broadcast address */
/* #define ETH_RXFC_PMMODE_DABCAST (7 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==Broadcast address
*/
# define ETH_RXFC_PMMODE_HASH (8 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & Hash Table Filter match */
# define ETH_RXFC_PMMODE_MAGIC (9 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & Packet = Magic Packet */
#define ETH_RXFC_NOTPM (1 << 12) /* Bit 12: Pattern match inversion */
/* Bit 13: Reserved */
#define ETH_RXFC_MPEN (1 << 14) /* Bit 14: Magic packet enable */
#define ETH_RXFC_HTEN (1 << 15) /* Bit 15: Hash table filtering enable */
/* Bits 16-31: Reserved */
/* Ethernet Controller Hash Table 0 Register */
#define ETH_HT0_BYTE0_SHIFT (0) /* Bits 0-7: Hash table byte 0, HT[0-7] */
@ -524,6 +547,7 @@
#define ETH_PMO_MASK (0xffff)
/* Flow Control Configuring Register */
/* Ethernet Controller Receive Watermarks Register */
#define ETH_RXWM_RXEWM_SHIFT (0) /* Bits 0-7: Receive empty watermark bits */
@ -532,6 +556,7 @@
#define ETH_RXWM_RXFWM_MASK (0xff << ETH_RXWM_RXFWM_SHIFT)
/* Ethernet Statistics Registers */
/* Ethernet Controller Receive Overflow Statistics Register */
#define ETH_RXOVFLOW_MASK (0xffff)
@ -561,6 +586,7 @@
#define ETH_ALGNERR_MASK (0xffff)
/* MAC Configuration Registers */
/* Ethernet Controller MAC Configuration 1 Register */
#define EMAC1_CFG1_RXEN (1 << 0) /* Bit 0: MAC Receive enable */
@ -577,6 +603,7 @@
#define EMAC1_CFG1_SIMRST (1 << 14) /* Bit 14: Simulation reset */
#define EMAC1_CFG1_SOFTRST (1 << 15) /* Bit 15: Soft reset */
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Configuration 2 Register */
#define EMAC1_CFG2_FULLDPLX (1 << 0) /* Bit 0: Full duplex operation */
@ -594,11 +621,13 @@
#define EMAC1_CFG2_BPNOBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */
#define EMAC1_CFG2_EXCESSDFR (1 << 14) /* Bit 14: Excess defer */
/* Bits 15-31: Reserved */
/* Ethernet Controller MAC Back-to-Back Interpacket Gap Register */
#define EMAC1_IPGT_SHIFT (0) /* Bits 0-6 */
#define EMAC1_IPGT_MASK (0x7f << EMAC1_IPGT_SHIFT)
/* Bits 7-31: Reserved */
/* Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register */
#define EMAC1_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */
@ -607,6 +636,7 @@
#define EMAC1_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */
#define EMAC1_IPGR_GAP1_MASK (0x7f << EMAC1_IPGR_GAP2_SHIFT)
/* Bits 15-31: Reserved */
/* Ethernet Controller MAC Collision Window/Retry Limit Register */
#define EMAC1_CLRT_RETX_SHIFT (0) /* Bits 0-3: Retransmission maximum */
@ -615,23 +645,28 @@
#define EMAC1_CLRT_CWINDOW_SHIFT (8) /* Bits 8-13: Collision window */
#define EMAC1_CLRT_CWINDOW_MASK (0x3f << EMAC1_CLRT_CWINDOW_SHIFT)
/* Bits 14-31: Reserved */
/* Ethernet Controller MAC Maximum Frame Length Register */
#define EMAC1_MAXF_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MAXF_MASK (0xffff << EMAC1_MAXF_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC PHY Support Register */
/* Bits 0-7: Reserved */
#define EMAC1_SUPP_SPEEDRMII (1 << 8) /* Bit 8: RMII Speed0=10Bps 1=100Bps */
/* Bits 9-10: Reserved */
#define EMAC1_SUPP_RESETRMII (1 << 11) /* Bit 11: Reset RMII Logic */
/* Bits 12-31: Reserved */
/* Ethernet Controller MAC Test Register */
#define EMAC1_TEST_SHRTQNTA (1 << 0) /* Bit 0: Shortcut pause quanta */
#define EMAC1_TEST_TESTPAUSE (1 << 1) /* Bit 1: Test pause */
#define EMAC1_TEST_TESTBP (1 << 2) /* Bit 2: Test packpressure */
/* Bits 3-31: Reserved */
/* Ethernet Controller MAC Station Address 0 Register */
#define EMAC1_SA0_STNADDR6_SHIFT (0) /* Bits 0-7: Station address 5th octet */
@ -639,6 +674,7 @@
#define EMAC1_SA0_STNADDR5_SHIFT (8) /* Bits 8-15: Station address 6th octet */
#define EMAC1_SA0_STNADDR5_MASK (0xff << EMAC1_SA0_STNADDR5_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Station Address 1 Register */
#define EMAC1_SA1_STNADDR4_SHIFT (0) /* Bits 0-7: Station address 4th octet */
@ -646,6 +682,7 @@
#define EMAC1_SA1_STNADDR3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */
#define EMAC1_SA1_STNADDR3_MASK (0xff << EMAC1_SA0_STNADDR3_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Station Address 2 Register */
#define EMAC1_SA2_STNADDR2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */
@ -653,6 +690,7 @@
#define EMAC1_SA2_STNADDR1_SHIFT (8) /* Bits 8-15: Station address 1st octet */
#define EMAC1_SA2_STNADDR1_MASK (0xff << EMAC1_SA2_STNADDR1_SHIFT)
/* Bits 16-31: Reserved */
/* MII Management Registers */
/* Ethernet Controller MAC MII Management Configuration Register */
@ -687,16 +725,19 @@
#define EMAC1_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */
#define EMAC1_MADR_PHYADDR_MASK (31 << EMAC1_MADR_PHYADDR_SHIFT)
/* Bits 13-31: Reserved */
/* Ethernet Controller MAC MII Management Write Data Register */
#define EMAC1_MWTD_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MWTD_MASK (0xffff << EMAC1_MWTD_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC MII Management Read Data Register */
#define EMAC1_MRDD_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MRDD_MASK (0xffff << EMAC1_MRDD_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC MII Management Indicators Register */
#define EMAC1_MIND_MIIMBUSY (1 << 0) /* Bit 0: Busy */
@ -705,7 +746,7 @@
#define EMAC1_MIND_LINKFAIL (1 << 3) /* Bit 3: MII link fail */
/* Bits 4-31: Reserved */
/* Descriptors Offsets **********************************************************************/
/* Descriptors Offsets ******************************************************/
/* Tx descriptor offsets. The NEXTED field is only present if NPV=1 */
@ -751,8 +792,10 @@
#define RXDESC_NEXTED 4 /* Next Ethernet Descriptor (ED) */
#define RXLINKED_SIZE 5 /* Size in 32-bit words of one linked Rx descriptor */
/* Descriptor Bit Definitions ***************************************************************/
/* Descriptor Bit Definitions ***********************************************/
/* Tx descriptor status bit definitions */
/* Bits 0-6: Reserved */
#define TXDESC_STATUS_EOWN (1 << 7) /* Bit 7: 1=Ethernet controller owns */
#define TXDESC_STATUS_SOWN (0) /* 0=Software owns */
@ -796,6 +839,7 @@
#define TXDESC_TSV2_TXUR (1 << 31) /* Bit 31: TSV31 Transmit Under-run */
/* Rx descriptor status bit definitions */
/* Bits 0-6: Reserved */
#define RXDESC_STATUS_EOWN (1 << 7) /* Bit 7: 1=Ethernet controller owns */
#define RXDESC_STATUS_SOWN (0) /* 0=Software owns */
@ -841,9 +885,9 @@
#define RXDESC_RSV2_VLAN (1 << 30) /* Bit 30: RSV30 Receive VLAN Type Detected */
/* Bit 31: RSV31 Reserved */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -891,13 +935,13 @@ struct pic32mx_rxdesc_s
uint32_t nexted; /* Next Ethernet Descriptor (ED) */
};
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

32
arch/mips/src/pic32mx/pic32mx_flash.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */
#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */
@ -46,7 +47,7 @@
#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */
#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET)
#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET)
@ -60,7 +61,7 @@
#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET)
#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET)
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Programming Control Register */
@ -71,6 +72,7 @@
# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */
# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */
# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */
#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */
#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */
#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */
@ -85,19 +87,19 @@
/* Source Data Address Register -- 32 Bits of data */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

31
arch/mips/src/pic32mx/pic32mx_i2c.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_i2c.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_I2C_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_I2C_CON_OFFSET 0x0000 /* I2C control register */
#define PIC32MX_I2C_CONCLR_OFFSET 0x0004 /* I2C control clear register */
@ -61,7 +62,7 @@
#define PIC32MX_I2C_TRNINV_OFFSET 0x005c /* I2C transmit invert register */
#define PIC32MX_I2C_RCV_OFFSET 0x0060 /* I2C receive buffer register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#if CHIP_NI2C > 0
# define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)
@ -203,7 +204,7 @@
# define PIC32MX_I2C5_RCV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* I2C control register */
@ -260,19 +261,19 @@
#define I2C_RCV_MASK 0xff /* 8-bit receive data */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

33
arch/mips/src/pic32mx/pic32mx_ic.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_ic.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,10 +32,11 @@
#if CHIP_NIC > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
@ -43,7 +44,7 @@
#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_IC_CON(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CON_OFFSET)
#define PIC32MX_IC_CONCLR(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONCLR_OFFSET)
@ -89,7 +90,7 @@
# define PIC32MX_IC5_BUF (PIC32MX_IC5_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Input Capture X Control Register */
@ -103,6 +104,7 @@
# define IC_CON_ICM_16th (5 << IC_CON_ICM_SHIFT) /* Every sixteenth rising edge */
# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICM_SHIFT) /* Specified edge first and every edge thereafter */
# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICM_SHIFT) /* Interrupt-only mode */
#define IC_CON_ICBNE (1 << 3) /* Bit 3: Input Capture Buffer Not Empty Status */
#define IC_CON_ICOV (1 << 4) /* Bit 4: Input Capture */
#define IC_CON_ICI_SHIFT (5) /* Bits 5-6: Interrupt Control */
@ -111,6 +113,7 @@
# define IC_CON_ICI_2ND (1 << IC_CON_ICI_SHIFT) /* Interrupt every 2nd capture event */
# define IC_CON_ICI_3RD (2 << IC_CON_ICI_SHIFT) /* Interrupt every 3rd capture event */
# define IC_CON_ICI_4TH (3 << IC_CON_ICI_SHIFT) /* Interrupt every 4th capture event */
#define IC_CON_ICTMR (1 << 7) /* Bit 7: Timer Select */
#define IC_CON_C32 (1 << 8) /* Bit 8: 32-bit Capture Select */
#define IC_CON_FEDGE (1 << 9) /* Bit 9: First Capture Edge Select */
@ -120,19 +123,19 @@
/* Input Capture X Buffer Register -- 32-bit capture value */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

2
arch/mips/src/pic32mx/pic32mx_int.h
View File

@ -33,6 +33,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_INT_INTCON_OFFSET 0x0000 /* Interrupt control register */
@ -296,6 +297,7 @@
# define INT_INTCON_TPC_PRIO5 (5 << INT_INTCON_TPC_SHIFT) /* Int group priority <=5 start TP timer */
# define INT_INTCON_TPC_PRIO6 (6 << INT_INTCON_TPC_SHIFT) /* Int group priority <=6 start TP timer */
# define INT_INTCON_TPC_PRIO7 (7 << INT_INTCON_TPC_SHIFT) /* Int group priority <=7 start TP timer */
#define INT_INTCON_MVEC (1 << 12) /* Bit 12: Multi vector configuration */
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \

31
arch/mips/src/pic32mx/pic32mx_ioport.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_ioport.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
/* Offsets relative to PIC32MX_IOPORTn_K1BASE */
@ -112,7 +113,7 @@
# define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */
#endif
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
# define PIC32MX_IOPORT_ANSEL(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ANSEL_OFFSET)
@ -369,7 +370,7 @@
# define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Analog select register */
@ -435,19 +436,19 @@
# endif
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

31
arch/mips/src/pic32mx/pic32mx_memorymap.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "mips32-memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Physical Memory Map **************************************************************/
****************************************************************************/
/* Physical Memory Map ******************************************************/
/* This top-level memory map is valid for the PIC32MX1xx/2xx families. */
@ -62,7 +63,7 @@
# error "Memory map unknown for this PIC32 chip"
#endif
/* Virtual Memory Map ***************************************************************/
/* Virtual Memory Map *******************************************************/
#define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
#define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
@ -75,7 +76,7 @@
#define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
#define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
/* Register Base Addresses **********************************************************/
/* Register Base Addresses **************************************************/
#if defined(CHIP_PIC32MX1) || defined(CHIP_PIC32MX2)
@ -489,19 +490,19 @@
# error "Memory map unknown for this PIC32 chip"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

32
arch/mips/src/pic32mx/pic32mx_oc.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_oc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,10 +32,11 @@
#if CHIP_NOC > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_OC_CON_OFFSET 0x0000 /* Output compare control register */
#define PIC32MX_OC_CONCLR_OFFSET 0x0004 /* Output compare control clear register */
@ -52,7 +53,7 @@
/* See also TIMER2 and TIMER3 registers */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_OC_CON(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CON_OFFSET)
#define PIC32MX_OC_CONCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONCLR_OFFSET)
@ -140,7 +141,7 @@
# define PIC32MX_OC5_RSINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Output compare control register */
@ -154,6 +155,7 @@
# define OC_CON_OCM_HIPULSE (5 << OC_CON_OCM_SHIFT) /* OCx high; output pulse on OCx */
# define OC_CON_OCM_PWM (6 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault disabled */
# define OC_CON_OCM_PWMFAULT (7 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault enabled */
#define OC_CON_OCTSEL (1 << 3) /* Bit 3: Output compare timer select */
#define OC_CON_OCFLT (1 << 4) /* Bit 4: PWM fault condition status */
#define OC_CON_OC32 (1 << 5) /* Bit 5: 32-bit compare more */
@ -165,19 +167,19 @@
/* Output compare secondary data register -- 32-bit data register */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

3
arch/mips/src/pic32mx/pic32mx_osc.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
@ -64,6 +65,7 @@
# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */
# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */
# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */
#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */
@ -74,6 +76,7 @@
# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */
# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */
# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */
#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */
#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT)
# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT)

39
arch/mips/src/pic32mx/pic32mx_pmp.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_pmp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_PMP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_PMP_CON_OFFSET 0x0000 /* Parallel Port Control Register */
#define PIC32MX_PMP_CONCLR_OFFSET 0x0004 /* Parallel Port Control Clear Register */
@ -63,7 +64,7 @@
#define PIC32MX_PMP_STATSET_OFFSET 0x0068 /* Parallel Port Status Set Register */
#define PIC32MX_PMP_STATINV_OFFSET 0x006c /* Parallel Port Status Invert Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_PMP_CON (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CON_OFFSET)
#define PIC32MX_PMP_CONCLR (PIC32MX_PMP_K1BASE+PIC32MX_PMP_CONCLR_OFFSET)
@ -94,7 +95,7 @@
#define PIC32MX_PMP_STATSET (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATSET_OFFSET)
#define PIC32MX_PMP_STATINV (PIC32MX_PMP_K1BASE+PIC32MX_PMP_STATINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Parallel Port Control Register */
@ -108,6 +109,7 @@
# define PMP_CON_CSF_ADDR1415 (0 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = address bits 15 and 14 */
# define PMP_CON_CSF_CS2ADDR14 (1 << PMP_CON_CSF_SHIFT) /* PMCS2 = Chip Select, PMCS1 = address bit 14 */
# define PMP_CON_CSF_CS12 (2 << PMP_CON_CSF_SHIFT) /* PMCS2/PMCS1 = Chip Select */
#define PMP_CON_PTRDEN (1 << 8) /* Bit 8: Read/write strobe port enable */
#define PMP_CON_PTWREN (1 << 9) /* Bit 9: Write enable strobe port enable */
#define PMP_CON_PMPTTL (1 << 10) /* Bit 10: PMP module TTL input buffer select */
@ -117,6 +119,7 @@
# define PMP_CON_ADRMUX_BYTE (1 << PMP_CON_ADRMUX_SHIFT) /* LS address are mux'ed on PMD 7:0 MS on PMA 15:8 */
# define PMP_CON_ADRMUX_MUX8 (2 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 7:0 */
# define PMP_CON_ADRMUX_MUX16 (3 << PMP_CON_ADRMUX_SHIFT) /* Address mux'ed on PMD 15:0 */
#define PMP_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define PMP_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define PMP_CON_ON (1 << 15) /* Bit 15: Parallel master port enable */
@ -127,21 +130,25 @@
#define PMP_MODE_WAITE_MASK (3 << PMP_MODE_WAITE_SHIFT)
# define PMP_MODE_WAITE_WR(n) ((n-1) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=1..4 */
# define PMP_MODE_WAITE_RD(n) ((n) << PMP_MODE_WAITE_SHIFT) /* Wait of n TPB n=0..3 */
#define PMP_MODE_WAITM_SHIFT (2) /* Bits 2-5: Data R/W strobe wait states */
#define PMP_MODE_WAITM_MASK (15 << PMP_MODE_WAITM_SHIFT)
# define PMP_MODE_WAITM(n) ((n-1) << PMP_MODE_WAITM_SHIFT) /* Wait of n TPB n=1..16 */
#define PMP_MODE_WAITB_SHIFT (6) /* Bits 6-7: Data setup to R/W strobe wait states */
#define PMP_MODE_WAITB_MASK (3 << PMP_MODE_WAITB_SHIFT)
# define PMP_MODE_WAITB_1TPB (0 << PMP_MODE_WAITB_SHIFT) /* Data wait of 1 TPB */
# define PMP_MODE_WAITB_2TPB (1 << PMP_MODE_WAITB_SHIFT) /* Data wait of 2 TPB */
# define PMP_MODE_WAITB_3TPB (2 << PMP_MODE_WAITB_SHIFT) /* Data wait of 3 TPB */
# define PMP_MODE_WAITB_4TPB (3 << PMP_MODE_WAITB_SHIFT) /* Data wait of 4 TPB */
#define PMP_MODE_MODE_SHIFT (8) /* Bits 8-9: Parallel port mode select */
#define PMP_MODE_MODE_MASK (3 << PMP_MODE_MODE_SHIFT)
# define PMP_MODE_MODE_LEGACY (0 << PMP_MODE_MODE_SHIFT) /* Legacy parallel slave port */
# define PMP_MODE_MODE_SLAVE (1 << PMP_MODE_MODE_SHIFT) /* Enhanced slave mode */
# define PMP_MODE_MODE_MODE2 (2 << PMP_MODE_MODE_SHIFT) /* Master mode 2 */
# define PMP_MODE_MODE_MODE1 (3 << PMP_MODE_MODE_SHIFT) /* Master mode 1 */
#define PMP_MODE_MODE16 (1 << 10) /* Bit 10: 1=16-bit mode */
#define PMP_MODE_MODE8 (0) /* 0=8-bit mode */
#define PMP_MODE_INCM_SHIFT (11) /* Bits 11-12: Increment Mode */
@ -150,11 +157,13 @@
# define PMP_MODE_INCM_INCR (1 << PMP_MODE_INCM_SHIFT) /* Incr addr on R/W cycle */
# define PMP_MODE_INCM_DECR (2 << PMP_MODE_INCM_SHIFT) /* Decr addr on R/Wcycle */
# define PMP_MODE_INCM_SLAVE (3 << PMP_MODE_INCM_SHIFT) /* Slave mode auto-increment */
#define PMP_MODE_IRQM_SHIFT (13) /* Bits 13-14: Interrupt request mode */
#define PMP_MODE_IRQM_MASK (3 << PMP_MODE_IRQM_SHIFT)
# define PMP_MODE_IRQM_NONE (0 << PMP_MODE_IRQM_SHIFT) /* No Interrupt generated */
# define PMP_MODE_IRQM_RW (1 << PMP_MODE_IRQM_SHIFT) /* Interrupt at end of R/W cycle */
# define PMP_MODE_IRQM_BUFFER (2 << PMP_MODE_IRQM_SHIFT) /* R/W buffer 3 or write PMA=11 */
#define PMP_MODE_BUSY (1 << 15) /* Bit 15: Busy (master mode only) */
/* Parallel Port Address Register */
@ -194,19 +203,19 @@
#define PMP_STAT_IBOV (1 << 14) /* Bit 14: Input buffer overflow status */
#define PMP_STAT_IBF (1 << 15) /* Bit 15: Input buffer full status */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

9
arch/mips/src/pic32mx/pic32mx_pps.h
View File

@ -34,7 +34,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
/* Peripheral pin select input registers */
#define PIC32MX_PPS_INT1R_OFFSET 0x0004
@ -98,6 +100,7 @@
#define PIC32MX_PPS_RPC9R_OFFSET 0x0090
/* Register Addresses *******************************************************/
/* Peripheral pin select input registers */
#define PIC32MX_PPS_INT1R (PIC32MX_INSEL_K1BASE+PIC32MX_PPS_INT1R_OFFSET)
@ -161,6 +164,7 @@
#define PIC32MX_PPS_RPC9R (PIC32MX_OUTSEL_K1BASE+PIC32MX_PPS_RPC9R_OFFSET)
/* Register Bit-Field Definitions *******************************************/
/* Peripheral pin select input registers */
#define PPS_INSEL_MASK 0x0000000f
@ -217,8 +221,9 @@
#define PPS_OUTSEL_SDO2 4
#define PPS_OUTSEL_OC2 5
//#define PPS_OUTSEL_SDO1 3
//#define PPS_OUTSEL_SDO2 4
/* #define PPS_OUTSEL_SDO1 3 */
/* #define PPS_OUTSEL_SDO2 4 */
#define PPS_OUTSEL_OC4 5
#define PPS_OUTSEL_OC5 6
#define PPS_OUTSEL_REFCLKO 7

31
arch/mips/src/pic32mx/pic32mx_reset.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_reset.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RESET_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_RESET_RCON_OFFSET 0x0000 /* Reset control register */
#define PIC32MX_RESET_RCONCLR_OFFSET 0x0004 /* RCON clear register */
@ -43,7 +44,7 @@
#define PIC32MX_RESET_RSWRSTSET_OFFSET 0x0018 /* RSWRST set register */
#define PIC32MX_RESET_RSWRSTINV_OFFSET 0x001c /* RSWRST invert register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_RESET_RCON (PIC32MX_RESET_K1BASE+PIC32MX_RCON_OFFSET)
#define PIC32MX_RESET_RCONCLR (PIC32MX_RESET_K1BASE+PIC32MX_RCONCLR_OFFSET)
@ -54,7 +55,7 @@
#define PIC32MX_RESET_RSWRSTSET (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTSET_OFFSET)
#define PIC32MX_RESET_RSWRSTINV (PIC32MX_RESET_K1BASE+PIC32MX_RSWRSTINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Reset control register */
@ -72,19 +73,19 @@
#define RESET_RSWRST_TRIGGER (1 << 0) /* Bit 0: Software reset trigger */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

32
arch/mips/src/pic32mx/pic32mx_rtcc.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_rtcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_RTCC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register Offsets *************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_RTCC_CON_OFFSET 0x0000 /* RTC Control Register */
#define PIC32MX_RTCC_CONCLR_OFFSET 0x0004 /* RTC Control Clear Register */
@ -59,7 +60,7 @@
#define PIC32MX_RTCC_ALRMDATESET_OFFSET 0x0058 /* Alarm Date Value Set Register */
#define PIC32MX_RTCC_ALRMDATEINV_OFFSET 0x005c /* Alarm Date Value Invert Register */
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_RTCC_CON (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CON_OFFSET)
#define PIC32MX_RTCC_CONCLR (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_CONCLR_OFFSET)
@ -86,11 +87,12 @@
#define PIC32MX_RTCC_ALRMDATESET (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATESET_OFFSET)
#define PIC32MX_RTCC_ALRMDATEINV (PIC32MX_RTCC_K1BASE+PIC32MX_RTCC_ALRMDATEINV_OFFSET)
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* RTC Control Register */
#define RTCC_CON_CAL_SHIFT (16) /* Bits 16-25: RTC drift calibration */
#define RTCC_CON_CAL_MASK (0x3ff << RTCC_CON_CAL_SHIFT) /* 10-bit 2's complement */
# define RTCC_CON_CAL_MAX (0x1ff << RTCC_CON_CAL_SHIFT)
# define RTCC_CON_CAL_CENTER (0x000 << RTCC_CON_CAL_SHIFT)
@ -174,19 +176,19 @@
#define RTCC_ALRMDATE_MONTH01_MASK (15 << RTCC_ALRMDATE_MONTH01_SHIFT)
#define RTCC_DATE_MONTH10 (1 << 20) /* Bit 20: BCD month, 10 digits */
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

4
arch/mips/src/pic32mx/pic32mx_spi.h
View File

@ -33,6 +33,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_SPI_CON_OFFSET 0x0000 /* SPI control register */
@ -127,6 +128,7 @@
# define SPI_CON_RTXISEL_NEMPTY (1 << SPI_CON_RTXISEL_SHIFT) /* Buffer not empty */
# define SPI_CON_RTXISEL_HALF (2 << SPI_CON_RTXISEL_SHIFT) /* Buffer half full or more */
# define SPI_CON_RTXISEL_FULL (3 << SPI_CON_RTXISEL_SHIFT) /* Buffer full */
# define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */
# define SPI_CON_STXISEL_MASK (3 << SPI_CON_STXISEL_SHIFT)
# define SPI_CON_STXISEL_DONE (0 << SPI_CON_STXISEL_SHIFT) /* Buffer empty (and data shifted out) */
@ -182,6 +184,7 @@
# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
# define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
# define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
#endif
@ -199,6 +202,7 @@
# define SPI2_CON2_AUDMOD_LJ (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
# define SPI2_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
# define SPI2_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
/* Bit 2: Reserved */
# define SPI2_CON2_AUDMONO (1 << 3) /* Bit 3: Transmit Audio Data Format */
/* Bits 5-6: Reserved */

33
arch/mips/src/pic32mx/pic32mx_timer.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,10 +32,11 @@
#if CHIP_NTIMERS > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_TIMER_CON_OFFSET 0x0000 /* Timer control register */
#define PIC32MX_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
@ -50,7 +51,7 @@
#define PIC32MX_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
#define PIC32MX_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_TIMER_CON(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CON_OFFSET)
#define PIC32MX_TIMER_CONCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONCLR_OFFSET)
@ -138,7 +139,7 @@
# define PIC32MX_TIMER5_PRINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Timer control register */
@ -155,12 +156,14 @@
# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
@ -176,19 +179,19 @@
#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

34
arch/mips/src/pic32mx/pic32mx_uart.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_UART_MODE_OFFSET 0x0000 /* UARTx mode register */
#define PIC32MX_UART_MODECLR_OFFSET 0x0004 /* UARTx mode clear register */
@ -50,7 +51,7 @@
#define PIC32MX_UART_BRGSET_OFFSET 0x0048 /* UARTx baud rate set register */
#define PIC32MX_UART_BRGINV_OFFSET 0x004c /* UARTx baud rate invert register */
/* Register Addresses ****************************************************************/
/* Register Addresses *******************************************************/
#if CHIP_NUARTS > 0
# define PIC32MX_UART1_MODE (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODE_OFFSET)
@ -154,7 +155,7 @@
# define PIC32MX_UART6_BRGINV (PIC32MX_UART6_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
/* Register Bit-Field Definitions ****************************************************/
/* Register Bit-Field Definitions *******************************************/
/* UARTx mode register */
@ -165,6 +166,7 @@
# define UART_MODE_PDSEL_8EVEN (1 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, even parity */
# define UART_MODE_PDSEL_8ODD (2 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, odd parity */
# define UART_MODE_PDSEL_9NONE (3 << UART_MODE_PDSEL_SHIFT) /* 9-bit data, no parity */
#define UART_MODE_BRGH (1 << 3) /* Bit 3: High baud rate enable */
#define UART_MODE_RXINV (1 << 4) /* Bit 4: Receive polarity inversion */
#define UART_MODE_ABAUD (1 << 5) /* Bit 5: Auto-baud enable */
@ -176,6 +178,7 @@
# define UART_MODE_UEN_ENR_CPORT (1 << UART_MODE_UEN_SHIFT) /* UxRTS=enabled; UxCTS=PORTx register */
# define UART_MODE_UEN_ENCR (2 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS=enabled */
# define UART_MODE_UEN_CPORT (3 << UART_MODE_UEN_SHIFT) /* UxCTS=PORTx register */
#define UART_MODE_RTSMD (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */
#define UART_MODE_IREN (1 << 12) /* Bit 12: IrDA encoder and decoder enable */
#define UART_MODE_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
@ -216,6 +219,7 @@
# define UART_STA_UTXISEL_TXBNF (0 << UART_STA_UTXISEL_SHIFT) /* TX buffer not full */
# define UART_STA_UTXISEL_DRAINED (1 << UART_STA_UTXISEL_SHIFT) /* All characters sent */
# define UART_STA_UTXISEL_TXBE (2 << UART_STA_UTXISEL_SHIFT) /* TX buffer empty */
#define UART_STA_ADDR_SHIFT (16) /* Bits:16-23: Automatic address mask */
#define UART_STA_ADDR_MASK (0xff << UART_STA_ADDR_SHIFT)
#define UART_STA_ADM_EN (1 << 24) /* Bit 24: Automatic address detect mode enable */
@ -232,19 +236,19 @@
#define UART_BRG_MASK 0xffff
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

38
arch/mips/src/pic32mx/pic32mx_usbotg.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mx/pic32mx_usbotg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_USBOTG_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_USBOTG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mx_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_USBOTG_IR_OFFSET 0x0040 /* USB OTG Interrupt Flags Register */
#define PIC32MX_USBOTG_IE_OFFSET 0x0050 /* USB OTG Interrupt Enable Register */
@ -73,7 +74,7 @@
#define PIC32MX_USB_EP14_OFFSET 0x03e0 /* USB Endpoint 14 Control Register */
#define PIC32MX_USB_EP15_OFFSET 0x03f0 /* USB Endpoint 15 Control Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MX_USBOTG_IR (PIC32MX_USB_K1BASE+PIC32MX_USBOTG_IR_OFFSET)
#define PIC32MX_USBOTG_IE (PIC32MX_USB_K1BASE+PIC32MX_USBOTG_IE_OFFSET)
@ -114,9 +115,10 @@
#define PIC32MX_USB_EP14 (PIC32MX_USB_K1BASE+PIC32MX_USB_EP14_OFFSET)
#define PIC32MX_USB_EP15 (PIC32MX_USB_K1BASE+PIC32MX_USB_EP15_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* USB OTG Interrupt Flags Register */
/* USB OTG Interrupt Enable Register */
#define USBOTG_INT_VBUSVD (1 << 0) /* Bit 0: A-Device VBUS Change Indicator */
@ -157,6 +159,7 @@
#define USB_PWRC_UACTPND (1 << 7) /* Bit 7: USB Activity Pending */
/* USB Pending Interrupt Register */
/* USB Interrupt Enable Register */
#define USB_INT_URST (1 << 0) /* Bit 0: USB Reset Interrupt (Device mode) */
@ -172,6 +175,7 @@
#define USB_INT_ALL 0xff
/* USB Pending Error Interrupt Register */
/* USB Interrupt Error Enable Register */
#define USB_EINT_PID (1 << 0) /* Bit 0: PID Check Failure Flag */
@ -234,6 +238,7 @@
# define USB_TOK_PID_OUT (1 << USB_TOK_PID_SHIFT) /* OUT (TX) token type transaction */
# define USB_TOK_PID_IN (9 << USB_TOK_PID_SHIFT) /* IN (RX) token type transaction */
# define USB_TOK_PID_SETUP (13 << USB_TOK_PID_SHIFT) /* SETUP (TX) token type transaction */
#define USB_TOK_EP_SHIFT (0) /* Bits 0-3: Token Command Endpoint Address */
#define USB_TOK_EP_MASK (15 << USB_TOK_EP_SHIFT)
@ -278,7 +283,8 @@
#define USB_EP_RETRYDIS (1 << 6) /* Bit 6: Retry Disable (Host mode and U1EP0 only) */
#define USB_EP_LSPD (1 << 7) /* Bit 7: Low-Speed Direct Connection Enable */
/* Buffer Descriptor Table (BDT) ****************************************************/
/* Buffer Descriptor Table (BDT) ********************************************/
/* Offset 0: On write (software->hardware) */
#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */
@ -308,9 +314,9 @@
#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */
#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -322,13 +328,13 @@ struct usbotg_bdtentry_s
uint8_t *addr; /* Buffer address */
};
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

2
arch/mips/src/pic32mx/pic32mx_wdt.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MX_WDT_CON_OFFSET 0x0000 /* Watchdog timer control register */
@ -70,6 +71,7 @@
# define WDT_CON_SWDTPS_262144 (18 << WDT_CON_SWDTPS_SHIFT) /* 1:262144 */
# define WDT_CON_SWDTPS_524288 (19 << WDT_CON_SWDTPS_SHIFT) /* 1:524288 */
# define WDT_CON_SWDTPS_1048576 (20 << WDT_CON_SWDTPS_SHIFT) /* 1:1048576 */
#define WDT_CON_ON (1 << 15 /* Bit 15: Watchdog timer enable */
/****************************************************************************

51
arch/mips/src/pic32mz/hardware/pic32mz_dma.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_DMA_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_DMA_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/pic32mz/chip.h>
@ -32,10 +32,11 @@
#if CHIP_NDMACH > 0
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* DMA Channel Offsets **********************************************************************/
****************************************************************************/
/* DMA Channel Offsets ******************************************************/
#define PIC32MZ_DMACHn_OFFSET(n) (0x0060 + 0xc0 *(n))
# define PIC32MZ_DMACH0_OFFSET 0x0060
@ -47,7 +48,8 @@
# define PIC32MZ_DMACH6_OFFSET 0x04f0
# define PIC32MZ_DMACH7_OFFSET 0x05b0
/* DMA Register Offsets *********************************************************************/
/* DMA Register Offsets *****************************************************/
/* Global DMA Registers (relative the DMA K1BASE) */
#define PIC32MZ_DMA_CON_OFFSET 0x0000 /* DMA Controller Control Register */
@ -126,7 +128,7 @@
#define PIC32MZ_DMACH_DATSET_OFFSET 0x00b8 /* DMA Channel Pattern Data Set Register */
#define PIC32MZ_DMACH_DATINV_OFFSET 0x00bc /* DMA Channel Pattern Data Invert Register */
/* DMA Channel Addresses ********************************************************************/
/* DMA Channel Addresses ****************************************************/
#define PIC32MZ_DMACHn_K1BASE(n) (PIC32MZ_DMA_K1BASE+PIC32MZ_DMACHn_OFFSET(n))
# define PIC32MZ_DMACH0_K1BASE (PIC32MZ_DMA_K1BASE+PIC32MZ_DMACH0_OFFSET)
@ -138,7 +140,8 @@
# define PIC32MZ_DMACH6_K1BASE (PIC32MZ_DMA_K1BASE+PIC32MZ_DMACH6_OFFSET)
# define PIC32MZ_DMACH7_K1BASE (PIC32MZ_DMA_K1BASE+PIC32MZ_DMACH7_OFFSET)
/* DMA Register Addresses *******************************************************************/
/* DMA Register Addresses ***************************************************/
/* Global DMA Registers */
#define PIC32MZ_DMA_CON (PIC32MZ_DMA_K1BASE+PIC32MZ_DMA_CON_OFFSET)
@ -633,8 +636,10 @@
# define PIC32MZ_DMACH7_DATINV (PIC32MZ_DMACH7_K1BASE+PIC32MZ_DMACH_DATINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Global DMA Registers */
/* DMA Controller Control Register */
#define DMA_CON_DMABUSY (1 << 11) /* Bit 15: DMA module busy */
@ -670,9 +675,11 @@
# define DMA_CRCCON_BYTO_SWAP16 (3 << DMA_CRCCON_BYTO_SHIFT) /* Endian byte swap on half-word boundaries */
/* DMA CRC Data Register -- 16 or 32-bits of data */
/* DMA CRCXOR Enable Register -- 16 or 32-bits of data */
/* Per-Channel DMA Registers */
/* DMA Channel Control Register */
#define DMACH_CON_CHPRI_SHIFT (0) /* Bits 0-1: Channel priority */
@ -728,8 +735,14 @@
#define DMACH_INT_EN_SHIFT (16) /* Bits 16-23: Channel Interrupt Enable events */
#define DMACH_INT_EN_MASK (0xff << DMACH_INT_EN_SHIFT)
/* DMA Channel Source Start Address Register -- This register contains a 32-bit address value */
/* DMA Channel Destination Start Address Register -- This register contains a 32-bit address value */
/* DMA Channel Source Start Address Register --
* This register contains a 32-bit address value
*/
/* DMA Channel Destination Start Address Register --
* This register contains a 32-bit address value
*/
/* DMA Channel Source Size Register -- 16 bits of byte size data */
#define DMACH_SSIZ_MASK 0x0000ffff
@ -758,19 +771,19 @@
#define DMACH_DAT_MASK 0x0000ffff
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Inline Functions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

88
arch/mips/src/pic32mz/hardware/pic32mz_ethernet.h
View File

@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_ethernet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_ETHERNET_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_ETHERNET_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/pic32mz/chip.h>
@ -32,10 +32,11 @@
#if CHIP_NETHERNET > 0
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
/* Controller and DMA Engine Configuration/Status Registers */
@ -241,7 +242,7 @@
#define PIC32MZ_EMAC1_MINDSET_OFFSET 0x02d8
#define PIC32MZ_EMAC1_MINDINV_OFFSET 0x02dc
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
/* Controller and DMA Engine Configuration/Status Registers */
@ -447,9 +448,10 @@
#define PIC32MZ_EMAC1_MINDSET (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MINDSET_OFFSET)
#define PIC32MZ_EMAC1_MINDINV (PIC32MZ_ETH_K1BASE+PIC32MZ_EMAC1_MINDINV_OFFSET)
/* Register Bit-Field Definitions *******************************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Controller and DMA Engine Configuration/Status Registers */
/* Ethernet Controller Control 1 Register */
#define ETH_CON1_BUFCDEC (1 << 0) /* Bit 0: : Descriptor Buffer Count Decrement bit */
@ -467,16 +469,24 @@
#define ETH_CON1_PTV_MASK (0xffff << ETH_CON1_PTV_SHIFT)
/* Ethernet Controller Control 2 Register */
/* Bits 0-3: Reserved */
#define ETH_CON2_RXBUFSZ_SHIFT (4) /* Bits 4-10: RX Data Buffer Size for All RX Descriptors */
#define ETH_CON2_RXBUFSZ_MASK (0x7f << ETH_CON2_RXBUFSZ_SHIFT)
# define ETH_CON2_RXBUFSZ(n) (((n) >> 4) << ETH_CON2_RXBUFSZ_SHIFT) /* n=16, 32, 48, ... 2032 */
/* Bits 11-31: Reserved */
/* Ethernet Controller TX Packet Descriptor Start Address Register (32-bit address) */
/* Ethernet Controller RX Packet Descriptor Start Address Register (32-bit address) */
/* Ethernet Controller TX Packet Descriptor Start Address Register
* (32-bit address)
*/
/* Ethernet Controller RX Packet Descriptor Start Address Register
* (32-bit address)
*/
/* Ethernet Controller Interrupt Enable Register */
/* Ethernet Controller Interrupt Request Register */
#define ETH_INT_RXOVFLW (1 << 0) /* Bit 0: Receive FIFO overflow interrupt */
@ -507,6 +517,7 @@
/* Bits 24-31: Reserved */
/* RX Filtering Configuration Registers */
/* Ethernet Controller Receive Filter Configuration Register */
#define ETH_RXFC_BCEN (1 << 0) /* Bit 0: Broadcast filter enable */
@ -522,18 +533,29 @@
# define ETH_RXFC_PMMODE_DISABLED (0 << ETH_RXFC_PMMODE_SHIFT) /* Pattern match is always unsuccessful */
# define ETH_RXFC_PMMODE_PMCKSUM (1 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches */
# define ETH_RXFC_PMMODE_DASTA (2 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==STA */
/* #define ETH_RXFC_PMMODE_DASTA (3 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==STA */
/* #define ETH_RXFC_PMMODE_DASTA (3 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==STA
*/
# define ETH_RXFC_PMMODE_DAUCAST (4 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==Unicast address */
/* #define ETH_RXFC_PMMODE_DAUCAST (5 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==Unicast address */
/* #define ETH_RXFC_PMMODE_DAUCAST (5 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==Unicast address
*/
# define ETH_RXFC_PMMODE_DABCAST (6 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & DA==Broadcast address */
/* #define ETH_RXFC_PMMODE_DABCAST (7 << ETH_RXFC_PMMODE_SHIFT) PM checksum matches & DA==Broadcast address */
/* #define ETH_RXFC_PMMODE_DABCAST (7 << ETH_RXFC_PMMODE_SHIFT)
* PM checksum matches & DA==Broadcast address
*/
# define ETH_RXFC_PMMODE_HASH (8 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & Hash Table Filter match */
# define ETH_RXFC_PMMODE_MAGIC (9 << ETH_RXFC_PMMODE_SHIFT) /* PM checksum matches & Packet = Magic Packet */
#define ETH_RXFC_NOTPM (1 << 12) /* Bit 12: Pattern match inversion */
/* Bit 13: Reserved */
#define ETH_RXFC_MPEN (1 << 14) /* Bit 14: Magic packet enable */
#define ETH_RXFC_HTEN (1 << 15) /* Bit 15: Hash table filtering enable */
/* Bits 16-31: Reserved */
/* Ethernet Controller Hash Table 0 Register */
#define ETH_HT0_BYTE0_SHIFT (0) /* Bits 0-7: Hash table byte 0, HT[0-7] */
@ -590,6 +612,7 @@
#define ETH_PMO_MASK (0xffff)
/* Flow Control Configuring Register */
/* Ethernet Controller Receive Watermarks Register */
#define ETH_RXWM_RXEWM_SHIFT (0) /* Bits 0-7: Receive empty watermark bits */
@ -598,6 +621,7 @@
#define ETH_RXWM_RXFWM_MASK (0xff << ETH_RXWM_RXFWM_SHIFT)
/* Ethernet Statistics Registers */
/* Ethernet Controller Receive Overflow Statistics Register */
#define ETH_RXOVFLOW_MASK (0xffff)
@ -627,6 +651,7 @@
#define ETH_ALGNERR_MASK (0xffff)
/* MAC Configuration Registers */
/* Ethernet Controller MAC Configuration 1 Register */
#define EMAC1_CFG1_RXEN (1 << 0) /* Bit 0: MAC Receive enable */
@ -643,6 +668,7 @@
#define EMAC1_CFG1_SIMRST (1 << 14) /* Bit 14: Simulation reset */
#define EMAC1_CFG1_SOFTRST (1 << 15) /* Bit 15: Soft reset */
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Configuration 2 Register */
#define EMAC1_CFG2_FULLDPLX (1 << 0) /* Bit 0: Full duplex operation */
@ -660,11 +686,13 @@
#define EMAC1_CFG2_BPNOBKOFF (1 << 13) /* Bit 13: Back pressure/no backoff */
#define EMAC1_CFG2_EXCESSDFR (1 << 14) /* Bit 14: Excess defer */
/* Bits 15-31: Reserved */
/* Ethernet Controller MAC Back-to-Back Interpacket Gap Register */
#define EMAC1_IPGT_SHIFT (0) /* Bits 0-6 */
#define EMAC1_IPGT_MASK (0x7f << EMAC1_IPGT_SHIFT)
/* Bits 7-31: Reserved */
/* Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register */
#define EMAC1_IPGR_GAP2_SHIFT (0) /* Bits 0-6: Gap part 2 */
@ -673,6 +701,7 @@
#define EMAC1_IPGR_GAP1_SHIFT (8) /* Bits 8-18: Gap part 1 */
#define EMAC1_IPGR_GAP1_MASK (0x7f << EMAC1_IPGR_GAP2_SHIFT)
/* Bits 15-31: Reserved */
/* Ethernet Controller MAC Collision Window/Retry Limit Register */
#define EMAC1_CLRT_RETX_SHIFT (0) /* Bits 0-3: Retransmission maximum */
@ -681,23 +710,28 @@
#define EMAC1_CLRT_CWINDOW_SHIFT (8) /* Bits 8-13: Collision window */
#define EMAC1_CLRT_CWINDOW_MASK (0x3f << EMAC1_CLRT_CWINDOW_SHIFT)
/* Bits 14-31: Reserved */
/* Ethernet Controller MAC Maximum Frame Length Register */
#define EMAC1_MAXF_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MAXF_MASK (0xffff << EMAC1_MAXF_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC PHY Support Register */
/* Bits 0-7: Reserved */
#define EMAC1_SUPP_SPEEDRMII (1 << 8) /* Bit 8: RMII Speed0=10Bps 1=100Bps */
/* Bits 9-10: Reserved */
#define EMAC1_SUPP_RESETRMII (1 << 11) /* Bit 11: Reset RMII Logic */
/* Bits 12-31: Reserved */
/* Ethernet Controller MAC Test Register */
#define EMAC1_TEST_SHRTQNTA (1 << 0) /* Bit 0: Shortcut pause quanta */
#define EMAC1_TEST_TESTPAUSE (1 << 1) /* Bit 1: Test pause */
#define EMAC1_TEST_TESTBP (1 << 2) /* Bit 2: Test packpressure */
/* Bits 3-31: Reserved */
/* Ethernet Controller MAC Station Address 0 Register */
#define EMAC1_SA0_STNADDR6_SHIFT (0) /* Bits 0-7: Station address 5th octet */
@ -705,6 +739,7 @@
#define EMAC1_SA0_STNADDR5_SHIFT (8) /* Bits 8-15: Station address 6th octet */
#define EMAC1_SA0_STNADDR5_MASK (0xff << EMAC1_SA0_STNADDR5_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Station Address 1 Register */
#define EMAC1_SA1_STNADDR4_SHIFT (0) /* Bits 0-7: Station address 4th octet */
@ -712,6 +747,7 @@
#define EMAC1_SA1_STNADDR3_SHIFT (8) /* Bits 8-15: Station address 3rd octet */
#define EMAC1_SA1_STNADDR3_MASK (0xff << EMAC1_SA0_STNADDR3_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC Station Address 2 Register */
#define EMAC1_SA2_STNADDR2_SHIFT (0) /* Bits 0-7: Station address 2nd octet */
@ -719,6 +755,7 @@
#define EMAC1_SA2_STNADDR1_SHIFT (8) /* Bits 8-15: Station address 1st octet */
#define EMAC1_SA2_STNADDR1_MASK (0xff << EMAC1_SA2_STNADDR1_SHIFT)
/* Bits 16-31: Reserved */
/* MII Management Registers */
/* Ethernet Controller MAC MII Management Configuration Register */
@ -737,6 +774,7 @@
# define EMAC1_MCFG_CLKSEL_DIV40 (8 << EMAC1_MCFG_CLKSEL_SHIFT) /* PBCLK5 divided by 40 */
# define EMAC1_MCFG_CLKSEL_DIV48 (9 << EMAC1_MCFG_CLKSEL_SHIFT) /* PBCLK5 divided by 48 */
# define EMAC1_MCFG_CLKSEL_DIV50 (10 << EMAC1_MCFG_CLKSEL_SHIFT) /* PBCLK5 divided by 50 */
/* Bits 6-14: Reserved */
#define EMAC1_MCFG_MGMTRST (1 << 15) /* Bit 15: Reset MII mgmt */
/* Bits 16-31: Reserved */
@ -756,16 +794,19 @@
#define EMAC1_MADR_PHYADDR_SHIFT (8) /* Bits 8-12: PHY address */
#define EMAC1_MADR_PHYADDR_MASK (31 << EMAC1_MADR_PHYADDR_SHIFT)
/* Bits 13-31: Reserved */
/* Ethernet Controller MAC MII Management Write Data Register */
#define EMAC1_MWTD_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MWTD_MASK (0xffff << EMAC1_MWTD_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC MII Management Read Data Register */
#define EMAC1_MRDD_SHIFT (0) /* Bits 0-15 */
#define EMAC1_MRDD_MASK (0xffff << EMAC1_MRDD_SHIFT)
/* Bits 16-31: Reserved */
/* Ethernet Controller MAC MII Management Indicators Register */
#define EMAC1_MIND_MIIMBUSY (1 << 0) /* Bit 0: Busy */
@ -774,7 +815,7 @@
#define EMAC1_MIND_LINKFAIL (1 << 3) /* Bit 3: MII link fail */
/* Bits 4-31: Reserved */
/* Descriptors Offsets ******************************************************************************/
/* Descriptors Offsets ******************************************************/
/* Tx descriptor offsets. The NEXTED field is only present if NPV=1 */
@ -820,8 +861,10 @@
#define RXDESC_NEXTED 4 /* Next Ethernet Descriptor (ED) */
#define RXLINKED_SIZE 5 /* Size in 32-bit words of one linked Rx descriptor */
/* Descriptor Bit Definitions ***********************************************************************/
/* Descriptor Bit Definitions ***********************************************/
/* Tx descriptor status bit definitions */
/* Bits 0-6: Reserved */
#define TXDESC_STATUS_EOWN (1 << 7) /* Bit 7: 1=Ethernet controller owns */
#define TXDESC_STATUS_SOWN (0) /* 0=Software owns */
@ -865,6 +908,7 @@
#define TXDESC_TSV2_TXUR (1 << 31) /* Bit 31: TSV31 Transmit Under-run */
/* Rx descriptor status bit definitions */
/* Bits 0-6: Reserved */
#define RXDESC_STATUS_EOWN (1 << 7) /* Bit 7: 1=Ethernet controller owns */
#define RXDESC_STATUS_SOWN (0) /* 0=Software owns */
@ -910,9 +954,9 @@
#define RXDESC_RSV2_VLAN (1 << 30) /* Bit 30: RSV30 Receive VLAN Type Detected */
/* Bit 31: RSV31 Reserved */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -960,13 +1004,13 @@ struct pic32mz_rxdesc_s
uint32_t nexted; /* Next Ethernet Descriptor (ED) */
};
/****************************************************************************************************
/****************************************************************************
* Inline Functions
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Function Prototypes
****************************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

5
arch/mips/src/pic32mz/hardware/pic32mz_int.h
View File

@ -32,6 +32,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MZ_INT_INTCON_OFFSET 0x0000 /* Interrupt control register */
@ -1133,6 +1134,7 @@
# define INT_INTCON_TPC_PRIO5 (5 << INT_INTCON_TPC_SHIFT) /* Int group priority <=5 start TP timer */
# define INT_INTCON_TPC_PRIO6 (6 << INT_INTCON_TPC_SHIFT) /* Int group priority <=6 start TP timer */
# define INT_INTCON_TPC_PRIO7 (7 << INT_INTCON_TPC_SHIFT) /* Int group priority <=7 start TP timer */
#define INT_INTCON_MVEC (1 << 12) /* Bit 12: Multi vector configuration */
/* Priority shadow select register */
@ -1171,7 +1173,8 @@
* reload value with no field definitions.
*/
/* Interrupt flag status register 0-5 and Interrupt enable control register 0-5
/* Interrupt flag status register 0-5 and Interrupt enable control
* register 0-5
* Contains interrupt status/control bits, one for each interrupt:
*
* IFS0/IEC0 - Interrupts 0-31

35
arch/mips/src/pic32mz/hardware/pic32mz_ioport.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_ioport.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_IOPORT_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_IOPORT_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/pic32mz/chip.h>
@ -31,10 +31,11 @@
#if CHIP_NPORTS > 0
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* IOPort Peripheral Offsets ****************************************************************/
****************************************************************************/
/* IOPort Peripheral Offsets ************************************************/
#define PIC32MZ_IOPORTA 0
#define PIC32MZ_IOPORTB 1
@ -59,7 +60,7 @@
# define PIC32MZ_IOPORTJ_OFFSET 0x0800
# define PIC32MZ_IOPORTK_OFFSET 0x0900
/* Register Offsets *************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MZ_IOPORT_ANSEL_OFFSET 0x0000 /* Analog select register */
#define PIC32MZ_IOPORT_ANSELCLR_OFFSET 0x0004 /* Analog select clear register */
@ -131,7 +132,7 @@
#define PIC32MZ_IOPORT_SRCON1SET_OFFSET 0x00d8 /* Slew Rate Control1 set register */
#define PIC32MZ_IOPORT_SRCON1INV_OFFSET 0x00dc /* Slew Rate Control1 invert register */
/* IOPort Peripheral Addresses **************************************************************/
/* IOPort Peripheral Addresses **********************************************/
#define PIC32MZ_IOPORTn_K1BASE(n) (PIC32MZ_IOPORT_K1BASE+PIC32MZ_IOPORTn_OFFSET(n))
# define PIC32MZ_IOPORTA_K1BASE (PIC32MZ_IOPORT_K1BASE+PIC32MZ_IOPORTA_OFFSET)
@ -145,7 +146,7 @@
# define PIC32MZ_IOPORTJ_K1BASE (PIC32MZ_IOPORT_K1BASE+PIC32MZ_IOPORTJ_OFFSET)
# define PIC32MZ_IOPORTK_K1BASE (PIC32MZ_IOPORT_K1BASE+PIC32MZ_IOPORTK_OFFSET)
/* Register Addresses ***********************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MZ_IOPORT_ANSEL(n) (PIC32MZ_IOPORTn_K1BASE(n)+PIC32MZ_IOPORT_ANSEL_OFFSET)
#define PIC32MZ_IOPORT_ANSELCLR(n) (PIC32MZ_IOPORTn_K1BASE(n)+PIC32MZ_IOPORT_ANSELCLR_OFFSET)
@ -789,7 +790,7 @@
# define PIC32MZ_IOPORTK_CNSTATINV (PIC32MZ_IOPORTK_K1BASE+PIC32MZ_IOPORT_CNSTATINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***********************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Analog select register */
@ -862,15 +863,15 @@
#define IOPORT_SRCON1(n) (1 << (n)) /* Bits 0-15: Slew Rate control pin n */
#define IOPORT_SRCON1_ALL 0x0000ffff
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
@ -880,9 +881,9 @@ extern "C"
#define EXTERN extern
#endif
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus

8
arch/mips/src/pic32mz/hardware/pic32mz_osc.h
View File

@ -47,6 +47,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MZ_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
@ -111,6 +112,7 @@
# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */
# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Internal low power RC oscillator */
# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* Internal fast RC / FRCDIV */
#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* Internal fast RC oscillator / FRCDIV */
@ -120,6 +122,7 @@
# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Internal low power RC oscillator */
# define OSCCON_COSC_BFRC (5 << OSCCON_COSC_SHIFT) /* Back-up Fast RC Oscillator */
# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* Internal fast RC / FRCDIV */
#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */
#define OSCCON_DRMEN (1 << 23) /* Bit 23: Dream mode enable */
#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */
@ -152,13 +155,16 @@
# define SPLLCON_PLLRANGE_13_26MHZ (3 << SPLLCON_PLLRANGE_SHIFT) /* 13-26 MHz */
# define SPLLCON_PLLRANGE_21_42MHZ (4 << SPLLCON_PLLRANGE_SHIFT) /* 21-42 MHz */
# define SPLLCON_PLLRANGE_34_64MHZ (5 << SPLLCON_PLLRANGE_SHIFT) /* 34-64 MHz */
#define SPLLCON_PLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Source bit */
#define SPLLCON_PLLIDIV_SHIFT (8) /* Bits 8-10: System PLL Input Clock Divider bits */
#define SPLLCON_PLLIDIV_MASK (7 << SPLLCON_PLLIDIV_SHIFT)
# define SPLLCON_PLLIDIV(n) ((uint32_t)((n)-1) << SPLLCON_PLLIDIV_SHIFT) /* Divide by n, n=1..8 */
#define SPLLCON_PLLMULT_SHIFT (16) /* Bits 16-22 <6:0>: System PLL Multiplier bits */
#define SPLLCON_PLLMULT_MASK (0x7f << SPLLCON_PLLMULT_SHIFT)
# define SPLLCON_PLLMULT(n) ((uint32_t)((n)-1) << SPLLCON_PLLMULT_SHIFT) /* Muliply by n, n=1..128 */
#define SPLLCON_PLLODIV_SHIFT (24) /* Bits 24-26: System PLL Output Clock Divider bits */
#define SPLLCON_PLLODIV_MASK (7 << SPLLCON_PLLODIV_SHIFT)
# define SPLLCON_PLLODIV_2 (1 << SPLLCON_PLLODIV_SHIFT) /* PLL Divide by 2 */
@ -180,6 +186,7 @@
# define REFOCON_ROSEL_SPLL (7 << REFOCON_ROSEL_SHIFT) /* System PLL output */
# define REFOCON_ROSEL_REFCLKI (8 << REFOCON_ROSEL_SHIFT) /* REFCLKIx */
# define REFOCON_ROSEL_BFRC (9 << REFOCON_ROSEL_SHIFT) /* BFRC */
#define REFOCON_ACTIVE (1 << 8) /* Bit 8: Reference Clock Request Status bit */
#define REFOCON_DIVSWEN (1 << 9) /* Bit 9: Divider Switch Enable bit */
#define REFOCON_RSLP (1 << 11) /* Bit 11: Reference Oscillator Module Run in Sleep bit */
@ -200,6 +207,7 @@
#define PBDIV_SHIFT (0) /* Bits 0-6: Peripheral Bus Clock Divisor Control bits */
#define PBDIV_MASK (0x7f << PBDIV_SHIFT)
# define PBDIV(n) ((uint32_t)((n)-1) << PBDIV_SHIFT) /* PBCLK = SYSLCK/n, n=1..128 */
#define PBDIV_PBDIVRDY (1 << 11) /* Bit 11: Peripheral Bus Clock Divisor Ready bit */
#define PBDIV_ON (1 << 15) /* Bit 15: Peripheral Bus Output Clock Enable bit */

63
arch/mips/src/pic32mz/hardware/pic32mz_pps.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_pps.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,18 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PPS_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PPS_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* PPS Register Offsets/Addresses ***********************************************************/
/* PPS Register Offsets/Addresses *******************************************/
/* Depends on the peripherals supported by the particular device */
@ -42,27 +39,35 @@
# error Unknown PIC32MZ family
#endif
/* PPS Register Bit Field Definitions *************************************(*****************/
/* All registers contain a single 4 bit field (bits 0-3) holding the peripheral pin
* selection.
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* PPS Register Bit Field Definitions ***************************************/
/* All registers contain a single 4 bit field (bits 0-3) holding the
* peripheral pin selection.
*/
#define PPS_MASK 0x0000000f
/* Pin Selection Helper Macros **************************************************************/
/* The encoding of the input pin selection is simple. Since we know the devices, we also
* can infer the register address so we need only the value for the register which is
* exactly what is provided by macro definitions.
/* Pin Selection Helper Macros **********************************************/
/* The encoding of the input pin selection is simple.
* Since we know the devices, we also can infer the register address so we
* need only the value for the register which is exactly what is provided
* by macro definitions.
*
* The encoding of the output pin selection is a little more complex. Knowing the device
* does not provide sufficient information. The output pin definitions include both the
* register value and the register address and the following helper macros can be used
* extract one or the other.
* The encoding of the output pin selection is a little more complex.
* Knowing the device does not provide sufficient information. The output
* pin definitions include both the register value and the register address
* and the following helper macros can be used extract one or the other.
*
* NOTE: These odd macro forms are used to work around a pre-processor issue. The argument
* to PPS_OUTPUT_REGADDR is defined to have the form nn,xxxx but the preprocessor would
* claim that only one parameter is passed. The following version takes only one parameter
* and keeps the pre-processor happy.
* NOTE: These odd macro forms are used to work around a pre-processor issue.
* The argument to PPS_OUTPUT_REGADDR is defined to have the form nn,xxxx
* but the preprocessor would claim that only one parameter is passed.
* The following version takes only one parameter and keeps the
* pre-processor happy.
*/
#define __PPS_OUTPUT_REGADDR(a,b) ((uintptr_t)(b))
@ -71,15 +76,15 @@
#define __PPS_OUTPUT_REGVAL(a,b) ((uint32_t)(a))
#define PPS_OUTPUT_REGVAL(a) __PPS_OUTPUT_REGVAL(a)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
@ -89,9 +94,9 @@ extern "C"
#define EXTERN extern
#endif
/********************************************************************************************
/****************************************************************************
* Public Function Prototypes
********************************************************************************************/
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus

21
arch/mips/src/pic32mz/hardware/pic32mz_prefetch.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_prefetch.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,45 +16,48 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PREFETCH_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PREFETCH_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "pic32mz_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Prefetch register offsets ****************************************************************/
****************************************************************************/
/* Prefetch register offsets ************************************************/
#define PIC32MZ_PRECON_OFFSET 0x0000 /* Prefetch module control register */
#define PIC32MZ_PRESTAT_OFFSET 0x0000 /* Prefetch module status register */
/* Prefetch register addresses **************************************************************/
/* Prefetch register addresses **********************************************/
#define PIC32MZ_PRECON (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRECON_OFFSET)
#define PIC32MZ_PRESTAT (PIC32MZ_PREFETCH_K1BASE+PIC32MZ_PRESTAT_OFFSET)
/* Prefetch register bit field definitions **************************************************/
/* Prefetch register bit field definitions **********************************/
/* Prefetch module control register */
#define PRECON_PFMWS_SHIFT (0) /* Bits 0-2: PFM Access Time */
#define PRECON_PFMWS_MASK (7 << PRECON_PFMWS_SHIFT)
# define PRECON_PFMWS(n) ((uint32_t)(n) << PRECON_PFMWS_SHIFT) /* n wait states, n=0..7 */
#define PRECON_PREFEN_SHIFT (4) /* Bit 4-5: Predictive Prefetch Enable */
#define PRECON_PREFEN_MASK (3 << PRECON_PREFEN_SHIFT)
# define PRECON_PREFEN_DISABLE (0 << PRECON_PREFEN_SHIFT) /* Disable predictive prefetch */
# define PRECON_PREFEN_CPUI (1 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions */
# define PRECON_PREFEN_CPUID (2 << PRECON_PREFEN_SHIFT) /* Predictive prefetch CPU instructions and data */
# define PRECON_PREFEN_ANY (3 << PRECON_PREFEN_SHIFT) /* Predictive prefetch any address */
#define PRECON_PFMSECEN (1 << 26) /* Bit 26: Flash SEC Interrupt Enable */
/* Prefetch module status register */

13
arch/mips/src/pic32mz/hardware/pic32mz_spi.h
View File

@ -192,12 +192,14 @@
# define SPI_CON_SRXISEL_NEMPTY (1 << SPI_CON_SRXISEL_SHIFT) /* Buffer not empty */
# define SPI_CON_SRXISEL_HALF (2 << SPI_CON_SRXISEL_SHIFT) /* Buffer half full or more */
# define SPI_CON_SRXISEL_FULL (3 << SPI_CON_SRXISEL_SHIFT) /* Buffer full */
#define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */
#define SPI_CON_STXISEL_MASK (3 << SPI_CON_STXISEL_SHIFT)
# define SPI_CON_STXISEL_DONE (0 << SPI_CON_STXISEL_SHIFT) /* Buffer empty (and data shifted out) */
# define SPI_CON_STXISEL_EMPTY (1 << SPI_CON_STXISEL_SHIFT) /* Buffer empty */
# define SPI_CON_STXISEL_HALF (2 << SPI_CON_STXISEL_SHIFT) /* Buffer half empty or more */
# define SPI_CON_STXISEL_NFULL (3 << SPI_CON_STXISEL_SHIFT) /* Buffer not full */
#define SPI_CON_DISSDI (1 << 4) /* Bit 4: Disable SDI */
#define SPI_CON_MSTEN (1 << 5) /* Bit 5: Master mode enable */
#define SPI_CON_CKP (1 << 6) /* Bit 6: Clock polarity select */
@ -215,6 +217,7 @@
# define SPI_CON_MODE_161632 (1 << SPI_CON_MODE_SHIFT) /* 16-bit data, 16-bit FIFO, 32-bit channel */
# define SPI_CON_MODE_323232 (2 << SPI_CON_MODE_SHIFT) /* 32-bit data, 32-bit FIFO, 32-bit channel */
# define SPI_CON_MODE_243232 (3 << SPI_CON_MODE_SHIFT) /* 24-bit data, 32-bit FIFO, 32-bit channel */
#define SPI_CON_DISSDO (1 << 12) /* Bit 12: Disable SDOx pin */
#define SPI_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define SPI_CON_ON (1 << 15) /* Bit 15: SPI peripheral on */
@ -230,6 +233,7 @@
# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
#define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
#define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
#define SPI_CON_FRMPOL (1 << 29) /* Bits 29: Frame sync polarity */
@ -244,18 +248,19 @@
# define SPI_CON2_AUDMOD_LJ (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
# define SPI_CON2_AUDMOD_RJ (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
# define SPI_CON2_AUDMOD_PCM (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
/* Bit 2: Reserved */
/* Bit 2: Reserved */
#define SPI_CON2_AUDMONO (1 << 3) /* Bit 3: Transmit Audio Data Format */
/* Bits 5-6: Reserved */
/* Bits 5-6: Reserved */
#define SPI_CON2_AUDEN (1 << 7) /* Bit 7: Enable Audio CODEC Support */
#define SPI_CON2_IGNTUR (1 << 8) /* Bit 8: Ignore Transmit Underrun bit */
#define SPI_CON2_IGNROV (1 << 9) /* Bit 9: Ignore Receive Overflow */
#define SPI_CON2_SPITUREN (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */
#define SPI_CON2_SPIROVEN (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */
#define SPI_CON2_FRMERREN (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */
/* Bits 13-14: Reserved */
/* Bits 13-14: Reserved */
#define SPI_CON2_SPISGNEXT (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */
/* Bits 16-31: Reserved */
/* Bits 16-31: Reserved */
/* SPI status register */

38
arch/mips/src/pic32mz/hardware/pic32mz_timer.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_timer.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_TIMER_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,10 +32,11 @@
#if CHIP_NTIMERS > 0
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Timer Peripheral Offsets *********************************************************/
****************************************************************************/
/* Timer Peripheral Offsets *************************************************/
#define PIC32MZ_TIMERn_OFFSET(n) ((n) << 9)
# define PIC32MZ_TIMER1_OFFSET 0x0000
@ -48,7 +49,7 @@
# define PIC32MZ_TIMER8_OFFSET 0x0e00
# define PIC32MZ_TIMER9_OFFSET 0x1000
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MZ_TIMER_CON_OFFSET 0x0000 /* Timer control register */
#define PIC32MZ_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
@ -65,7 +66,7 @@
#define PIC32MZ_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
#define PIC32MZ_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
/* Timer Peripheral Addresses *******************************************************/
/* Timer Peripheral Addresses ***********************************************/
#define PIC32MZ_TIMERn_K1BASE(n) (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMERn_OFFSET(n))
# define PIC32MZ_TIMER1_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER1_OFFSET)
@ -78,7 +79,7 @@
# define PIC32MZ_TIMER8_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER8_OFFSET)
# define PIC32MZ_TIMER9_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER9_OFFSET)
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define PIC32MZ_TIMER_CON(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER_CONCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONCLR_OFFSET)
@ -226,8 +227,7 @@
# define PIC32MZ_TIMER9_PRINV (PIC32MZ_TIMER9_K1BASE+PIC32MZ_TIMER_PRINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Timer control register */
@ -244,12 +244,14 @@
# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
@ -264,19 +266,19 @@
#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

39
arch/mips/src/pic32mz/hardware/pic32mz_uart.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mz_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_UART_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/pic32mz/chip.h>
#include "hardware/pic32mz_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* UART Peripheral Offsets **********************************************************/
****************************************************************************/
/* UART Peripheral Offsets **************************************************/
#define PIC32MZ_UARTn_OFFSET(n) ((n) << 9)
# define PIC32MZ_UART1_OFFSET 0x0000
@ -43,7 +44,7 @@
# define PIC32MZ_UART5_OFFSET 0x0800
# define PIC32MZ_UART6_OFFSET 0x0a00
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define PIC32MZ_UART_MODE_OFFSET 0x0000 /* UARTx mode register */
#define PIC32MZ_UART_MODECLR_OFFSET 0x0004 /* UARTx mode clear register */
@ -63,7 +64,7 @@
#define PIC32MZ_UART_BRGSET_OFFSET 0x0048 /* UARTx baud rate set register */
#define PIC32MZ_UART_BRGINV_OFFSET 0x004c /* UARTx baud rate invert register */
/* Timer Peripheral Addresses *******************************************************/
/* Timer Peripheral Addresses ***********************************************/
#define PIC32MZ_UARTn_K1BASE(n) (PIC32MZ_UART_K1BASE+PIC32MZ_UARTn_OFFSET(n))
# define PIC32MZ_UART1_K1BASE (PIC32MZ_UART_K1BASE+PIC32MZ_UART1_OFFSET)
@ -76,7 +77,7 @@
# define PIC32MZ_UART8_K1BASE (PIC32MZ_UART_K1BASE+PIC32MZ_UART8_OFFSET)
# define PIC32MZ_UART9_K1BASE (PIC32MZ_UART_K1BASE+PIC32MZ_UART9_OFFSET)
/* Register Addresses ****************************************************************/
/* Register Addresses *******************************************************/
#if CHIP_NUARTS > 0
# define PIC32MZ_UART1_MODE (PIC32MZ_UART1_K1BASE+PIC32MZ_UART_MODE_OFFSET)
@ -180,7 +181,7 @@
# define PIC32MZ_UART6_BRGINV (PIC32MZ_UART6_K1BASE+PIC32MZ_UART_BRGINV_OFFSET)
#endif
/* Register Bit-Field Definitions ****************************************************/
/* Register Bit-Field Definitions *******************************************/
/* UARTx mode register */
@ -191,6 +192,7 @@
# define UART_MODE_PDSEL_8EVEN (1 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, even parity */
# define UART_MODE_PDSEL_8ODD (2 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, odd parity */
# define UART_MODE_PDSEL_9NONE (3 << UART_MODE_PDSEL_SHIFT) /* 9-bit data, no parity */
#define UART_MODE_BRGH (1 << 3) /* Bit 3: High baud rate enable */
#define UART_MODE_RXINV (1 << 4) /* Bit 4: Receive polarity inversion */
#define UART_MODE_ABAUD (1 << 5) /* Bit 5: Auto-baud enable */
@ -202,6 +204,7 @@
# define UART_MODE_UEN_ENR_CPORT (1 << UART_MODE_UEN_SHIFT) /* UxRTS=enabled; UxCTS=PORTx register */
# define UART_MODE_UEN_ENCR (2 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS=enabled */
# define UART_MODE_UEN_CPORT (3 << UART_MODE_UEN_SHIFT) /* UxCTS=PORTx register */
#define UART_MODE_RTSMD (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */
#define UART_MODE_IREN (1 << 12) /* Bit 12: IrDA encoder and decoder enable */
#define UART_MODE_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
@ -220,6 +223,7 @@
# define UART_STA_URXISEL_RECVD (0 << UART_STA_URXISEL_SHIFT) /* Character received */
# define UART_STA_URXISEL_RXB50 (1 << UART_STA_URXISEL_SHIFT) /* RX buffer 1/2 full */
# define UART_STA_URXISEL_RXB75 (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 full */
#define UART_STA_UTRMT (1 << 8) /* Bit 8: Transmit shift register is empty */
#define UART_STA_UTXBF (1 << 9) /* Bit 9: Transmit buffer full status */
#define UART_STA_UTXEN (1 << 10) /* Bit 10: Transmit enable */
@ -231,6 +235,7 @@
# define UART_STA_UTXISEL_TXBNF (0 << UART_STA_UTXISEL_SHIFT) /* TX buffer not full */
# define UART_STA_UTXISEL_DRAINED (1 << UART_STA_UTXISEL_SHIFT) /* All characters sent */
# define UART_STA_UTXISEL_TXBE (2 << UART_STA_UTXISEL_SHIFT) /* TX buffer empty */
#define UART_STA_ADDR_SHIFT (16) /* Bits:16-23: Automatic address mask */
#define UART_STA_ADDR_MASK (0xff << UART_STA_ADDR_SHIFT)
#define UART_STA_ADM_EN (1 << 24) /* Bit 24: Automatic address detect mode enable */
@ -247,19 +252,19 @@
#define UART_BRG_MASK 0xffff
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"

49
arch/mips/src/pic32mz/hardware/pic32mzec_features.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzec_features.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register/Flash Offsets ***********************************************************/
****************************************************************************/
/* Register/Flash Offsets ***************************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
@ -84,7 +85,7 @@
#define PIC32MZ_DEVSN0_OFFSET 0x0000 /* Device serial number 0 */
#define PIC32MZ_DEVSN1_OFFSET 0x0004 /* Device serial number 1 */
/* Register/Flash Addresses *********************************************************/
/* Register/Flash Addresses *************************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
@ -133,17 +134,21 @@
#define PIC32MZ_DEVADC4 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC4_OFFSET)
#define PIC32MZ_DEVADC5 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVADC5_OFFSET)
/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */
/* Device Serial Number
* (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE)
*/
#define PIC32MZ_DEVSN0 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN0_OFFSET)
#define PIC32MZ_DEVSN1 (PIC32MZ_ADCCALIB_K1BASE+PIC32MZ_DEVSN1_OFFSET)
/* Register/Flash Bit Field Definitions *********************************************/
/* Register/Flash Bit Field Definitions *************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
/* Configuration control register
*
* NOTE: To change many of the bits in the register, the unlock sequence must first
* NOTE:
* To change many of the bits in the register, the unlock sequence must first
* be performed.
*/
@ -156,6 +161,7 @@
# define CFGCON_ECCCON_DYNECC (1 << CFGCON_ECCCON_SHIFT) /* Dynamic Flash ECC enabled */
# define CFGCON_ECCCON_DISLCK (2 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */
# define CFGCON_ECCCON_DISWR (3 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */
#define CFGCON_USBSSEN (1 << 8) /* Bit 8: USB Suspend Sleep Enable bit */
#define CFGCON_PGLOCK (1 << 11) /* Bit 11: Permission Group Lock bit */
#define CFGCON_PMDLOCK (1 << 12) /* Bit 12: Peripheral Module Disable bit */
@ -290,7 +296,9 @@
# define CFGPG_CRYPTPG_GROUP3 CFGPG_CRYPTPG(CFGPG_GROUP3)
/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
/* Device configuration word 3 / Alternate device configuration word 3 */
#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */
@ -316,6 +324,7 @@
#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL Input Divider bits */
#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT)
# define DEVCFG2_FPLLIDIV(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLIDIV_SHIFT) /* n=1..8 */
# define DEVCFG2_FPLLIDIV_1 (0 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 1 */
# define DEVCFG2_FPLLIDIV_2 (1 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 2 */
# define DEVCFG2_FPLLIDIV_3 (2 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 3 */
@ -324,6 +333,7 @@
# define DEVCFG2_FPLLIDIV_6 (5 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 6 */
# define DEVCFG2_FPLLIDIV_7 (6 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 7 */
# define DEVCFG2_FPLLIDIV_8 (7 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 8 */
#define DEVCFG2_FPLLRNG_SHIFT (4) /* Bits 4-6: System PLL Divided Input Clock Frequency Range bits */
#define DEVCFG2_FPLLRNG_MASK (7 << DEVCFG2_FPLLRNG_SHIFT)
# define DEVCFG2_FPLLRNG_BYPASS (0 << DEVCFG2_FPLLRNG_SHIFT) /* Bypass */
@ -332,10 +342,12 @@
# define DEVCFG2_FPLLRNG_13_26MHZ (3 << DEVCFG2_FPLLRNG_SHIFT) /* 13-26 MHz */
# define DEVCFG2_FPLLRNG_21_42MHZ (4 << DEVCFG2_FPLLRNG_SHIFT) /* 21-42 MHz */
# define DEVCFG2_FPLLRNG_34_64MHZ (5 << DEVCFG2_FPLLRNG_SHIFT) /* 34-64 MHz */
#define DEVCFG2_FPLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Select bit */
#define DEVCFG2_FPLLMULT_SHIFT (8) /* Bits 8-14: System PLL Feedback Divider bits */
#define DEVCFG2_FPLLMULT_MASK (0x7f << DEVCFG2_FPLLMULT_SHIFT)
# define DEVCFG2_FPLLMULT(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLMULT_SHIFT) /* n=1..128 */
#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default System PLL Output Divisor bits */
#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT)
# define DEVCFG2_FPLLODIV_2 (1 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 2 */
@ -343,6 +355,7 @@
# define DEVCFG2_FPLLODIV_8 (3 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 8 */
# define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */
# define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */
#define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */
# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */
# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */
@ -359,6 +372,7 @@
# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */
# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */
# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */
#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT)
# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */
@ -369,6 +383,7 @@
# define DEVCFG1_DMTINV_31_32 (5 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 31/32 counter */
# define DEVCFG1_DMTINV_63_64 (6 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 63/64 counter */
# define DEVCFG1_DMTINV_127_128 (7 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 127/128 counter */
#define DEVCFG1_FSOSCEN (1 << 6) /* Bit 6: Secondary Oscillator Enable bit */
#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal External Switchover bit */
#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary Oscillator Configuration bits */
@ -376,6 +391,7 @@
# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode selected */
# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS Oscillator mode selected */
# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* POSC disabled */
#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO Enable Configuration bit */
#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock Switching and Monitoring Selection */
#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT)
@ -383,6 +399,7 @@
# define DEVCFG1_FCKSM_SWITCH (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching enabled */
# define DEVCFG1_FCKSM_MONITOR (2 << DEVCFG1_FCKSM_SHIFT) /* Clock monitoring enabled */
# define DEVCFG1_FCKSM_BOTH (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring enabled */
#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: Watchdog Timer Postscale Select bits */
#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT)
# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */
@ -406,6 +423,7 @@
# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */
# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */
# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */
@ -421,11 +439,14 @@
# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */
# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */
# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */
# define DEVCFG1_DMTCNT_MAX (23 << DEVCFG1_DMTCNT_SHIFT) /* 2**31 (2147483648) */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */
@ -436,11 +457,13 @@
#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT)
# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT) /* Debugger is enabled */
# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT) /* Debugger is disabled */
#define DEVCFG0_JTAGEN (1 << 2) /* Bit 2: JTAG Enable bit(1) */
#define DEVCFG0_ICESEL_SHIFT (3) /* Bits 3-4: ICE Communication Channel Select bits */
#define DEVCFG0_ICESEL_MASK (3 << DEVCFG0_ICESEL_SHIFT)
# define DEVCFG0_ICESEL_1 (3 << DEVCFG0_ICESEL_SHIFT) /* PGEC1/PGED1 pair is used */
# define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */
#define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */
#define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */
# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */
@ -451,6 +474,7 @@
# define DEVCFG0_FECCCON_DYNECC (1 << DEVCFG0_FECCCON_SHIFT) /* Dynamic Flash ECC enabled (locked) */
# define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */
# define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */
#define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */
# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */
# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */
@ -460,6 +484,7 @@
# define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */
# define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */
# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */
#define DEVCFG0_EJTAGBEN (1 << 30) /* Bit 30: EJTAG Boot Enable bit */
# define DEVCFG0_EJTAG_NORMAL (1 << 30) /* Bit 30=1: Normal EJTAG functionality */
# define DEVCFG0_EJTAG_REDUCED (0 << 30) /* Bit 30=0: Reduced EJTAG functionality */
@ -491,9 +516,11 @@
#define DEVSIGN0_RWO 0x7fffffff /* Bits 0-30: Reserved, write as one */
/* Device ADC Calibration (Boot Flash PIC32MZ_ADCCALIB_K1BASE) */
/* ADC1-5 Calibration: 32-bit calibration values */
/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
/* Device serial number 0-1: 32-bit serial number data */
#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H */

20
arch/mips/src/pic32mz/hardware/pic32mzec_memorymap.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzec_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_MEMORYMAP_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "mips32-memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Physical Memory Map **************************************************************/
****************************************************************************/
/* Physical Memory Map ******************************************************/
/* Memory Regions */
#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
@ -54,7 +56,7 @@
#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */
#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff40 /* Sequence/configuration space 2 */
/* Virtual Memory Map ***************************************************************/
/* Virtual Memory Map *******************************************************/
#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE)
#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE)
@ -92,7 +94,7 @@
#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE)
#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE)
/* Register Base Addresses **********************************************************/
/* Register Base Addresses **************************************************/
#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */
#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */

34
arch/mips/src/pic32mz/hardware/pic32mzec_pps.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzec_pps.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_PPS_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_PPS_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include "pic32mz_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* PPS Register Offsets *********************************************************************/
/* PPS Register Offsets *****************************************************/
/* Peripheral pin select input register map */
@ -165,7 +165,7 @@
# define PIC32MZ_RPG8R_OFFSET 0x16a0
# define PIC32MZ_RPG9R_OFFSET 0x16a4
/* PPS Register Addresses *******************************************************************/
/* PPS Register Addresses ***************************************************/
#define PIC32MZ_INTnR(n) (PIC32MZ_SFR_K1BASE+PIC32MZ_INTnR_OFFSET(n))
# define PIC32MZ_INT1R (PIC32MZ_SFR_K1BASE+PIC32MZ_INT1R_OFFSET)
@ -297,9 +297,11 @@
# define PIC32MZ_RPG8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG8R_OFFSET)
# define PIC32MZ_RPG9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG9R_OFFSET)
/* Input Pin Selection **********************************************************************/
/* The encoding of the input pin selection is simple. Since we know the devices, we also
* can infer the register address so we need only the value for the register which is
/* Input Pin Selection ******************************************************/
/* The encoding of the input pin selection is simple.
* Since we know the devices, we also can infer the register
* address so we need only the value for the register which is
* exactly what is provided by the following definitions.
*/
@ -1030,10 +1032,12 @@
#define U6RXR_RPF13 9
#define U6RXR_RPG9 1
/* Output Pin Selection *********************************************************************/
/* The encoding of the output pin selection is a little more complex. Knowing the device
* does not provide sufficient information. So the following definitions include both the
* register value and the register address.
/* Output Pin Selection *****************************************************/
/* The encoding of the output pin selection is a little more complex.
* Knowing the device does not provide sufficient information.
* So the following definitions include both the register value and
* the register address.
*/
#define C1OUT_RPB0R 14, PI32MZ_RPB0R

51
arch/mips/src/pic32mz/hardware/pic32mzef_features.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzef_features.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register/Flash Offsets ***********************************************************/
****************************************************************************/
/* Register/Flash Offsets ***************************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
@ -85,7 +86,7 @@
#define PIC32MZ_DEVSN0_OFFSET 0x0020 /* Device serial number 0 */
#define PIC32MZ_DEVSN1_OFFSET 0x0024 /* Device serial number 1 */
/* Register/Flash Addresses *********************************************************/
/* Register/Flash Addresses *************************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
@ -135,17 +136,21 @@
#define PIC32MZ_DEVADC4 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC4_OFFSET)
#define PIC32MZ_DEVADC7 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVADC7_OFFSET)
/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE) */
/* Device Serial Number
*(Boot Flash PIC32MZ_DEVSN_K1BASEPIC32MZ_DEVSN_K1BASE)
*/
#define PIC32MZ_DEVSN0 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN0_OFFSET)
#define PIC32MZ_DEVSN1 (PIC32MZ_DEVSN_K1BASE+PIC32MZ_DEVSN1_OFFSET)
/* Register/Flash Bit Field Definitions *********************************************/
/* Register/Flash Bit Field Definitions *************************************/
/* Device ID, Revision, and Configuration (SFR PIC32MZ_CONFIG_K1BASE) */
/* Configuration control register
*
* NOTE: To change many of the bits in the register, the unlock sequence must first
* NOTE:
* To change many of the bits in the register, the unlock sequence must first
* be performed.
*/
@ -158,6 +163,7 @@
# define CFGCON_ECCCON_DYNECC (1 << CFGCON_ECCCON_SHIFT) /* Dynamic Flash ECC enabled */
# define CFGCON_ECCCON_DISLCK (2 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */
# define CFGCON_ECCCON_DISWR (3 << CFGCON_ECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */
#define CFGCON_IOANCPEN (1 << 7) /* Bit 7: I/O Analog Charge Pump Enable bit */
#define CFGCON_USBSSEN (1 << 8) /* Bit 8: USB Suspend Sleep Enable bit */
#define CFGCON_PGLOCK (1 << 11) /* Bit 11: Permission Group Lock bit */
@ -303,7 +309,9 @@
# define CFGPG_CRYPTPG_GROUP3 CFGPG_CRYPTPG(CFGPG_GROUP3)
/* Alternate Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
/* Device Configuration (Boot Flash PIC32MZ_BOOTCFG_K1BASE) */
/* Device configuration word 3 / Alternate device configuration word 3 */
#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */
@ -329,6 +337,7 @@
#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL Input Divider bits */
#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT)
# define DEVCFG2_FPLLIDIV(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLIDIV_SHIFT) /* n=1..8 */
# define DEVCFG2_FPLLIDIV_1 (0 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 1 */
# define DEVCFG2_FPLLIDIV_2 (1 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 2 */
# define DEVCFG2_FPLLIDIV_3 (2 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 3 */
@ -337,6 +346,7 @@
# define DEVCFG2_FPLLIDIV_6 (5 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 6 */
# define DEVCFG2_FPLLIDIV_7 (6 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 7 */
# define DEVCFG2_FPLLIDIV_8 (7 << DEVCFG2_FPLLIDIV_SHIFT) /* Divide by 8 */
#define DEVCFG2_FPLLRNG_SHIFT (4) /* Bits 4-6: System PLL Divided Input Clock Frequency Range bits */
#define DEVCFG2_FPLLRNG_MASK (7 << DEVCFG2_FPLLRNG_SHIFT)
# define DEVCFG2_FPLLRNG_BYPASS (0 << DEVCFG2_FPLLRNG_SHIFT) /* Bypass */
@ -345,10 +355,12 @@
# define DEVCFG2_FPLLRNG_13_26MHZ (3 << DEVCFG2_FPLLRNG_SHIFT) /* 13-26 MHz */
# define DEVCFG2_FPLLRNG_21_42MHZ (4 << DEVCFG2_FPLLRNG_SHIFT) /* 21-42 MHz */
# define DEVCFG2_FPLLRNG_34_64MHZ (5 << DEVCFG2_FPLLRNG_SHIFT) /* 34-64 MHz */
#define DEVCFG2_FPLLICLK (1 << 7) /* Bit 7: System PLL Input Clock Select bit */
#define DEVCFG2_FPLLMULT_SHIFT (8) /* Bits 8-14: System PLL Feedback Divider bits */
#define DEVCFG2_FPLLMULT_MASK (0x7f << DEVCFG2_FPLLMULT_SHIFT)
# define DEVCFG2_FPLLMULT(n) ((uint32_t)((n)-1) << DEVCFG2_FPLLMULT_SHIFT) /* n=1..128 */
#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default System PLL Output Divisor bits */
#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT)
# define DEVCFG2_FPLLODIV_2 (1 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 2 */
@ -356,6 +368,7 @@
# define DEVCFG2_FPLLODIV_8 (3 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 8 */
# define DEVCFG2_FPLLODIV_16 (4 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 16 */
# define DEVCFG2_FPLLODIV_32 (5 << DEVCFG2_FPLLODIV_SHIFT) /* PLL output divided by 32 */
#define DEVCFG2_UPLLFSEL (1 << 30) /* Bit 30: USB PLL Input Frequency Select bit */
# define DEVCFG2_UPLLFSEL_24MHZ (1 << 30) /* Bit 30=1: UPLL input clock is 24 MHz */
# define DEVCFG2_UPLLFSEL_12MHZ (0 << 30) /* Bit 30=0: UPLL input clock is 12 MHz */
@ -372,6 +385,7 @@
# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */
# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */
# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */
#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT)
# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */
@ -382,6 +396,7 @@
# define DEVCFG1_DMTINV_31_32 (5 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 31/32 counter */
# define DEVCFG1_DMTINV_63_64 (6 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 63/64 counter */
# define DEVCFG1_DMTINV_127_128 (7 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value 127/128 counter */
#define DEVCFG1_FSOSCEN (1 << 6) /* Bit 6: Secondary Oscillator Enable bit */
#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal External Switchover bit */
#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary Oscillator Configuration bits */
@ -389,6 +404,7 @@
# define DEVCFG1_POSCMOD_EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode selected */
# define DEVCFG1_POSCMOD_HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS Oscillator mode selected */
# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* POSC disabled */
#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO Enable Configuration bit */
#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock Switching and Monitoring Selection */
#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT)
@ -396,6 +412,7 @@
# define DEVCFG1_FCKSM_SWITCH (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching enabled */
# define DEVCFG1_FCKSM_MONITOR (2 << DEVCFG1_FCKSM_SHIFT) /* Clock monitoring enabled */
# define DEVCFG1_FCKSM_BOTH (3 << DEVCFG1_FCKSM_SHIFT) /* Clock switching/monitoring enabled */
#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: Watchdog Timer Postscale Select bits */
#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT)
# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */
@ -419,6 +436,7 @@
# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: WDT stop/run during flash programming bit */
# define DEVCFG1_WDTSPGM_STOP (1 << 21) /* Bit 21=1: WDT stops during flash programming */
# define DEVCFG1_WDTSPGM_RUN (0 << 21) /* Bit 21=0: WDT runs during flash programming */
@ -434,12 +452,15 @@
# define DEVCFG1_FWDTWINSZ_50 (1 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 50% */
# define DEVCFG1_FWDTWINSZ_37p5 (2 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 37.5% */
# define DEVCFG1_FWDTWINSZ_25 (3 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 25% */
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */
# define DEVCFG1_DMTCNT_MAX (23 << DEVCFG1_DMTCNT_SHIFT) /* 2**31 (2147483648) */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */
@ -449,11 +470,13 @@
#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT)
# define DEVCFG0_DEBUG_ENABLED (2 << DEVCFG0_DEBUG_SHIFT) /* Debugger is enabled */
# define DEVCFG0_DEBUG_DISABLED (3 << DEVCFG0_DEBUG_SHIFT) /* Debugger is disabled */
#define DEVCFG0_JTAGEN (1 << 2) /* Bit 2: JTAG Enable bit(1) */
#define DEVCFG0_ICESEL_SHIFT (3) /* Bits 3-4: ICE Communication Channel Select bits */
#define DEVCFG0_ICESEL_MASK (3 << DEVCFG0_ICESEL_SHIFT)
# define DEVCFG0_ICESEL_1 (3 << DEVCFG0_ICESEL_SHIFT) /* PGEC1/PGED1 pair is used */
# define DEVCFG0_ICESEL_2 (2 << DEVCFG0_ICESEL_SHIFT) /* PGEC2/PGED2 pair is used */
#define DEVCFG0_TRCEN (1 << 5) /* Bit 5: Trace Enable bit */
#define DEVCFG0_BOOTISA (1 << 6) /* Bit 6: Boot ISA Selection bit */
# define DEVCFG0_BOOT_MIPS32 (1 << 6) /* Bit 6=1: Boot code and Exception code is MIPS32 */
@ -464,6 +487,7 @@
# define DEVCFG0_FECCCON_DYNECC (1 << DEVCFG0_FECCCON_SHIFT) /* Dynamic Flash ECC enabled (locked) */
# define DEVCFG0_FECCCON_DISLCK (2 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (locked) */
# define DEVCFG0_FECCCON_DISWR (3 << DEVCFG0_FECCCON_SHIFT) /* ECC / dynamic ECC disabled (writable) */
#define DEVCFG0_FSLEEP (1 << 10) /* Bit 10: Flash Sleep Mode bit */
# define DEVCFG0_FSLEEP_OFF (1 << 10) /* Bit 10=1: Flash powered down in sleep mode */
# define DEVCFG0_FSLEEP_ON (0 << 10) /* Bit 10=0: Flash powerdown controlled by VREGS bit */
@ -473,6 +497,7 @@
# define DEVCFG0_DBGPER_GROUP1 (2 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 1 regions */
# define DEVCFG0_DBGPER_GROUP2 (4 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to group 2 regions */
# define DEVCFG0_DBGPER_ALL (7 << DEVCFG0_DBGPER_SHIFT) /* Allow/deny access to all regions */
#define DEVCFG0_SMCLR (1 << 15) /* Bit 15: Soft Master Clear Enable bit */
#define DEVCFG0_SOSCGAIN_SHIFT (16) /* Bits 16-17: Secondary Oscillator Gain Control bits */
#define DEVCFG0_SOSCGAIN_MASK (3 << DEVCFG0_SOSCGAIN_SHIFT)
@ -517,9 +542,11 @@
#define DEVSIGN0_RWO 0x7fffffff /* Bits 0-30: Reserved, write as one */
/* Device ADC Calibration (Boot Flash PIC32MZ_DEVSN_K1BASE) */
/* ADC0-4,7 Calibration: 32-bit calibration values */
/* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
/* Device serial number 0-1: 32-bit serial number data */
#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H */

20
arch/mips/src/pic32mz/hardware/pic32mzef_memorymap.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzef_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,23 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_MEMORYMAP_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "mips32-memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Physical Memory Map **************************************************************/
****************************************************************************/
/* Physical Memory Map ******************************************************/
/* Memory Regions */
#define PIC32MZ_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
@ -53,7 +55,7 @@
#define PIC32MZ_BOOT2_PBASE 0x1fc60000 /* Boot flash 2 */
#define PIC32MZ_SEQCFG2_PBASE 0x1fc6ff00 /* Sequence/configuration space 2 */
/* Virtual Memory Map ***************************************************************/
/* Virtual Memory Map *******************************************************/
#define PIC32MZ_DATAMEM_K0BASE (KSEG0_BASE + PIC32MZ_DATAMEM_PBASE)
#define PIC32MZ_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MZ_PROGFLASH_PBASE)
@ -89,7 +91,7 @@
#define PIC32MZ_BOOT2_K1BASE (KSEG1_BASE + PIC32MZ_BOOT2_PBASE)
#define PIC32MZ_SEQCFG2_K1BASE (KSEG1_BASE + PIC32MZ_SEQCFG2_PBASE)
/* Register Base Addresses **********************************************************/
/* Register Base Addresses **************************************************/
#define PIC32MZ_CONFIG_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000000) /* Configuration */
#define PIC32MZ_FLASHC_K1BASE (PIC32MZ_SFR_K1BASE + 0x00000600) /* Flash Controller */

37
arch/mips/src/pic32mz/hardware/pic32mzef_pps.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/hardware/pic32mzef_pps.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,21 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_PPS_H
#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_PPS_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include "pic32mz_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* PPS Register Offsets *********************************************************************/
****************************************************************************/
/* PPS Register Offsets *****************************************************/
/* Peripheral pin select input register map */
@ -164,7 +165,7 @@
# define PIC32MZ_RPG8R_OFFSET 0x16a0
# define PIC32MZ_RPG9R_OFFSET 0x16a4
/* PPS Register Addresses *******************************************************************/
/* PPS Register Addresses ***************************************************/
/* Peripheral pin select input register map */
@ -298,10 +299,12 @@
# define PIC32MZ_RPG8R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG8R_OFFSET)
# define PIC32MZ_RPG9R (PIC32MZ_SFR_K1BASE+PIC32MZ_RPG9R_OFFSET)
/* Input Pin Selection **********************************************************************/
/* The encoding of the input pin selection is simple. Since we know the devices, we also
* can infer the register address so we need only the value for the register which is
* exactly what is provided by the following definitions.
/* Input Pin Selection ******************************************************/
/* The encoding of the input pin selection is simple. Since we know the
* devices, we also can infer the register address so we need only the value
* for the register which is exactly what is provided by the following
* definitions.
*/
#define C1RXR_RPA15 13
@ -1031,10 +1034,12 @@
#define U6RXR_RPF13 9
#define U6RXR_RPG9 1
/* Output Pin Selection *********************************************************************/
/* The encoding of the output pin selection is a little more complex. Knowing the device
* does not provide sufficient information. So the following definitions include both the
* register value and the register address.
/* Output Pin Selection *****************************************************/
/* The encoding of the output pin selection is a little more complex.
* Knowing the device does not provide sufficient information. So the
* following definitions include both the register value and the register
* address.
*/
#define C1OUT_RPB0R 14, PI32MZ_RPB0R

48
arch/mips/src/pic32mz/pic32mz_config.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,30 +16,30 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include <arch/board/board.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Cache line sizes (in bytes) for the PIC32MZ */
#define PIC32MZ_DCACHE_LINESIZE 16 /* 16 bytes (4 words) */
#define PIC32MZ_ICACHE_LINESIZE 16 /* 16 bytes (4 words) */
/* GPIO IRQs ************************************************************************/
/* GPIO IRQs ****************************************************************/
#ifndef CONFIG_PIC32MZ_GPIOIRQ
# undef CONFIG_PIC32MZ_GPIOIRQ_PORTA
@ -85,7 +85,8 @@
# undef CONFIG_PIC32MZ_GPIOIRQ_PORTK
#endif
/* UARTs ****************************************************************************/
/* UARTs ********************************************************************/
/* Don't enable UARTs not supported by the chip. */
#if CHIP_NUARTS < 1
@ -182,7 +183,8 @@
# undef HAVE_SERIAL_CONSOLE
#endif
/* SPI ******************************************************************************/
/* SPI **********************************************************************/
/* Don't enable SPI peripherals not supported by the chip. */
#if CHIP_NSPI < 1
@ -223,7 +225,8 @@
# define CONFIG_PIC32MZ_SPI 1
#endif
/* I2C ******************************************************************************/
/* I2C **********************************************************************/
/* Don't enable I2C peripherals not supported by the chip. */
#if CHIP_NI2C < 1
@ -257,8 +260,10 @@
# define CONFIG_PIC32MZ_I2C 1
#endif
/* Device Configuration *************************************************************/
/* Device Configuration *****************************************************/
/* DEVCFG3 */
/* Configurable settings */
#ifndef CONFIG_PIC32MZ_USERID /* User ID */
@ -295,6 +300,7 @@
#endif
/* DEVCFG2 */
/* PLL Input Divider bits */
#undef CONFIG_PIC32MZ_PLLIDIV
@ -387,6 +393,7 @@
/* USB PLL Input Frequency Select bit */
/* DEVCFG1 */
/* Configurable settings */
#undef CONFIG_PIC32MZ_FNOSC
@ -519,6 +526,7 @@
#define CONFIG_PIC32MZ_FDMTEN 0
/* DEVCFG0 */
/* Configurable settings */
#undef CONFIG_PIC32MZ_DEBUGGER
@ -585,20 +593,20 @@
#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL
#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CONFIG_H */

68
arch/mips/src/pic32mz/pic32mz_dma.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,7 +16,7 @@
* License for the specific language governing permissions and limitations
* under the License.
*
*****************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_DMA_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_DMA_H
@ -45,7 +45,8 @@
*
* If a start irq is set this function will only enable the channel.
* The transfer will be controlled by the start irq.
* If start irq is set to PIC32MZ_DMA_NOIRQ then a force start is performed.
* If start irq is set to PIC32MZ_DMA_NOIRQ then a force start is
* performed.
*
* 4. Stop and free the channel
*
@ -55,9 +56,9 @@
* pic32mz_dma_free will free the channel and make it available.
*/
/*****************************************************************************
/****************************************************************************
* Included Files
*****************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
@ -65,17 +66,17 @@
#include <sys/types.h>
#include <stdint.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* This is used when setting a channel with no start/abort irq */
#define PIC32MZ_DMA_NOIRQ (NR_IRQS + 1)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -187,9 +188,9 @@ struct pic32mz_dmaregs_s
};
#endif
/*****************************************************************************
/****************************************************************************
* Public Data
******************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@ -200,27 +201,27 @@ extern "C"
#define EXTERN extern
#endif
/******************************************************************************
/****************************************************************************
* Public Function Prototypes
******************************************************************************/
****************************************************************************/
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_alloc
*
* Description:
* Allocate a DMA channel. This function sets aside a DMA channel and gives
* the caller exclusive access to the DMA channel.
* Allocate a DMA channel. This function sets aside a DMA channel and
* gives the caller exclusive access to the DMA channel.
*
* Returned Value:
* On success, this function returns a non-NULL, void* DMA channel handle.
* NULL is returned on any failure.
* This function can fail only if no DMA channel is available.
*
******************************************************************************/
****************************************************************************/
DMA_HANDLE pic32mz_dma_alloc(const struct pic32mz_dma_chcfg_s *cfg);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_free
*
* Description:
@ -231,11 +232,11 @@ DMA_HANDLE pic32mz_dma_alloc(const struct pic32mz_dma_chcfg_s *cfg);
* Returned Value:
* None
*
******************************************************************************/
****************************************************************************/
void pic32mz_dma_free(DMA_HANDLE handle);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_chcfg
*
* Description:
@ -243,33 +244,33 @@ void pic32mz_dma_free(DMA_HANDLE handle);
* This config can be done during alloc, however if reconfig is needed,
* this functions should be used.
*
******************************************************************************/
****************************************************************************/
int pic32mz_dma_chcfg(DMA_HANDLE handle,
FAR const struct pic32mz_dma_chcfg_s *cfg);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_xfrsetup
*
* Description:
* Configure DMA for one transfer.
*
******************************************************************************/
****************************************************************************/
int pic32mz_dma_xfrsetup(DMA_HANDLE handle,
FAR const struct pic32mz_dma_xfrcfg_s *cfg);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_start
*
* Description:
* Start the DMA transfer
*
******************************************************************************/
****************************************************************************/
int pic32mz_dma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_stop
*
* Description:
@ -278,17 +279,17 @@ int pic32mz_dma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg);
* and pic32mz_dma_xfrsetup() must be called before pic32mz_dma_start()
* can be called again.
*
******************************************************************************/
****************************************************************************/
void pic32mz_dma_stop(DMA_HANDLE handle);
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_sample
*
* Description:
* Sample DMA register contents
*
******************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void pic32mz_dma_sample(DMA_HANDLE handle, struct pic32mz_dmaregs_s *regs);
@ -296,17 +297,18 @@ void pic32mz_dma_sample(DMA_HANDLE handle, struct pic32mz_dmaregs_s *regs);
# define pic32mz_dma_sample(handle,regs)
#endif
/*******************************************************************************
/****************************************************************************
* Name: pic32mz_dma_dump
*
* Description:
* Dump previously sampled DMA register contents
*
******************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void pic32mz_dma_dump(DMA_HANDLE handle, const struct pic32mz_dmaregs_s *regs,
const char *msg);
void pic32mz_dma_dump(DMA_HANDLE handle,
const struct pic32mz_dmaregs_s *regs,
const char *msg);
#else
# define pic32mz_dma_dump(handle,regs,msg)
#endif

86
arch/mips/src/pic32mz/pic32mz_excptmacros.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_excptmacros.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_EXCPTMACROS_H
#define __ARCH_MIPS_SRC_PIC32MZ_EXCPTMACROS_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -32,13 +32,13 @@
#ifdef __ASSEMBLY__
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Symbols
********************************************************************************************/
****************************************************************************/
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.global g_intstackbase
@ -47,45 +47,48 @@
#endif
#endif
/********************************************************************************************
/****************************************************************************
* Assembly Language Macros
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* General Usage Example:
*
* my_exception:
* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
* move a0, sp - Pass register save structure as the parameter 1
* USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack
* jal handler - Handle the exception IN=old regs OUT=new regs
* di - Disable interrupts
* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
* EXCPT_PROLOGUE t0 - Save registers on stack, enable nested interrupts
* move a0, sp - Pass register save structure as the parameter 1
* USE_INTSTACK t0, t1, t2, t3 - Switch to the interrupt stack
* jal handler - Handle the exception IN=old regs OUT=new regs
* di - Disable interrupts
* RESTORE_STACK t0, t1 - Undo the operations of USE_STACK
* EXCPT_EPILOGUE v0 - Return to the context returned by handler()
*
********************************************************************************************/
/********************************************************************************************
****************************************************************************/
/****************************************************************************
* Name: EXCPT_PROLOGUE
*
* Description:
* Provides the "prologue" logic that should appear at the beginning of every exception
* handler.
* Provides the "prologue" logic that should appear at the beginning of
* every exception handler.
*
* On Entry:
* sp - Points to the top of the stack
* tmp - Is a register the can be modified for scratch usage (after it has been saved)
* k0 and k1 - Since we are in an exception handler, these are available for use
* tmp - Is a register the can be modified for scratch usage
* (after it has been saved)
* k0 and k1 - Since we are in an exception handler, these are available
* for use
*
* At completion:
* Register state is saved on the stack; All registers are available for usage except sp
* and k1:
* Register state is saved on the stack; All registers are available for
* usage except sp and k1:
*
* - sp points the beginning of the register save area
* - k1 holds the value of the STATUS register
*
* The following registers are modified: k0, k1, sp, a0
*
********************************************************************************************/
****************************************************************************/
.macro EXCPT_PROLOGUE, tmp
.set noat
@ -226,30 +229,32 @@
sw ra, REG_RA(sp)
/* $29 = sp: The value of the stack pointer on return from the exception. a0 is
* used as a temporary
/* $29 = sp: The value of the stack pointer on return from the exception.
* a0 is used as a temporary
*/
addiu \tmp, sp, XCPTCONTEXT_SIZE
sw \tmp, REG_SP(sp)
.endm
/********************************************************************************************
/****************************************************************************
* Name: EXCPT_EPILOGUE
*
* Description:
* Provides the "epilogue" logic that should appear at the end of every exception handler.
* Provides the "epilogue" logic that should appear at the end of every
* exception handler.
*
* On input:
* regs - points to the register save structure. NOTE: This *may not* be an address
* lying in a stack! It might be an address in a TCB!
* regs - points to the register save structure.
* NOTE: This *may not* be an address lying in a stack!
* It might be an address in a TCB!
* Interrupts are disabled (via 'di')
*
* On completion:
* All registers restored
* eret is executed to return from the exception
*
********************************************************************************************/
****************************************************************************/
.macro EXCPT_EPILOGUE, regs
.set noat
@ -345,7 +350,7 @@
nop
.endm
/********************************************************************************************
/****************************************************************************
* Name: USE_INTSTACK
*
* Description:
@ -361,7 +366,7 @@
* interrupt stack and sp points to the interrupt stack.
* The values of tmp1, tmp2, tmp3, and sp have been altered
*
********************************************************************************************/
****************************************************************************/
.macro USE_INTSTACK, tmp1, tmp2, tmp3, tmp4
@ -397,12 +402,13 @@
#endif
.endm
/********************************************************************************************
/****************************************************************************
* Name: RESTORE_STACK
*
* Description:
* Restore the user stack. Not really.. actually only decrements the nesting level. We
* always get the new stack pointer for the register save array.
* Restore the user stack. Not really.. actually only decrements the
* nesting level. We always get the new stack pointer for the register
* save array.
*
* On Entry:
* tmp1 and tmp2 are registers that can be used temporarily.
@ -412,7 +418,7 @@
* Current nesting level is decremented
* The values of tmp1 and tmp2 have been altered
*
********************************************************************************************/
****************************************************************************/
.macro RESTORE_STACK, tmp1, tmp2

77
arch/mips/src/pic32mz/pic32mz_gpio.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_GPIO_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
@ -36,9 +36,10 @@
#include <nuttx/irq.h>
#include <arch/pic32mz/irq.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO settings used in the configport, readport, writeport, etc.
*
* General encoding:
@ -63,6 +64,7 @@
# define GPIO_MEDIUM (1 << GPIO_SR_SHIFT) /* 01: Enabled and set to medium */
# define GPIO_SLOW (2 << GPIO_SR_SHIFT) /* 10: Enabled and set to slow */
# define GPIO_SLOWEST (3 << GPIO_SR_SHIFT) /* 11: Enabled and set to slowest */
#define GPIO_SR_CON0_SHIFT (0) /* Bit 0: SRCON0x */
#define GPIO_SR_CON0_MASK (1 << GPIO_SR_CON0_SHIFT)
#define GPIO_SR_CON1_SHIFT (1) /* Bit 1: SRCON1x */
@ -156,17 +158,17 @@
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
typedef uint32_t pinset_t;
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@ -184,53 +186,53 @@ extern "C"
EXTERN const uintptr_t g_gpiobase[CHIP_NPORTS];
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: pic32mz_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin (the interrupt
* will be configured when pic32mz_attach() is called).
* Configure a GPIO pin based on bit-encoded description of the pin (the
* interrupt will be configured when pic32mz_attach() is called).
*
* Returned Value:
* OK on success; negated errno on failure.
*
************************************************************************************/
****************************************************************************/
int pic32mz_configgpio(pinset_t cfgset);
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
void pic32mz_gpiowrite(pinset_t pinset, bool value);
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
************************************************************************************/
****************************************************************************/
bool pic32mz_gpioread(pinset_t pinset);
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpioirqinitialize
*
* Description:
* Initialize logic to support a GPIO change notification interrupts. This
* function is called internally by the system on power up and should not be
* called again.
* function is called internally by the system on power up and should not
* be called again.
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PIC32MZ_GPIOIRQ
void pic32mz_gpioirqinitialize(void);
@ -238,18 +240,19 @@ void pic32mz_gpioirqinitialize(void);
# define pic32mz_gpioirqinitialize()
#endif
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpioattach
*
* Description:
* Attach an interrupt service routine to a GPIO interrupt. This will also
* reconfigure the pin as an interrupting input. The change notification number is
* associated with all interrupt-capable GPIO pins. The association could,
* however, differ from part to part and must be provided by the caller.
* reconfigure the pin as an interrupting input. The change notification
* number is associated with all interrupt-capable GPIO pins. The
* association could, however, differ from part to part and must be
* provided by the caller.
*
* When an interrupt occurs, it is due to a change on the GPIO input pin. In that
* case, all attached handlers will be called. Each handler must maintain state
* and determine if the underlying GPIO input value changed.
* When an interrupt occurs, it is due to a change on the GPIO input pin.
* In that case, all attached handlers will be called. Each handler must
* maintain state and determine if the underlying GPIO input value changed.
*
* pinset - GPIO pin configuration
* handler - Interrupt handler (may be NULL to detach)
@ -267,13 +270,13 @@ int pic32mz_gpioattach(pinset_t pinset, xcpt_t handler, void *arg);
# define pic32mz_gpioattach(p,h,a) (0)
#endif
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PIC32MZ_GPIOIRQ
void pic32mz_gpioirqenable(pinset_t pinset);
@ -281,13 +284,13 @@ void pic32mz_gpioirqenable(pinset_t pinset);
# define pic32mz_gpioirqenable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Name: pic32mz_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PIC32MZ_GPIOIRQ
void pic32mz_gpioirqdisable(pinset_t pinset);
@ -295,13 +298,13 @@ void pic32mz_gpioirqdisable(pinset_t pinset);
# define pic32mz_gpioirqdisable(irq)
#endif
/************************************************************************************
/****************************************************************************
* Function: pic32mz_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
void pic32mz_dumpgpio(pinset_t pinset, const char *msg);

4
arch/mips/src/pic32mz/pic32mz_i2c.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_i2c.h
*
* Copyright (C) 2018 Abdelatif Guettouche. All rights reserved.
@ -31,7 +31,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_I2C_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_I2C_H

3
arch/mips/src/pic32mz/pic32mz_lowconsole.c
View File

@ -161,7 +161,8 @@ static void pic32mz_uartsetbaud(uintptr_t uart_base, uint32_t baudrate)
uint32_t brg;
unsigned int mode;
/* We want the largest value of BRG divisor possible (for the best accuracy)
/* We want the largest value of BRG divisor possible
* (for the best accuracy)
* Subject to BRG <= 65536.
*/

37
arch/mips/src/pic32mz/pic32mz_lowconsole.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_lowconsole.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_LOWCONSOLE_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_LOWCONSOLE_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
@ -31,19 +31,19 @@
#include <stdint.h>
#include <stdbool.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@ -54,19 +54,19 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: pic32mz_consoleinit
*
* Description:
* Performs low level initialization of the console UART. This UART done early so
* that the serial console is available for debugging very early in the boot
* sequence.
* Performs low level initialization of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
************************************************************************************/
****************************************************************************/
#ifdef HAVE_SERIAL_CONSOLE
void pic32mz_consoleinit(void);
@ -96,7 +96,8 @@ void pic32mz_uartreset(uintptr_t uart_base);
#ifdef HAVE_UART_DEVICE
void pic32mz_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
unsigned int parity, unsigned int nbits, bool stop2);
unsigned int parity, unsigned int nbits,
bool stop2);
#endif
#undef EXTERN

3
arch/mips/src/pic32mz/pic32mz_oneshot.c
View File

@ -63,7 +63,8 @@
****************************************************************************/
static int pic32mz_oneshot_handler(int irg_num, void * context, void *arg);
static inline int pic32mz_allocate_handler(struct pic32mz_oneshot_s *oneshot);
static inline
int pic32mz_allocate_handler(struct pic32mz_oneshot_s *oneshot);
/****************************************************************************
* Private Data

77
arch/mips/src/pic32mz/pic32mz_spi.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/mips/src/pic32mz/pic32mz_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,31 +16,31 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_SPI_H
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_SPI_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@ -51,9 +51,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
struct spi_dev_s; /* Forward reference */
@ -73,33 +73,34 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *pic32mz_spibus_initialize(int port);
/************************************************************************************
/****************************************************************************
* Name: pic32mz_spiNselect, pic32mz_spiNstatus, and pic32mz_spiNcmddata
*
* Description:
* These external functions must be provided by board-specific logic. They are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* including pic32mz_spibus_initialize()) are provided by common PIC32MZ logic. To use
* this common SPI logic on your board:
* These external functions must be provided by board-specific logic. They
* are implementations of the select, status, and cmddata methods of the
* SPI interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
* All other methods including pic32mz_spibus_initialize()) are provided by
* common PIC32MZ logic. To use this common SPI logic on your board:
*
* 1. Provide logic in pic32mz_boardinitialize() to configure SPI/SSP chip select
* pins.
* 1. Provide logic in pic32mz_boardinitialize() to configure SPI/SSP chip
* select pins.
* 2. Provide pic32mz_spiNselect() and pic32mz_spiNstatus() functions
* in your board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* pic32mz_spiNcmddata() functions in your board-specific logic. These
* functions will perform cmd/data selection operations using GPIOs in the way
* your board is configured.
* 3. Add a call to pic32mz_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by pic32mz_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* functions will perform cmd/data selection operations using GPIOs in
* the way your board is configured.
* 3. Add a call to pic32mz_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by pic32mz_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_PIC32MZ_SPI1
void pic32mz_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
@ -177,32 +178,38 @@ int pic32mz_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_PIC32MZ_SPI1
int pic32mz_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi1register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_PIC32MZ_SPI2
int pic32mz_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi2register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_PIC32MZ_SPI3
int pic32mz_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi3register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_PIC32MZ_SPI4
int pic32mz_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi4register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_PIC32MZ_SPI5
int pic32mz_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi5register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_PIC32MZ_SPI6
int pic32mz_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
int pic32mz_spi6register(FAR struct spi_dev_s *dev,
spi_mediachange_t callback,
FAR void *arg);
#endif
#endif /* CONFIG_SPI_CALLBACK */

3
arch/mips/src/pic32mz/pic32mz_timer.c
View File

@ -173,7 +173,8 @@ static void pic32mz_timer_start(FAR struct pic32mz_timer_dev_s *dev);
static void pic32mz_timer_stop(FAR struct pic32mz_timer_dev_s *dev);
static void pic32mz_timer_setperiod(FAR struct pic32mz_timer_dev_s *dev,
uint32_t period);
static uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev);
static
uint32_t pic32mz_timer_getcounter(FAR struct pic32mz_timer_dev_s *dev);
static void pic32mz_timer_setcounter(FAR struct pic32mz_timer_dev_s *dev,
uint32_t count);
static uint32_t pic32mz_timer_getfreq(FAR struct pic32mz_timer_dev_s *dev);

2
arch/mips/src/pic32mz/pic32mz_timer.h
View File

@ -113,7 +113,7 @@ struct pic32mz_timer_dev_s
};
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************