From 2954551ef6b5c24f46a9c0b20750632b0123a21b Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Thu, 21 Dec 2023 16:04:04 -0300 Subject: [PATCH] esp32/hardware/esp32_efuse.h: Update macros for registers. This commit is intended to update the EFUSE's register content and update related configs: - Remove duplicated configs from `esp32_soc.h`; - Add missing header files from APB registers; - Add missing macro definitions from EFUSE; - Update related code to use the new macros; --- arch/xtensa/src/esp32/esp32_efuse.c | 1 + arch/xtensa/src/esp32/esp32_efuse_table.c | 2 +- arch/xtensa/src/esp32/esp32_pm.c | 15 +- arch/xtensa/src/esp32/esp32_psram.c | 21 +- arch/xtensa/src/esp32/esp32_rtc.c | 1 + .../src/esp32/hardware/esp32_apb_ctrl.h | 422 +++ arch/xtensa/src/esp32/hardware/esp32_efuse.h | 2834 ++++++++--------- .../src/esp32/hardware/esp32_efuse_defs.h | 73 + arch/xtensa/src/esp32/hardware/esp32_soc.h | 90 +- 9 files changed, 1771 insertions(+), 1688 deletions(-) create mode 100644 arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h create mode 100644 arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h diff --git a/arch/xtensa/src/esp32/esp32_efuse.c b/arch/xtensa/src/esp32/esp32_efuse.c index 210097a175..12f2ddd514 100644 --- a/arch/xtensa/src/esp32/esp32_efuse.c +++ b/arch/xtensa/src/esp32/esp32_efuse.c @@ -32,6 +32,7 @@ #include "xtensa.h" #include "esp32_efuse.h" #include "esp32_clockconfig.h" +#include "hardware/esp32_apb_ctrl.h" #include "hardware/esp32_efuse.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_efuse_table.c b/arch/xtensa/src/esp32/esp32_efuse_table.c index b923099f4e..d559459b17 100644 --- a/arch/xtensa/src/esp32/esp32_efuse_table.c +++ b/arch/xtensa/src/esp32/esp32_efuse_table.c @@ -314,7 +314,7 @@ static const efuse_desc_t SDIO_TIEH[] = static const efuse_desc_t SDIO_FORCE[] = { { - 144, 1 /* EFUSE_RD_SDIO_FORCE */ + 144, 1 /* EFUSE_RD_XPD_SDIO_FORCE */ }, }; diff --git a/arch/xtensa/src/esp32/esp32_pm.c b/arch/xtensa/src/esp32/esp32_pm.c index 28abfcd220..025ae954f4 100644 --- a/arch/xtensa/src/esp32/esp32_pm.c +++ b/arch/xtensa/src/esp32/esp32_pm.c @@ -502,25 +502,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config( efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); - if (efuse_reg & EFUSE_RD_SDIO_FORCE) + if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE) { /* Get configuration from EFUSE */ result->force = 0; result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S; - result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) - >> EFUSE_RD_SDIO_TIEH_S; + result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M) + >> EFUSE_RD_XPD_SDIO_TIEH_S; if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0) { - result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) - >> EFUSE_RD_SDIO_DREFH_S; - result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) - >> EFUSE_RD_SDIO_DREFM_S; - result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) - >> EFUSE_RD_SDIO_DREFL_S; + result->drefh = (efuse_reg >> 8) & 0x3; + result->drefm = (efuse_reg >> 10) & 0x3; + result->drefl = (efuse_reg >> 12) & 0x3; } return OK; diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c index 99e1504ca1..937a5658a2 100644 --- a/arch/xtensa/src/esp32/esp32_psram.c +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -381,25 +381,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config( efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); - if (efuse_reg & EFUSE_RD_SDIO_FORCE) + if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE) { /* Get configuration from EFUSE */ result->force = 0; result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S; - result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) - >> EFUSE_RD_SDIO_TIEH_S; + result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M) + >> EFUSE_RD_XPD_SDIO_TIEH_S; if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0) { - result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) - >> EFUSE_RD_SDIO_DREFH_S; - result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) - >> EFUSE_RD_SDIO_DREFM_S; - result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) - >> EFUSE_RD_SDIO_DREFL_S; + result->drefh = (efuse_reg >> 8) & 0x3; + result->drefm = (efuse_reg >> 10) & 0x3; + result->drefl = (efuse_reg >> 12) & 0x3; } return OK; @@ -1514,8 +1511,10 @@ psram_enable(int mode, int vaddrmode) /* psram init */ 0 }; - uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, - EFUSE_RD_CHIP_VER_PKG); + uint32_t chip_ver = (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_CHIP_PACKAGE_4BIT) << 3) | + REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_CHIP_PACKAGE); uint32_t pkg_ver = chip_ver & 0x7; uint32_t spiconfig; diff --git a/arch/xtensa/src/esp32/esp32_rtc.c b/arch/xtensa/src/esp32/esp32_rtc.c index 35e87861a9..1c73282d35 100644 --- a/arch/xtensa/src/esp32/esp32_rtc.c +++ b/arch/xtensa/src/esp32/esp32_rtc.c @@ -34,6 +34,7 @@ #include "esp32_clockconfig.h" #include "esp32_rt_timer.h" +#include "hardware/esp32_apb_ctrl.h" #include "hardware/esp32_rtccntl.h" #include "hardware/esp32_rtc_io.h" #include "hardware/esp32_dport.h" diff --git a/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h b/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h new file mode 100644 index 0000000000..83ca590a32 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h @@ -0,0 +1,422 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* APB_CTRL_SYSCLK_CONF_REG register */ + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) + +/* APB_CTRL_QUICK_CLK_CHNG : RW; bitpos: [13]; default: 1; */ + +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (APB_CTRL_QUICK_CLK_CHNG_V << APB_CTRL_QUICK_CLK_CHNG_S) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x00000001 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 + +/* APB_CTRL_RST_TICK_CNT : RW; bitpos: [12]; default: 0; */ + +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (APB_CTRL_RST_TICK_CNT_V << APB_CTRL_RST_TICK_CNT_S) +#define APB_CTRL_RST_TICK_CNT_V 0x00000001 +#define APB_CTRL_RST_TICK_CNT_S 12 + +/* APB_CTRL_CLK_EN : RW; bitpos: [11]; default: 0; */ + +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (APB_CTRL_CLK_EN_V << APB_CTRL_CLK_EN_S) +#define APB_CTRL_CLK_EN_V 0x00000001 +#define APB_CTRL_CLK_EN_S 11 + +/* APB_CTRL_CLK_320M_EN : RW; bitpos: [10]; default: 0; */ + +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (APB_CTRL_CLK_320M_EN_V << APB_CTRL_CLK_320M_EN_S) +#define APB_CTRL_CLK_320M_EN_V 0x00000001 +#define APB_CTRL_CLK_320M_EN_S 10 + +/* APB_CTRL_PRE_DIV_CNT : RW; bitpos: [9:0]; default: 0; */ + +#define APB_CTRL_PRE_DIV_CNT 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_M (APB_CTRL_PRE_DIV_CNT_V << APB_CTRL_PRE_DIV_CNT_S) +#define APB_CTRL_PRE_DIV_CNT_V 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_S 0 + +/* APB_CTRL_XTAL_TICK_CONF_REG register */ + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) + +/* APB_CTRL_XTAL_TICK_NUM : RW; bitpos: [7:0]; default: 39; */ + +#define APB_CTRL_XTAL_TICK_NUM 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_M (APB_CTRL_XTAL_TICK_NUM_V << APB_CTRL_XTAL_TICK_NUM_S) +#define APB_CTRL_XTAL_TICK_NUM_V 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +/* APB_CTRL_PLL_TICK_CONF_REG register */ + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) + +/* APB_CTRL_PLL_TICK_NUM : RW; bitpos: [7:0]; default: 79; */ + +#define APB_CTRL_PLL_TICK_NUM 0x000000ff +#define APB_CTRL_PLL_TICK_NUM_M (APB_CTRL_PLL_TICK_NUM_V << APB_CTRL_PLL_TICK_NUM_S) +#define APB_CTRL_PLL_TICK_NUM_V 0x000000ff +#define APB_CTRL_PLL_TICK_NUM_S 0 + +/* APB_CTRL_CK8M_TICK_CONF_REG register */ + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xc) + +/* APB_CTRL_CK8M_TICK_NUM : RW; bitpos: [7:0]; default: 11; */ + +#define APB_CTRL_CK8M_TICK_NUM 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_M (APB_CTRL_CK8M_TICK_NUM_V << APB_CTRL_CK8M_TICK_NUM_S) +#define APB_CTRL_CK8M_TICK_NUM_V 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +/* APB_CTRL_APB_SARADC_CTRL_REG register */ + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) + +/* APB_CTRL_SARADC_DATA_TO_I2S : RW; bitpos: [26]; default: 0; + * 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from + * GPIO matrix + */ + +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (APB_CTRL_SARADC_DATA_TO_I2S_V << APB_CTRL_SARADC_DATA_TO_I2S_S) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x00000001 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 + +/* APB_CTRL_SARADC_DATA_SAR_SEL : RW; bitpos: [25]; default: 0; + * 1: sar_sel will be coded by the MSB of the 16-bit output data in this + * case the resolution should not be larger than 11 bits. + */ + +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (APB_CTRL_SARADC_DATA_SAR_SEL_V << APB_CTRL_SARADC_DATA_SAR_SEL_S) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x00000001 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 + +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : RW; bitpos: [24]; default: 0; + * clear the pointer of pattern table for DIG ADC2 CTRL + */ + +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 + +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : RW; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x00000001 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 + +/* APB_CTRL_SARADC_SAR2_PATT_LEN : RW; bitpos: [22:19]; default: 15; + * 0 ~ 15 means length 1 ~ 16 + */ + +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000f +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M (APB_CTRL_SARADC_SAR2_PATT_LEN_V << APB_CTRL_SARADC_SAR2_PATT_LEN_S) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0x0000000f +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 + +/* APB_CTRL_SARADC_SAR1_PATT_LEN : RW; bitpos: [18:15]; default: 15; + * 0 ~ 15 means length 1 ~ 16 + */ + +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000f +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M (APB_CTRL_SARADC_SAR1_PATT_LEN_V << APB_CTRL_SARADC_SAR1_PATT_LEN_S) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0x0000000f +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 + +/* APB_CTRL_SARADC_SAR_CLK_DIV : RW; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000ff +#define APB_CTRL_SARADC_SAR_CLK_DIV_M (APB_CTRL_SARADC_SAR_CLK_DIV_V << APB_CTRL_SARADC_SAR_CLK_DIV_S) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0x000000ff +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 + +/* APB_CTRL_SARADC_SAR_CLK_GATED : RW; bitpos: [6]; default: 1; */ + +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (APB_CTRL_SARADC_SAR_CLK_GATED_V << APB_CTRL_SARADC_SAR_CLK_GATED_S) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x00000001 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 + +/* APB_CTRL_SARADC_SAR_SEL : RW; bitpos: [5]; default: 0; + * 0: SAR1 1: SAR2 only work for single SAR mode + */ + +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (APB_CTRL_SARADC_SAR_SEL_V << APB_CTRL_SARADC_SAR_SEL_S) +#define APB_CTRL_SARADC_SAR_SEL_V 0x00000001 +#define APB_CTRL_SARADC_SAR_SEL_S 5 + +/* APB_CTRL_SARADC_WORK_MODE : RW; bitpos: [4:3]; default: 0; + * 0: single mode 1: double mode 2: alternate mode + */ + +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M (APB_CTRL_SARADC_WORK_MODE_V << APB_CTRL_SARADC_WORK_MODE_S) +#define APB_CTRL_SARADC_WORK_MODE_V 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_S 3 + +/* APB_CTRL_SARADC_SAR2_MUX : RW; bitpos: [2]; default: 0; + * 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by + * PWDET CTRL + */ + +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (APB_CTRL_SARADC_SAR2_MUX_V << APB_CTRL_SARADC_SAR2_MUX_S) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 + +/* APB_CTRL_SARADC_START : RW; bitpos: [1]; default: 0; */ + +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (APB_CTRL_SARADC_START_V << APB_CTRL_SARADC_START_S) +#define APB_CTRL_SARADC_START_V 0x00000001 +#define APB_CTRL_SARADC_START_S 1 + +/* APB_CTRL_SARADC_START_FORCE : RW; bitpos: [0]; default: 0; */ + +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (APB_CTRL_SARADC_START_FORCE_V << APB_CTRL_SARADC_START_FORCE_S) +#define APB_CTRL_SARADC_START_FORCE_V 0x00000001 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +/* APB_CTRL_APB_SARADC_CTRL2_REG register */ + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) + +/* APB_CTRL_SARADC_SAR2_INV : RW; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted otherwise not + */ + +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (APB_CTRL_SARADC_SAR2_INV_V << APB_CTRL_SARADC_SAR2_INV_S) +#define APB_CTRL_SARADC_SAR2_INV_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_INV_S 10 + +/* APB_CTRL_SARADC_SAR1_INV : RW; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted otherwise not + */ + +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (APB_CTRL_SARADC_SAR1_INV_V << APB_CTRL_SARADC_SAR1_INV_S) +#define APB_CTRL_SARADC_SAR1_INV_V 0x00000001 +#define APB_CTRL_SARADC_SAR1_INV_S 9 + +/* APB_CTRL_SARADC_MAX_MEAS_NUM : RW; bitpos: [8:1]; default: 255; + * max conversion number + */ + +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000ff +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M (APB_CTRL_SARADC_MAX_MEAS_NUM_V << APB_CTRL_SARADC_MAX_MEAS_NUM_S) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0x000000ff +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 + +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : RW; bitpos: [0]; default: 0; */ + +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (APB_CTRL_SARADC_MEAS_NUM_LIMIT_V << APB_CTRL_SARADC_MEAS_NUM_LIMIT_S) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x00000001 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +/* APB_CTRL_APB_SARADC_FSM_REG register */ + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) + +/* APB_CTRL_SARADC_SAMPLE_CYCLE : RW; bitpos: [31:24]; default: 2; + * sample cycles + */ + +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000ff +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M (APB_CTRL_SARADC_SAMPLE_CYCLE_V << APB_CTRL_SARADC_SAMPLE_CYCLE_S) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0x000000ff +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 + +/* APB_CTRL_SARADC_START_WAIT : RW; bitpos: [23:16]; default: 8; */ + +#define APB_CTRL_SARADC_START_WAIT 0x000000ff +#define APB_CTRL_SARADC_START_WAIT_M (APB_CTRL_SARADC_START_WAIT_V << APB_CTRL_SARADC_START_WAIT_S) +#define APB_CTRL_SARADC_START_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_START_WAIT_S 16 + +/* APB_CTRL_SARADC_STANDBY_WAIT : RW; bitpos: [15:8]; default: 255; */ + +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000ff +#define APB_CTRL_SARADC_STANDBY_WAIT_M (APB_CTRL_SARADC_STANDBY_WAIT_V << APB_CTRL_SARADC_STANDBY_WAIT_S) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 + +/* APB_CTRL_SARADC_RSTB_WAIT : RW; bitpos: [7:0]; default: 8; */ + +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000ff +#define APB_CTRL_SARADC_RSTB_WAIT_M (APB_CTRL_SARADC_RSTB_WAIT_V << APB_CTRL_SARADC_RSTB_WAIT_S) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1c) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M (APB_CTRL_SARADC_SAR1_PATT_TAB1_V << APB_CTRL_SARADC_SAR1_PATT_TAB1_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M (APB_CTRL_SARADC_SAR1_PATT_TAB2_V << APB_CTRL_SARADC_SAR1_PATT_TAB2_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135; + * Item 8 ~ 11 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M (APB_CTRL_SARADC_SAR1_PATT_TAB3_V << APB_CTRL_SARADC_SAR1_PATT_TAB3_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135; + * Item 12 ~ 15 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M (APB_CTRL_SARADC_SAR1_PATT_TAB4_V << APB_CTRL_SARADC_SAR1_PATT_TAB4_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2c) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135; + * item 0 ~ 3 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M (APB_CTRL_SARADC_SAR2_PATT_TAB1_V << APB_CTRL_SARADC_SAR2_PATT_TAB1_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135; + * Item 4 ~ 7 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M (APB_CTRL_SARADC_SAR2_PATT_TAB2_V << APB_CTRL_SARADC_SAR2_PATT_TAB2_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135; + * Item 8 ~ 11 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M (APB_CTRL_SARADC_SAR2_PATT_TAB3_V << APB_CTRL_SARADC_SAR2_PATT_TAB3_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135; + * Item 12 ~ 15 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M (APB_CTRL_SARADC_SAR2_PATT_TAB4_V << APB_CTRL_SARADC_SAR2_PATT_TAB4_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +/* APB_CTRL_APLL_TICK_CONF_REG register */ + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3c) + +/* APB_CTRL_APLL_TICK_NUM : RW; bitpos: [7:0]; default: 99; */ + +#define APB_CTRL_APLL_TICK_NUM 0x000000ff +#define APB_CTRL_APLL_TICK_NUM_M (APB_CTRL_APLL_TICK_NUM_V << APB_CTRL_APLL_TICK_NUM_S) +#define APB_CTRL_APLL_TICK_NUM_V 0x000000ff +#define APB_CTRL_APLL_TICK_NUM_S 0 + +/* APB_CTRL_DATE_REG register */ + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7c) + +/* APB_CTRL_DATE : RW; bitpos: [31:0]; default: 369369088; */ + +#define APB_CTRL_DATE 0xffffffff +#define APB_CTRL_DATE_M (APB_CTRL_DATE_V << APB_CTRL_DATE_S) +#define APB_CTRL_DATE_V 0xffffffff +#define APB_CTRL_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_efuse.h b/arch/xtensa/src/esp32/hardware/esp32_efuse.h index 0364ffb270..81d2859784 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_efuse.h +++ b/arch/xtensa/src/esp32/hardware/esp32_efuse.h @@ -26,1802 +26,1478 @@ ****************************************************************************/ #include "esp32_soc.h" +#include "esp32_efuse_defs.h" -#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ -/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; - * Description: read for flash_crypt_cnt - */ +/* EFUSE_BLK0_RDATA0_REG register */ + +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_RESERVED_0_28 : R; bitpos: [31:28]; default: 0; */ + +#define EFUSE_RESERVED_0_28 0x0000000f +#define EFUSE_RESERVED_0_28_M (EFUSE_RESERVED_0_28_V << EFUSE_RESERVED_0_28_S) +#define EFUSE_RESERVED_0_28_V 0x0000000f +#define EFUSE_RESERVED_0_28_S 28 + +/* EFUSE_RD_UART_DOWNLOAD_DIS : R; bitpos: [27]; default: 0; */ + +#define EFUSE_RD_UART_DOWNLOAD_DIS (BIT(27)) +#define EFUSE_RD_UART_DOWNLOAD_DIS_M (EFUSE_RD_UART_DOWNLOAD_DIS_V << EFUSE_RD_UART_DOWNLOAD_DIS_S) +#define EFUSE_RD_UART_DOWNLOAD_DIS_V 0x00000001 +#define EFUSE_RD_UART_DOWNLOAD_DIS_S 27 + +/* EFUSE_RD_FLASH_CRYPT_CNT : R; bitpos: [26:20]; default: 0; */ #define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007f -#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V) << \ - (EFUSE_RD_FLASH_CRYPT_CNT_S)) -#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7f +#define EFUSE_RD_FLASH_CRYPT_CNT_M (EFUSE_RD_FLASH_CRYPT_CNT_V << EFUSE_RD_FLASH_CRYPT_CNT_S) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x0000007f #define EFUSE_RD_FLASH_CRYPT_CNT_S 20 -/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; - * Description: read for efuse_rd_disable - */ +/* EFUSE_RD_EFUSE_RD_DIS : R; bitpos: [19:16]; default: 0; */ -#define EFUSE_RD_EFUSE_RD_DIS 0x0000000f -#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V) << \ - (EFUSE_RD_EFUSE_RD_DIS_S)) -#define EFUSE_RD_EFUSE_RD_DIS_V 0xf -#define EFUSE_RD_EFUSE_RD_DIS_S 16 +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_EFUSE_RD_DIS_M (EFUSE_RD_EFUSE_RD_DIS_V << EFUSE_RD_EFUSE_RD_DIS_S) +#define EFUSE_RD_EFUSE_RD_DIS_V 0x0000000f +#define EFUSE_RD_EFUSE_RD_DIS_S 16 -/* Read disable bits for efuse blocks 1-3 */ +/* EFUSE_RD_EFUSE_WR_DIS : R; bitpos: [15:0]; default: 0; */ -#define EFUSE_RD_DIS_BLK1 (1 << 16) -#define EFUSE_RD_DIS_BLK2 (1 << 17) -#define EFUSE_RD_DIS_BLK3 (1 << 18) +#define EFUSE_RD_EFUSE_WR_DIS 0x0000ffff +#define EFUSE_RD_EFUSE_WR_DIS_M (EFUSE_RD_EFUSE_WR_DIS_V << EFUSE_RD_EFUSE_WR_DIS_S) +#define EFUSE_RD_EFUSE_WR_DIS_V 0x0000ffff +#define EFUSE_RD_EFUSE_WR_DIS_S 0 -/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS - * in efuse block 0 - */ +/* EFUSE_BLK0_RDATA1_REG register */ -#define EFUSE_RD_DIS_BLK0_PARTIAL (1 << 19) +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x4) -/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; - * Description: read for efuse_wr_disable - */ +/* EFUSE_RD_MAC : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_RD_EFUSE_WR_DIS 0x0000ffff -#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V) << \ - (EFUSE_RD_EFUSE_WR_DIS_S)) -#define EFUSE_RD_EFUSE_WR_DIS_V 0xffff -#define EFUSE_RD_EFUSE_WR_DIS_S 0 +#define EFUSE_RD_MAC 0xffffffff +#define EFUSE_RD_MAC_M (EFUSE_RD_MAC_V << EFUSE_RD_MAC_S) +#define EFUSE_RD_MAC_V 0xffffffff +#define EFUSE_RD_MAC_S 0 -/* Write disable bits */ +/* EFUSE_BLK0_RDATA2_REG register */ -#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */ -#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2) -#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */ -#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */ -#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */ -#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */ -#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */ -#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */ -#define EFUSE_WR_DIS_FL_CRYPT_COD_SCH (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ -#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */ -#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */ -#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */ -#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x8) -#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) +/* EFUSE_RD_RESERVE_0_88 : RW; bitpos: [31:24]; default: 0; */ -/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; - * Description: read for low 32bit WIFI_MAC_Address - */ +#define EFUSE_RD_RESERVE_0_88 0x000000ff +#define EFUSE_RD_RESERVE_0_88_M (EFUSE_RD_RESERVE_0_88_V << EFUSE_RD_RESERVE_0_88_S) +#define EFUSE_RD_RESERVE_0_88_V 0x000000ff +#define EFUSE_RD_RESERVE_0_88_S 24 -#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xffffffff -#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V) << \ - (EFUSE_RD_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xffffffff -#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 +/* EFUSE_RD_MAC_CRC : R; bitpos: [23:16]; default: 0; */ -#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) +#define EFUSE_RD_MAC_CRC 0x000000ff +#define EFUSE_RD_MAC_CRC_M (EFUSE_RD_MAC_CRC_V << EFUSE_RD_MAC_CRC_S) +#define EFUSE_RD_MAC_CRC_V 0x000000ff +#define EFUSE_RD_MAC_CRC_S 16 -/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; - * Description: read for high 24bit WIFI_MAC_Address - */ +/* EFUSE_RD_MAC_1 : R; bitpos: [15:0]; default: 0; */ -#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00ffffff -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V) << \ - (EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xffffff -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 +#define EFUSE_RD_MAC_1 0x0000ffff +#define EFUSE_RD_MAC_1_M (EFUSE_RD_MAC_1_V << EFUSE_RD_MAC_1_S) +#define EFUSE_RD_MAC_1_V 0x0000ffff +#define EFUSE_RD_MAC_1_S 0 -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) +/* EFUSE_BLK0_RDATA3_REG register */ -/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: bit is set to 1 for rev1 silicon - */ +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0xc) -#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V) << \ - (EFUSE_RD_CHIP_VER_REV1_S)) -#define EFUSE_RD_CHIP_VER_REV1_V 0x1 -#define EFUSE_RD_CHIP_VER_REV1_S 15 +/* EFUSE_RD_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; */ -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; - * Description: If set, this bit indicates that BLOCK3[143:96] is reserved - * for internal use - */ +#define EFUSE_RD_RESERVE_0_112 0x0000ffff +#define EFUSE_RD_RESERVE_0_112_M (EFUSE_RD_RESERVE_0_112_V << EFUSE_RD_RESERVE_0_112_S) +#define EFUSE_RD_RESERVE_0_112_V 0x0000ffff +#define EFUSE_RD_RESERVE_0_112_S 16 -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << \ - (EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 +/* EFUSE_RD_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; */ -/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; - * Description: If set, the ESP32's maximum CPU frequency has been rated - */ +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M (EFUSE_RD_CHIP_VER_REV1_V << EFUSE_RD_CHIP_VER_REV1_S) +#define EFUSE_RD_CHIP_VER_REV1_V 0x00000001 +#define EFUSE_RD_CHIP_VER_REV1_S 15 + +/* EFUSE_RD_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; */ + +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M (EFUSE_RD_BLK3_PART_RESERVE_V << EFUSE_RD_BLK3_PART_RESERVE_S) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x00000001 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 + +/* EFUSE_RD_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; */ #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V) << \ - (EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M (EFUSE_RD_CHIP_CPU_FREQ_RATED_V << EFUSE_RD_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x00000001 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 -/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; - * Description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's - * max CPU frequency is rated for 160MHz. 240MHz otherwise - */ +/* EFUSE_RD_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; */ -#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V) << \ - (EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M (EFUSE_RD_CHIP_CPU_FREQ_LOW_V << EFUSE_RD_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x00000001 +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 -/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; - * Description: chip package - */ +/* EFUSE_RD_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; */ -#define EFUSE_RD_CHIP_VER_PKG 0x00000007 -#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V) << \ - (EFUSE_RD_CHIP_VER_PKG_S)) -#define EFUSE_RD_CHIP_VER_PKG_V 0x7 -#define EFUSE_RD_CHIP_VER_PKG_S 9 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_PACKAGE 0x00000007 +#define EFUSE_RD_CHIP_PACKAGE_M (EFUSE_RD_CHIP_PACKAGE_V << EFUSE_RD_CHIP_PACKAGE_S) +#define EFUSE_RD_CHIP_PACKAGE_V 0x00000007 +#define EFUSE_RD_CHIP_PACKAGE_S 9 -/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; - * Description: read for SPI_pad_config_hd - */ +/* EFUSE_RD_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; */ -#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M (EFUSE_RD_SPI_PAD_CONFIG_HD_V << EFUSE_RD_SPI_PAD_CONFIG_HD_S) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 -/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_RD_DIS_CACHE : R; bitpos: [3]; default: 0; */ -#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 +#define EFUSE_RD_DIS_CACHE (BIT(3)) +#define EFUSE_RD_DIS_CACHE_M (EFUSE_RD_DIS_CACHE_V << EFUSE_RD_DIS_CACHE_S) +#define EFUSE_RD_DIS_CACHE_V 0x00000001 +#define EFUSE_RD_DIS_CACHE_S 3 -/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_RD_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; */ -#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 -#define EFUSE_RD_CHIP_VER_32PAD_S 2 +#define EFUSE_RD_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_M (EFUSE_RD_CHIP_PACKAGE_4BIT_V << EFUSE_RD_CHIP_PACKAGE_4BIT_S) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_V 0x00000001 +#define EFUSE_RD_CHIP_PACKAGE_4BIT_S 2 -/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_RD_DISABLE_BT : R; bitpos: [1]; default: 0; */ -#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 +#define EFUSE_RD_DISABLE_BT (BIT(1)) +#define EFUSE_RD_DISABLE_BT_M (EFUSE_RD_DISABLE_BT_V << EFUSE_RD_DISABLE_BT_S) +#define EFUSE_RD_DISABLE_BT_V 0x00000001 +#define EFUSE_RD_DISABLE_BT_S 1 -/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_RD_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; */ -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 +#define EFUSE_RD_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_RD_DISABLE_APP_CPU_M (EFUSE_RD_DISABLE_APP_CPU_V << EFUSE_RD_DISABLE_APP_CPU_S) +#define EFUSE_RD_DISABLE_APP_CPU_V 0x00000001 +#define EFUSE_RD_DISABLE_APP_CPU_S 0 -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) +/* EFUSE_BLK0_RDATA4_REG register */ -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; - * Description: read for sdio_force - */ +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x10) -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 +/* EFUSE_RD_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; */ -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; - * Description: read for SDIO_TIEH - */ +#define EFUSE_RD_RESERVE_0_145 0x00007fff +#define EFUSE_RD_RESERVE_0_145_M (EFUSE_RD_RESERVE_0_145_V << EFUSE_RD_RESERVE_0_145_S) +#define EFUSE_RD_RESERVE_0_145_V 0x00007fff +#define EFUSE_RD_RESERVE_0_145_S 17 -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 +/* EFUSE_RD_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; */ -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; - * Description: read for XPD_SDIO_REG - */ +#define EFUSE_RD_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_XPD_SDIO_FORCE_M (EFUSE_RD_XPD_SDIO_FORCE_V << EFUSE_RD_XPD_SDIO_FORCE_S) +#define EFUSE_RD_XPD_SDIO_FORCE_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_FORCE_S 16 -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 +/* EFUSE_RD_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; */ -/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; - * Description: True ADC reference voltage - */ +#define EFUSE_RD_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_XPD_SDIO_TIEH_M (EFUSE_RD_XPD_SDIO_TIEH_V << EFUSE_RD_XPD_SDIO_TIEH_S) +#define EFUSE_RD_XPD_SDIO_TIEH_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_TIEH_S 15 -#define EFUSE_RD_ADC_VREF 0x0000001f -#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V) << \ - (EFUSE_RD_ADC_VREF_S)) -#define EFUSE_RD_ADC_VREF_V 0x1f -#define EFUSE_RD_ADC_VREF_S 8 +/* EFUSE_RD_XPD_SDIO_REG : R; bitpos: [14]; default: 0; */ -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (EFUSE_RD_XPD_SDIO_REG_V << EFUSE_RD_XPD_SDIO_REG_S) +#define EFUSE_RD_XPD_SDIO_REG_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_REG_S 14 -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; - * Description: - */ +/* EFUSE_RD_RESERVE_0_141 : RW; bitpos: [13]; default: 0; */ -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << \ - (EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 +#define EFUSE_RD_RESERVE_0_141 (BIT(13)) +#define EFUSE_RD_RESERVE_0_141_M (EFUSE_RD_RESERVE_0_141_V << EFUSE_RD_RESERVE_0_141_S) +#define EFUSE_RD_RESERVE_0_141_V 0x00000001 +#define EFUSE_RD_RESERVE_0_141_S 13 -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; - * Description: - */ +/* EFUSE_RD_ADC_VREF : RW; bitpos: [12:8]; default: 0; */ -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << \ - (EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 +#define EFUSE_RD_ADC_VREF 0x0000001f +#define EFUSE_RD_ADC_VREF_M (EFUSE_RD_ADC_VREF_V << EFUSE_RD_ADC_VREF_S) +#define EFUSE_RD_ADC_VREF_V 0x0000001f +#define EFUSE_RD_ADC_VREF_S 8 -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; - * Description: - */ +/* EFUSE_RD_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; */ -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << \ - (EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 +#define EFUSE_RD_CLK8M_FREQ 0x000000ff +#define EFUSE_RD_CLK8M_FREQ_M (EFUSE_RD_CLK8M_FREQ_V << EFUSE_RD_CLK8M_FREQ_S) +#define EFUSE_RD_CLK8M_FREQ_V 0x000000ff +#define EFUSE_RD_CLK8M_FREQ_S 0 -/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; - * Description: - */ +/* EFUSE_BLK0_RDATA5_REG register */ -#define EFUSE_RD_CK8M_FREQ 0x000000ff -#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V) << \ - (EFUSE_RD_CK8M_FREQ_S)) -#define EFUSE_RD_CK8M_FREQ_V 0xff -#define EFUSE_RD_CK8M_FREQ_S 0 +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x14) -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) - -/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; - * Description: read for flash_crypt_config - */ +/* EFUSE_RD_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; */ #define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000f -#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V) << \ - (EFUSE_RD_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xf +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M (EFUSE_RD_FLASH_CRYPT_CONFIG_V << EFUSE_RD_FLASH_CRYPT_CONFIG_S) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0x0000000f #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 -/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; - * Description: This field stores the difference between the digital - * regulator voltage at level6 and 1.2 V. (RO) - * BIT[27] is the sign bit, 0: + , 1: - - * BIT[26:24] is the difference value, unit: 0.017V - * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + - * BIT[26:24] * 0.017 - */ +/* EFUSE_RD_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; */ -#define EFUSE_RD_DIG_VOL_L6 0x0f -#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ - (EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_RD_DIG_VOL_L6_V 0x0f -#define EFUSE_RD_DIG_VOL_L6_S 24 +#define EFUSE_RD_RESERVE_0_186 0x00000003 +#define EFUSE_RD_RESERVE_0_186_M (EFUSE_RD_RESERVE_0_186_V << EFUSE_RD_RESERVE_0_186_S) +#define EFUSE_RD_RESERVE_0_186_V 0x00000003 +#define EFUSE_RD_RESERVE_0_186_S 26 -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] - * Description: This field stores the voltage level for CPU to run at 240 MHz - * or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; - * 0x1: level 6; - * 0x2: level 5; - * 0x3: level 4. (RO) - */ +/* EFUSE_RD_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ - (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 +#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003 +#define EFUSE_RD_WAFER_VERSION_MINOR_M (EFUSE_RD_WAFER_VERSION_MINOR_V << EFUSE_RD_WAFER_VERSION_MINOR_S) +#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x00000003 +#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 -/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; - * Deprecated - */ +/* EFUSE_RD_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; */ -#define EFUSE_RD_INST_CONFIG 0x000000ff /* Deprecated */ -#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V) << \ - (EFUSE_RD_INST_CONFIG_S)) -#define EFUSE_RD_INST_CONFIG_V 0xff /* Deprecated */ -#define EFUSE_RD_INST_CONFIG_S 20 /* Deprecated */ +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x00000003 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M (EFUSE_RD_VOL_LEVEL_HP_INV_V << EFUSE_RD_VOL_LEVEL_HP_INV_S) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x00000003 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 -/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; - * Description: read for SPI_pad_config_cs0 - */ +/* EFUSE_RD_RESERVE_0_181 : RW; bitpos: [21]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_181 (BIT(21)) +#define EFUSE_RD_RESERVE_0_181_M (EFUSE_RD_RESERVE_0_181_V << EFUSE_RD_RESERVE_0_181_S) +#define EFUSE_RD_RESERVE_0_181_V 0x00000001 +#define EFUSE_RD_RESERVE_0_181_S 21 + +/* EFUSE_RD_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ + +#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_RD_CHIP_VER_REV2_M (EFUSE_RD_CHIP_VER_REV2_V << EFUSE_RD_CHIP_VER_REV2_S) +#define EFUSE_RD_CHIP_VER_REV2_V 0x00000001 +#define EFUSE_RD_CHIP_VER_REV2_S 20 + +/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; */ #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M (EFUSE_RD_SPI_PAD_CONFIG_CS0_V << EFUSE_RD_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x0000001f #define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 -/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; - * Description: read for SPI_pad_config_d - */ +/* EFUSE_RD_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; */ -#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_D_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_D_M (EFUSE_RD_SPI_PAD_CONFIG_D_V << EFUSE_RD_SPI_PAD_CONFIG_D_S) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 -/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; - * Description: read for SPI_pad_config_q - */ +/* EFUSE_RD_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; */ -#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M (EFUSE_RD_SPI_PAD_CONFIG_Q_V << EFUSE_RD_SPI_PAD_CONFIG_Q_S) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 -/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; - * Description: read for SPI_pad_config_clk - */ +/* EFUSE_RD_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; */ #define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M (EFUSE_RD_SPI_PAD_CONFIG_CLK_V << EFUSE_RD_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x0000001f #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 -#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) +/* EFUSE_BLK0_RDATA6_REG register */ -/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; - * Description: read for key_status - */ +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x18) -#define EFUSE_RD_KEY_STATUS (BIT(10)) -#define EFUSE_RD_KEY_STATUS_M (BIT(10)) -#define EFUSE_RD_KEY_STATUS_V 0x1 -#define EFUSE_RD_KEY_STATUS_S 10 +/* EFUSE_RD_RESERVE_0_203 : RW; bitpos: [31:11]; default: 0; */ -/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; - * Description: read for download_dis_cache - */ +#define EFUSE_RD_RESERVE_0_203 0x001fffff +#define EFUSE_RD_RESERVE_0_203_M (EFUSE_RD_RESERVE_0_203_V << EFUSE_RD_RESERVE_0_203_S) +#define EFUSE_RD_RESERVE_0_203_V 0x001fffff +#define EFUSE_RD_RESERVE_0_203_S 11 -#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_RD_DISABLE_DL_CACHE_S 9 +/* EFUSE_RD_KEY_STATUS : R; bitpos: [10]; default: 0; */ -/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; - * Description: read for download_dis_decrypt - */ +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (EFUSE_RD_KEY_STATUS_V << EFUSE_RD_KEY_STATUS_S) +#define EFUSE_RD_KEY_STATUS_V 0x00000001 +#define EFUSE_RD_KEY_STATUS_S 10 + +/* EFUSE_RD_DISABLE_DL_CACHE : R; bitpos: [9]; default: 0; */ + +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (EFUSE_RD_DISABLE_DL_CACHE_V << EFUSE_RD_DISABLE_DL_CACHE_S) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x00000001 +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 + +/* EFUSE_RD_DISABLE_DL_DECRYPT : R; bitpos: [8]; default: 0; */ #define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (EFUSE_RD_DISABLE_DL_DECRYPT_V << EFUSE_RD_DISABLE_DL_DECRYPT_S) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x00000001 #define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 -/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; - * Description: read for download_dis_encrypt - */ +/* EFUSE_RD_DISABLE_DL_ENCRYPT : R; bitpos: [7]; default: 0; */ #define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (EFUSE_RD_DISABLE_DL_ENCRYPT_V << EFUSE_RD_DISABLE_DL_ENCRYPT_S) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x00000001 #define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 -/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; - * Description: read for JTAG_disable - */ +/* EFUSE_RD_JTAG_DISABLE : R; bitpos: [6]; default: 0; */ -#define EFUSE_RD_DISABLE_JTAG (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_V 0x1 -#define EFUSE_RD_DISABLE_JTAG_S 6 +#define EFUSE_RD_JTAG_DISABLE (BIT(6)) +#define EFUSE_RD_JTAG_DISABLE_M (EFUSE_RD_JTAG_DISABLE_V << EFUSE_RD_JTAG_DISABLE_S) +#define EFUSE_RD_JTAG_DISABLE_V 0x00000001 +#define EFUSE_RD_JTAG_DISABLE_S 6 -/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; - * Description: read for abstract_done_1 - */ +/* EFUSE_RD_ABS_DONE_1 : R; bitpos: [5]; default: 0; */ -#define EFUSE_RD_ABS_DONE_1 (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_V 0x1 -#define EFUSE_RD_ABS_DONE_1_S 5 +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (EFUSE_RD_ABS_DONE_1_V << EFUSE_RD_ABS_DONE_1_S) +#define EFUSE_RD_ABS_DONE_1_V 0x00000001 +#define EFUSE_RD_ABS_DONE_1_S 5 -/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; - * Description: read for abstract_done_0 - */ +/* EFUSE_RD_ABS_DONE_0 : R; bitpos: [4]; default: 0; */ -#define EFUSE_RD_ABS_DONE_0 (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_V 0x1 -#define EFUSE_RD_ABS_DONE_0_S 4 +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (EFUSE_RD_ABS_DONE_0_V << EFUSE_RD_ABS_DONE_0_S) +#define EFUSE_RD_ABS_DONE_0_V 0x00000001 +#define EFUSE_RD_ABS_DONE_0_S 4 -/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_RD_DISABLE_SDIO_HOST : R; bitpos: [3]; default: 0; */ -#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (EFUSE_RD_DISABLE_SDIO_HOST_V << EFUSE_RD_DISABLE_SDIO_HOST_S) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x00000001 +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 -/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; - * Description: read for console_debug_disable - */ +/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : R; bitpos: [2]; default: 0; */ #define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (EFUSE_RD_CONSOLE_DEBUG_DISABLE_V << EFUSE_RD_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x00000001 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; - * Description: read for coding_scheme - */ - -#define EFUSE_RD_CODING_SCHEME 0x00000003 -#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V) << \ - (EFUSE_RD_CODING_SCHEME_S)) -#define EFUSE_RD_CODING_SCHEME_V 0x3 -#define EFUSE_RD_CODING_SCHEME_S 0 - -#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 -#define EFUSE_CODING_SCHEME_VAL_34 0x1 -#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 - -#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) - -/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; - * Description: program for flash_crypt_cnt - */ - -#define EFUSE_FLASH_CRYPT_CNT 0x0000007f -#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V) << \ - (EFUSE_FLASH_CRYPT_CNT_S)) -#define EFUSE_FLASH_CRYPT_CNT_V 0x7f -#define EFUSE_FLASH_CRYPT_CNT_S 20 - -/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; - * Description: program for efuse_rd_disable - */ - -#define EFUSE_RD_DIS 0x0000000f -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V) << \ - (EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0xf -#define EFUSE_RD_DIS_S 16 - -/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; - * Description: program for efuse_wr_disable - */ - -#define EFUSE_WR_DIS 0x0000ffff -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V) << \ - (EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xffff -#define EFUSE_WR_DIS_S 0 - -#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) - -/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; - * Description: program for low 32bit WIFI_MAC_Address - */ - -#define EFUSE_WIFI_MAC_CRC_LOW 0xffffffff -#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V) << \ - (EFUSE_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_WIFI_MAC_CRC_LOW_V 0xffffffff -#define EFUSE_WIFI_MAC_CRC_LOW_S 0 - -#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) - -/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; - * Description: program for high 24bit WIFI_MAC_Address - */ - -#define EFUSE_WIFI_MAC_CRC_HIGH 0x00ffffff -#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V) << \ - (EFUSE_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xffffff -#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 - -#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) - -/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V) << \ - (EFUSE_CHIP_VER_REV1_S)) -#define EFUSE_CHIP_VER_REV1_V 0x1 -#define EFUSE_CHIP_VER_REV1_S 15 - -/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; - * Description: If set, this bit indicates that BLOCK3[143:96] is reserved - * for internal use - */ - -#define EFUSE_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V) << \ - (EFUSE_BLK3_PART_RESERVE_S)) -#define EFUSE_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_BLK3_PART_RESERVE_S 14 - -/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; - * Description: If set, the ESP32's maximum CPU frequency has been rated - */ - -#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V) << \ - (EFUSE_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 - -/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; - * Description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max - * CPU frequency is rated for 160MHz. 240MHz otherwise - */ - -#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V) << \ - (EFUSE_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 - -/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_PKG 0x00000007 -#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V) << \ - (EFUSE_CHIP_VER_PKG_S)) -#define EFUSE_CHIP_VER_PKG_V 0x7 -#define EFUSE_CHIP_VER_PKG_S 9 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 - -/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; - * Description: program for SPI_pad_config_hd - */ - -#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V) << \ - (EFUSE_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_HD_S 4 - -/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_CHIP_VER_DIS_CACHE_S 3 - -/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_V 0x1 -#define EFUSE_CHIP_VER_32PAD_S 2 - -/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_CHIP_VER_DIS_BT_S 1 - -/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 - -#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) - -/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; - * Description: program for sdio_force - */ - -#define EFUSE_SDIO_FORCE (BIT(16)) -#define EFUSE_SDIO_FORCE_M (BIT(16)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 16 - -/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: program for SDIO_TIEH - */ - -#define EFUSE_SDIO_TIEH (BIT(15)) -#define EFUSE_SDIO_TIEH_M (BIT(15)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 15 - -/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; - * Description: program for XPD_SDIO_REG - */ - -#define EFUSE_XPD_SDIO_REG (BIT(14)) -#define EFUSE_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_XPD_SDIO_REG_V 0x1 -#define EFUSE_XPD_SDIO_REG_S 14 - -/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; - * Description: True ADC reference voltage - */ - -#define EFUSE_ADC_VREF 0x0000001f -#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V) << \ - (EFUSE_ADC_VREF_S)) -#define EFUSE_ADC_VREF_V 0x1f -#define EFUSE_ADC_VREF_S 8 - -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ - -/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V) << \ - (EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 12 - -/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V) << \ - (EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 10 - -/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V) << \ - (EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 8 - -/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; - * Description: - */ - -#define EFUSE_CK8M_FREQ 0x000000ff -#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V) << \ - (EFUSE_CK8M_FREQ_S)) -#define EFUSE_CK8M_FREQ_V 0xff -#define EFUSE_CK8M_FREQ_S 0 - -#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) - -/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; - * Description: program for flash_crypt_config - */ - -#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000f -#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V) << \ - (EFUSE_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_FLASH_CRYPT_CONFIG_V 0xf -#define EFUSE_FLASH_CRYPT_CONFIG_S 28 - -/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; - * Description: This field stores the difference between the digital - * regulator voltage at level6 and 1.2 V. (R/W) - * BIT[27] is the sign bit, 0: + , 1: - - * BIT[26:24] is the difference value, unit: 0.017V - * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + - * BIT[26:24] * 0.017 - */ - -#define EFUSE_DIG_VOL_L6 0x0f -#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ - (EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_DIG_VOL_L6_V 0x0f -#define EFUSE_DIG_VOL_L6_S 24 - -/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] - * Description: This field stores the voltage level for CPU to run at - * 240 MHz, or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; - * 0x1: level 6; - * 0x2: level 5; - * 0x3: level 4. (R/W) - */ - -#define EFUSE_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ - (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_S 22 - -/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; - * Deprecated - */ - -#define EFUSE_INST_CONFIG 0x000000ff /* Deprecated */ -#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V) << \ - (EFUSE_INST_CONFIG_S)) /* Deprecated */ -#define EFUSE_INST_CONFIG_V 0xff /* Deprecated */ -#define EFUSE_INST_CONFIG_S 20 /* Deprecated */ - -/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; - * Description: program for SPI_pad_config_cs0 - */ - -#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V) << \ - (EFUSE_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 - -/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; - * Description: program for SPI_pad_config_d - */ - -#define EFUSE_SPI_PAD_CONFIG_D 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V) << \ - (EFUSE_SPI_PAD_CONFIG_D_S)) -#define EFUSE_SPI_PAD_CONFIG_D_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_D_S 10 - -/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; - * Description: program for SPI_pad_config_q - */ - -#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V) << \ - (EFUSE_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_Q_S 5 - -/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; - * Description: program for SPI_pad_config_clk - */ - -#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V) << \ - (EFUSE_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 - -#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) - -/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; - * Description: program for key_status - */ - -#define EFUSE_KEY_STATUS (BIT(10)) -#define EFUSE_KEY_STATUS_M (BIT(10)) -#define EFUSE_KEY_STATUS_V 0x1 -#define EFUSE_KEY_STATUS_S 10 - -/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; - * Description: program for download_dis_cache - */ - -#define EFUSE_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_DISABLE_DL_CACHE_S 9 - -/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; - * Description: program for download_dis_decrypt - */ - -#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_DISABLE_DL_DECRYPT_S 8 - -/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; - * Description: program for download_dis_encrypt - */ - -#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_DISABLE_DL_ENCRYPT_S 7 - -/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; - * Description: program for JTAG_disable - */ - -#define EFUSE_DISABLE_JTAG (BIT(6)) -#define EFUSE_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_DISABLE_JTAG_V 0x1 -#define EFUSE_DISABLE_JTAG_S 6 - -/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; - * Description: program for abstract_done_1 - */ - -#define EFUSE_ABS_DONE_1 (BIT(5)) -#define EFUSE_ABS_DONE_1_M (BIT(5)) -#define EFUSE_ABS_DONE_1_V 0x1 -#define EFUSE_ABS_DONE_1_S 5 - -/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; - * Description: program for abstract_done_0 - */ - -#define EFUSE_ABS_DONE_0 (BIT(4)) -#define EFUSE_ABS_DONE_0_M (BIT(4)) -#define EFUSE_ABS_DONE_0_V 0x1 -#define EFUSE_ABS_DONE_0_S 4 - -/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_DISABLE_SDIO_HOST_S 3 - -/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; - * Description: program for console_debug_disable - */ +/* EFUSE_RD_CODING_SCHEME : R; bitpos: [1:0]; default: 0; */ + +#define EFUSE_RD_CODING_SCHEME 0x00000003 +#define EFUSE_RD_CODING_SCHEME_M (EFUSE_RD_CODING_SCHEME_V << EFUSE_RD_CODING_SCHEME_S) +#define EFUSE_RD_CODING_SCHEME_V 0x00000003 +#define EFUSE_RD_CODING_SCHEME_S 0 + +/* EFUSE_BLK0_WDATA0_REG register */ + +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_FLASH_CRYPT_CNT : RW; bitpos: [26:20]; default: 0; */ + +#define EFUSE_FLASH_CRYPT_CNT 0x0000007f +#define EFUSE_FLASH_CRYPT_CNT_M (EFUSE_FLASH_CRYPT_CNT_V << EFUSE_FLASH_CRYPT_CNT_S) +#define EFUSE_FLASH_CRYPT_CNT_V 0x0000007f +#define EFUSE_FLASH_CRYPT_CNT_S 20 + +/* EFUSE_RD_DIS : RW; bitpos: [19:16]; default: 0; */ + +#define EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000000f +#define EFUSE_RD_DIS_S 16 + +/* EFUSE_WR_DIS : RW; bitpos: [15:0]; default: 0; */ + +#define EFUSE_WR_DIS 0x0000ffff +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0x0000ffff +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_BLK0_WDATA1_REG register */ + +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_WIFI_MAC_CRC_LOW : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_WIFI_MAC_CRC_LOW 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_M (EFUSE_WIFI_MAC_CRC_LOW_V << EFUSE_WIFI_MAC_CRC_LOW_S) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_S 0 + +/* EFUSE_BLK0_WDATA2_REG register */ + +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_WIFI_MAC_CRC_HIGH : RW; bitpos: [23:0]; default: 0; */ + +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00ffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_M (EFUSE_WIFI_MAC_CRC_HIGH_V << EFUSE_WIFI_MAC_CRC_HIGH_S) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0x00ffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 + +/* EFUSE_BLK0_WDATA3_REG register */ + +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; */ + +#define EFUSE_RESERVE_0_112 0x0000ffff +#define EFUSE_RESERVE_0_112_M (EFUSE_RESERVE_0_112_V << EFUSE_RESERVE_0_112_S) +#define EFUSE_RESERVE_0_112_V 0x0000ffff +#define EFUSE_RESERVE_0_112_S 16 + +/* EFUSE_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; */ + +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M (EFUSE_CHIP_VER_REV1_V << EFUSE_CHIP_VER_REV1_S) +#define EFUSE_CHIP_VER_REV1_V 0x00000001 +#define EFUSE_CHIP_VER_REV1_S 15 + +/* EFUSE_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; */ + +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M (EFUSE_BLK3_PART_RESERVE_V << EFUSE_BLK3_PART_RESERVE_S) +#define EFUSE_BLK3_PART_RESERVE_V 0x00000001 +#define EFUSE_BLK3_PART_RESERVE_S 14 + +/* EFUSE_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M (EFUSE_CHIP_CPU_FREQ_RATED_V << EFUSE_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x00000001 +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 + +/* EFUSE_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; */ + +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M (EFUSE_CHIP_CPU_FREQ_LOW_V << EFUSE_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x00000001 +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 + +/* EFUSE_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; */ + +#define EFUSE_CHIP_PACKAGE 0x00000007 +#define EFUSE_CHIP_PACKAGE_M (EFUSE_CHIP_PACKAGE_V << EFUSE_CHIP_PACKAGE_S) +#define EFUSE_CHIP_PACKAGE_V 0x00000007 +#define EFUSE_CHIP_PACKAGE_S 9 + +/* EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_HD_S 4 + +/* EFUSE_DIS_CACHE : R; bitpos: [3]; default: 0; */ + +#define EFUSE_DIS_CACHE (BIT(3)) +#define EFUSE_DIS_CACHE_M (EFUSE_DIS_CACHE_V << EFUSE_DIS_CACHE_S) +#define EFUSE_DIS_CACHE_V 0x00000001 +#define EFUSE_DIS_CACHE_S 3 + +/* EFUSE_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; */ + +#define EFUSE_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_CHIP_PACKAGE_4BIT_M (EFUSE_CHIP_PACKAGE_4BIT_V << EFUSE_CHIP_PACKAGE_4BIT_S) +#define EFUSE_CHIP_PACKAGE_4BIT_V 0x00000001 +#define EFUSE_CHIP_PACKAGE_4BIT_S 2 + +/* EFUSE_DISABLE_BT : R; bitpos: [1]; default: 0; */ + +#define EFUSE_DISABLE_BT (BIT(1)) +#define EFUSE_DISABLE_BT_M (EFUSE_DISABLE_BT_V << EFUSE_DISABLE_BT_S) +#define EFUSE_DISABLE_BT_V 0x00000001 +#define EFUSE_DISABLE_BT_S 1 + +/* EFUSE_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; */ + +#define EFUSE_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_DISABLE_APP_CPU_M (EFUSE_DISABLE_APP_CPU_V << EFUSE_DISABLE_APP_CPU_S) +#define EFUSE_DISABLE_APP_CPU_V 0x00000001 +#define EFUSE_DISABLE_APP_CPU_S 0 + +/* EFUSE_BLK0_WDATA4_REG register */ + +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; */ + +#define EFUSE_RESERVE_0_145 0x00007fff +#define EFUSE_RESERVE_0_145_M (EFUSE_RESERVE_0_145_V << EFUSE_RESERVE_0_145_S) +#define EFUSE_RESERVE_0_145_V 0x00007fff +#define EFUSE_RESERVE_0_145_S 17 + +/* EFUSE_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; */ + +#define EFUSE_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_XPD_SDIO_FORCE_M (EFUSE_XPD_SDIO_FORCE_V << EFUSE_XPD_SDIO_FORCE_S) +#define EFUSE_XPD_SDIO_FORCE_V 0x00000001 +#define EFUSE_XPD_SDIO_FORCE_S 16 + +/* EFUSE_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; */ + +#define EFUSE_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_XPD_SDIO_TIEH_M (EFUSE_XPD_SDIO_TIEH_V << EFUSE_XPD_SDIO_TIEH_S) +#define EFUSE_XPD_SDIO_TIEH_V 0x00000001 +#define EFUSE_XPD_SDIO_TIEH_S 15 + +/* EFUSE_XPD_SDIO_REG : R; bitpos: [14]; default: 0; */ + +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (EFUSE_XPD_SDIO_REG_V << EFUSE_XPD_SDIO_REG_S) +#define EFUSE_XPD_SDIO_REG_V 0x00000001 +#define EFUSE_XPD_SDIO_REG_S 14 + +/* EFUSE_RESERVE_0_141 : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_RESERVE_0_141 (BIT(13)) +#define EFUSE_RESERVE_0_141_M (EFUSE_RESERVE_0_141_V << EFUSE_RESERVE_0_141_S) +#define EFUSE_RESERVE_0_141_V 0x00000001 +#define EFUSE_RESERVE_0_141_S 13 + +/* EFUSE_ADC_VREF : RW; bitpos: [12:8]; default: 0; */ + +#define EFUSE_ADC_VREF 0x0000001f +#define EFUSE_ADC_VREF_M (EFUSE_ADC_VREF_V << EFUSE_ADC_VREF_S) +#define EFUSE_ADC_VREF_V 0x0000001f +#define EFUSE_ADC_VREF_S 8 + +/* EFUSE_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; */ + +#define EFUSE_CLK8M_FREQ 0x000000ff +#define EFUSE_CLK8M_FREQ_M (EFUSE_CLK8M_FREQ_V << EFUSE_CLK8M_FREQ_S) +#define EFUSE_CLK8M_FREQ_V 0x000000ff +#define EFUSE_CLK8M_FREQ_S 0 + +/* EFUSE_BLK0_WDATA5_REG register */ + +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; */ + +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000f +#define EFUSE_FLASH_CRYPT_CONFIG_M (EFUSE_FLASH_CRYPT_CONFIG_V << EFUSE_FLASH_CRYPT_CONFIG_S) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0x0000000f +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 + +/* EFUSE_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; */ + +#define EFUSE_RESERVE_0_186 0x00000003 +#define EFUSE_RESERVE_0_186_M (EFUSE_RESERVE_0_186_V << EFUSE_RESERVE_0_186_S) +#define EFUSE_RESERVE_0_186_V 0x00000003 +#define EFUSE_RESERVE_0_186_S 26 + +/* EFUSE_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ + +#define EFUSE_WAFER_VERSION_MINOR 0x00000003 +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000003 +#define EFUSE_WAFER_VERSION_MINOR_S 24 + +/* EFUSE_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; */ + +#define EFUSE_VOL_LEVEL_HP_INV 0x00000003 +#define EFUSE_VOL_LEVEL_HP_INV_M (EFUSE_VOL_LEVEL_HP_INV_V << EFUSE_VOL_LEVEL_HP_INV_S) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x00000003 +#define EFUSE_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RESERVE_0_181 : RW; bitpos: [21]; default: 0; */ + +#define EFUSE_RESERVE_0_181 (BIT(21)) +#define EFUSE_RESERVE_0_181_M (EFUSE_RESERVE_0_181_V << EFUSE_RESERVE_0_181_S) +#define EFUSE_RESERVE_0_181_V 0x00000001 +#define EFUSE_RESERVE_0_181_S 21 + +/* EFUSE_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ + +#define EFUSE_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_CHIP_VER_REV2_M (EFUSE_CHIP_VER_REV2_V << EFUSE_CHIP_VER_REV2_S) +#define EFUSE_CHIP_VER_REV2_V 0x00000001 +#define EFUSE_CHIP_VER_REV2_S 20 + +/* EFUSE_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CS0_M (EFUSE_SPI_PAD_CONFIG_CS0_V << EFUSE_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 + +/* EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_D_S 10 + +/* EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 + +/* EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 + +/* EFUSE_BLK0_WDATA6_REG register */ + +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_KEY_STATUS : RW; bitpos: [10]; default: 0; */ + +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (EFUSE_KEY_STATUS_V << EFUSE_KEY_STATUS_S) +#define EFUSE_KEY_STATUS_V 0x00000001 +#define EFUSE_KEY_STATUS_S 10 + +/* EFUSE_DISABLE_DL_CACHE : RW; bitpos: [9]; default: 0; */ + +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (EFUSE_DISABLE_DL_CACHE_V << EFUSE_DISABLE_DL_CACHE_S) +#define EFUSE_DISABLE_DL_CACHE_V 0x00000001 +#define EFUSE_DISABLE_DL_CACHE_S 9 + +/* EFUSE_DISABLE_DL_DECRYPT : RW; bitpos: [8]; default: 0; */ + +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (EFUSE_DISABLE_DL_DECRYPT_V << EFUSE_DISABLE_DL_DECRYPT_S) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x00000001 +#define EFUSE_DISABLE_DL_DECRYPT_S 8 + +/* EFUSE_DISABLE_DL_ENCRYPT : RW; bitpos: [7]; default: 0; */ + +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (EFUSE_DISABLE_DL_ENCRYPT_V << EFUSE_DISABLE_DL_ENCRYPT_S) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x00000001 +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 + +/* EFUSE_DISABLE_JTAG : RW; bitpos: [6]; default: 0; */ + +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (EFUSE_DISABLE_JTAG_V << EFUSE_DISABLE_JTAG_S) +#define EFUSE_DISABLE_JTAG_V 0x00000001 +#define EFUSE_DISABLE_JTAG_S 6 + +/* EFUSE_ABS_DONE_1 : RW; bitpos: [5]; default: 0; */ + +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (EFUSE_ABS_DONE_1_V << EFUSE_ABS_DONE_1_S) +#define EFUSE_ABS_DONE_1_V 0x00000001 +#define EFUSE_ABS_DONE_1_S 5 + +/* EFUSE_ABS_DONE_0 : RW; bitpos: [4]; default: 0; */ + +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (EFUSE_ABS_DONE_0_V << EFUSE_ABS_DONE_0_S) +#define EFUSE_ABS_DONE_0_V 0x00000001 +#define EFUSE_ABS_DONE_0_S 4 + +/* EFUSE_DISABLE_SDIO_HOST : RW; bitpos: [3]; default: 0; */ + +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (EFUSE_DISABLE_SDIO_HOST_V << EFUSE_DISABLE_SDIO_HOST_S) +#define EFUSE_DISABLE_SDIO_HOST_V 0x00000001 +#define EFUSE_DISABLE_SDIO_HOST_S 3 + +/* EFUSE_CONSOLE_DEBUG_DISABLE : RW; bitpos: [2]; default: 0; */ #define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (EFUSE_CONSOLE_DEBUG_DISABLE_V << EFUSE_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x00000001 #define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 -/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; - * Description: program for coding_scheme - */ - -#define EFUSE_CODING_SCHEME 0x00000003 -#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V) << \ - (EFUSE_CODING_SCHEME_S)) -#define EFUSE_CODING_SCHEME_V 0x3 -#define EFUSE_CODING_SCHEME_S 0 +/* EFUSE_CODING_SCHEME : RW; bitpos: [1:0]; default: 0; */ -#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) +#define EFUSE_CODING_SCHEME 0x00000003 +#define EFUSE_CODING_SCHEME_M (EFUSE_CODING_SCHEME_V << EFUSE_CODING_SCHEME_S) +#define EFUSE_CODING_SCHEME_V 0x00000003 +#define EFUSE_CODING_SCHEME_S 0 -/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT0 0xffffffff -#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V) << \ - (EFUSE_BLK1_DOUT0_S)) -#define EFUSE_BLK1_DOUT0_V 0xffffffff -#define EFUSE_BLK1_DOUT0_S 0 +/* EFUSE_BLK1_RDATA0_REG register */ -#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x38) -/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT1 0xffffffff -#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V) << \ - (EFUSE_BLK1_DOUT1_S)) -#define EFUSE_BLK1_DOUT1_V 0xffffffff -#define EFUSE_BLK1_DOUT1_S 0 +/* EFUSE_RD_BLOCK1 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) +#define EFUSE_RD_BLOCK1 0xffffffff +#define EFUSE_RD_BLOCK1_M (EFUSE_RD_BLOCK1_V << EFUSE_RD_BLOCK1_S) +#define EFUSE_RD_BLOCK1_V 0xffffffff +#define EFUSE_RD_BLOCK1_S 0 -/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT2 0xffffffff -#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V) << \ - (EFUSE_BLK1_DOUT2_S)) -#define EFUSE_BLK1_DOUT2_V 0xffffffff -#define EFUSE_BLK1_DOUT2_S 0 +/* EFUSE_BLK1_RDATA1_REG register */ -#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x3c) -/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT3 0xffffffff -#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V) << \ - (EFUSE_BLK1_DOUT3_S)) -#define EFUSE_BLK1_DOUT3_V 0xffffffff -#define EFUSE_BLK1_DOUT3_S 0 +/* EFUSE_RD_BLOCK1_1 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) +#define EFUSE_RD_BLOCK1_1 0xffffffff +#define EFUSE_RD_BLOCK1_1_M (EFUSE_RD_BLOCK1_1_V << EFUSE_RD_BLOCK1_1_S) +#define EFUSE_RD_BLOCK1_1_V 0xffffffff +#define EFUSE_RD_BLOCK1_1_S 0 -/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT4 0xffffffff -#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V) << \ - (EFUSE_BLK1_DOUT4_S)) -#define EFUSE_BLK1_DOUT4_V 0xffffffff -#define EFUSE_BLK1_DOUT4_S 0 +/* EFUSE_BLK1_RDATA2_REG register */ -#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x40) -/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT5 0xffffffff -#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V) << \ - (EFUSE_BLK1_DOUT5_S)) -#define EFUSE_BLK1_DOUT5_V 0xffffffff -#define EFUSE_BLK1_DOUT5_S 0 +/* EFUSE_RD_BLOCK1_2 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) +#define EFUSE_RD_BLOCK1_2 0xffffffff +#define EFUSE_RD_BLOCK1_2_M (EFUSE_RD_BLOCK1_2_V << EFUSE_RD_BLOCK1_2_S) +#define EFUSE_RD_BLOCK1_2_V 0xffffffff +#define EFUSE_RD_BLOCK1_2_S 0 -/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT6 0xffffffff -#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V) << \ - (EFUSE_BLK1_DOUT6_S)) -#define EFUSE_BLK1_DOUT6_V 0xffffffff -#define EFUSE_BLK1_DOUT6_S 0 +/* EFUSE_BLK1_RDATA3_REG register */ -#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x44) -/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT7 0xffffffff -#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V) << \ - (EFUSE_BLK1_DOUT7_S)) -#define EFUSE_BLK1_DOUT7_V 0xffffffff -#define EFUSE_BLK1_DOUT7_S 0 +/* EFUSE_RD_BLOCK1_3 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) +#define EFUSE_RD_BLOCK1_3 0xffffffff +#define EFUSE_RD_BLOCK1_3_M (EFUSE_RD_BLOCK1_3_V << EFUSE_RD_BLOCK1_3_S) +#define EFUSE_RD_BLOCK1_3_V 0xffffffff +#define EFUSE_RD_BLOCK1_3_S 0 -/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ +/* EFUSE_BLK1_RDATA4_REG register */ -#define EFUSE_BLK2_DOUT0 0xffffffff -#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V) << \ - (EFUSE_BLK2_DOUT0_S)) -#define EFUSE_BLK2_DOUT0_V 0xffffffff -#define EFUSE_BLK2_DOUT0_S 0 +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x48) -#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) +/* EFUSE_RD_BLOCK1_4 : R; bitpos: [31:0]; default: 0; */ -/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ +#define EFUSE_RD_BLOCK1_4 0xffffffff +#define EFUSE_RD_BLOCK1_4_M (EFUSE_RD_BLOCK1_4_V << EFUSE_RD_BLOCK1_4_S) +#define EFUSE_RD_BLOCK1_4_V 0xffffffff +#define EFUSE_RD_BLOCK1_4_S 0 -#define EFUSE_BLK2_DOUT1 0xffffffff -#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V) << \ - (EFUSE_BLK2_DOUT1_S)) -#define EFUSE_BLK2_DOUT1_V 0xffffffff -#define EFUSE_BLK2_DOUT1_S 0 +/* EFUSE_BLK1_RDATA5_REG register */ -#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x4c) -/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ +/* EFUSE_RD_BLOCK1_5 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_DOUT2 0xffffffff -#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V) << \ - (EFUSE_BLK2_DOUT2_S)) -#define EFUSE_BLK2_DOUT2_V 0xffffffff -#define EFUSE_BLK2_DOUT2_S 0 - -#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) +#define EFUSE_RD_BLOCK1_5 0xffffffff +#define EFUSE_RD_BLOCK1_5_M (EFUSE_RD_BLOCK1_5_V << EFUSE_RD_BLOCK1_5_S) +#define EFUSE_RD_BLOCK1_5_V 0xffffffff +#define EFUSE_RD_BLOCK1_5_S 0 -/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ +/* EFUSE_BLK1_RDATA6_REG register */ -#define EFUSE_BLK2_DOUT3 0xffffffff -#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V) << \ - (EFUSE_BLK2_DOUT3_S)) -#define EFUSE_BLK2_DOUT3_V 0xffffffff -#define EFUSE_BLK2_DOUT3_S 0 - -#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x50) -/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ +/* EFUSE_RD_BLOCK1_6 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_DOUT4 0xffffffff -#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V) << \ - (EFUSE_BLK2_DOUT4_S)) -#define EFUSE_BLK2_DOUT4_V 0xffffffff -#define EFUSE_BLK2_DOUT4_S 0 - -#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) - -/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT5 0xffffffff -#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V) << \ - (EFUSE_BLK2_DOUT5_S)) -#define EFUSE_BLK2_DOUT5_V 0xffffffff -#define EFUSE_BLK2_DOUT5_S 0 - -#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) - -/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT6 0xffffffff -#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V) << \ - (EFUSE_BLK2_DOUT6_S)) -#define EFUSE_BLK2_DOUT6_V 0xffffffff -#define EFUSE_BLK2_DOUT6_S 0 - -#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) - -/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT7 0xffffffff -#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V) << \ - (EFUSE_BLK2_DOUT7_S)) -#define EFUSE_BLK2_DOUT7_V 0xffffffff -#define EFUSE_BLK2_DOUT7_S 0 - -#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) - -/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT0 0xffffffff -#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V) << \ - (EFUSE_BLK3_DOUT0_S)) -#define EFUSE_BLK3_DOUT0_V 0xffffffff -#define EFUSE_BLK3_DOUT0_S 0 - -#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) - -/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT1 0xffffffff -#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V) << \ - (EFUSE_BLK3_DOUT1_S)) -#define EFUSE_BLK3_DOUT1_V 0xffffffff -#define EFUSE_BLK3_DOUT1_S 0 - -#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) - -/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT2 0xffffffff -#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V) << \ - (EFUSE_BLK3_DOUT2_S)) -#define EFUSE_BLK3_DOUT2_V 0xffffffff -#define EFUSE_BLK3_DOUT2_S 0 - -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for - * calibration purposes. This usage is indicated by the - * EFUSE_RD_BLK3_PART_RESERVE bit. - */ - -#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) - -/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT3 0xffffffff -#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V) << \ - (EFUSE_BLK3_DOUT3_S)) -#define EFUSE_BLK3_DOUT3_V 0xffffffff -#define EFUSE_BLK3_DOUT3_S 0 - -/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; - * Description: ADC2 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC2_TP_HIGH 0x1ff -#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V) << \ - (EFUSE_RD_ADC2_TP_HIGH_S)) -#define EFUSE_RD_ADC2_TP_HIGH_V 0x1ff -#define EFUSE_RD_ADC2_TP_HIGH_S 23 - -/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; - * Description: ADC2 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC2_TP_LOW 0x7f -#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V) << \ - (EFUSE_RD_ADC2_TP_LOW_S)) -#define EFUSE_RD_ADC2_TP_LOW_V 0x7f -#define EFUSE_RD_ADC2_TP_LOW_S 16 - -/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; - * Description: ADC1 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC1_TP_HIGH 0x1ff -#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V) << \ - (EFUSE_RD_ADC1_TP_HIGH_S)) -#define EFUSE_RD_ADC1_TP_HIGH_V 0x1ff -#define EFUSE_RD_ADC1_TP_HIGH_S 7 - -/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; - * Description: ADC1 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC1_TP_LOW 0x7f -#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V) << \ - (EFUSE_RD_ADC1_TP_LOW_S)) -#define EFUSE_RD_ADC1_TP_LOW_V 0x7f -#define EFUSE_RD_ADC1_TP_LOW_S 0 - -#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) - -/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT4 0xffffffff -#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V) << \ - (EFUSE_BLK3_DOUT4_S)) -#define EFUSE_BLK3_DOUT4_V 0xffffffff -#define EFUSE_BLK3_DOUT4_S 0 - -/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; - * Description: Reserved for future calibration use. Indicated by - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_CAL_RESERVED 0x0000ffff -#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V) << \ - (EFUSE_RD_CAL_RESERVED_S)) -#define EFUSE_RD_CAL_RESERVED_V 0xffff -#define EFUSE_RD_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) - -/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT5 0xffffffff -#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V) << \ - (EFUSE_BLK3_DOUT5_S)) -#define EFUSE_BLK3_DOUT5_V 0xffffffff -#define EFUSE_BLK3_DOUT5_S 0 - -#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) - -/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT6 0xffffffff -#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V) << (EFUSE_BLK3_DOUT6_S)) -#define EFUSE_BLK3_DOUT6_V 0xffffffff -#define EFUSE_BLK3_DOUT6_S 0 - -#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) - -/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT7 0xffffffff -#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V) << \ - (EFUSE_BLK3_DOUT7_S)) -#define EFUSE_BLK3_DOUT7_V 0xffffffff -#define EFUSE_BLK3_DOUT7_S 0 - -#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) - -/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN0 0xffffffff -#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V) << \ - (EFUSE_BLK1_DIN0_S)) -#define EFUSE_BLK1_DIN0_V 0xffffffff -#define EFUSE_BLK1_DIN0_S 0 - -#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) - -/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN1 0xffffffff -#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V) << \ - (EFUSE_BLK1_DIN1_S)) -#define EFUSE_BLK1_DIN1_V 0xffffffff -#define EFUSE_BLK1_DIN1_S 0 - -#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) - -/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN2 0xffffffff -#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V) << \ - (EFUSE_BLK1_DIN2_S)) -#define EFUSE_BLK1_DIN2_V 0xffffffff -#define EFUSE_BLK1_DIN2_S 0 +#define EFUSE_RD_BLOCK1_6 0xffffffff +#define EFUSE_RD_BLOCK1_6_M (EFUSE_RD_BLOCK1_6_V << EFUSE_RD_BLOCK1_6_S) +#define EFUSE_RD_BLOCK1_6_V 0xffffffff +#define EFUSE_RD_BLOCK1_6_S 0 -#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) +/* EFUSE_BLK1_RDATA7_REG register */ -/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x54) -#define EFUSE_BLK1_DIN3 0xffffffff -#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V) << \ - (EFUSE_BLK1_DIN3_S)) -#define EFUSE_BLK1_DIN3_V 0xffffffff -#define EFUSE_BLK1_DIN3_S 0 +/* EFUSE_RD_BLOCK1_7 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) +#define EFUSE_RD_BLOCK1_7 0xffffffff +#define EFUSE_RD_BLOCK1_7_M (EFUSE_RD_BLOCK1_7_V << EFUSE_RD_BLOCK1_7_S) +#define EFUSE_RD_BLOCK1_7_V 0xffffffff +#define EFUSE_RD_BLOCK1_7_S 0 -/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ +/* EFUSE_BLK2_RDATA0_REG register */ -#define EFUSE_BLK1_DIN4 0xffffffff -#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V) << \ - (EFUSE_BLK1_DIN4_S)) -#define EFUSE_BLK1_DIN4_V 0xffffffff -#define EFUSE_BLK1_DIN4_S 0 +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x58) -#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) +/* EFUSE_RD_BLOCK2 : R; bitpos: [31:0]; default: 0; */ -/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ +#define EFUSE_RD_BLOCK2 0xffffffff +#define EFUSE_RD_BLOCK2_M (EFUSE_RD_BLOCK2_V << EFUSE_RD_BLOCK2_S) +#define EFUSE_RD_BLOCK2_V 0xffffffff +#define EFUSE_RD_BLOCK2_S 0 -#define EFUSE_BLK1_DIN5 0xffffffff -#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V) << \ - (EFUSE_BLK1_DIN5_S)) -#define EFUSE_BLK1_DIN5_V 0xffffffff -#define EFUSE_BLK1_DIN5_S 0 +/* EFUSE_BLK2_RDATA1_REG register */ -#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x5c) -/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ +/* EFUSE_RD_BLOCK2_1 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK1_DIN6 0xffffffff -#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V) << \ - (EFUSE_BLK1_DIN6_S)) -#define EFUSE_BLK1_DIN6_V 0xffffffff -#define EFUSE_BLK1_DIN6_S 0 +#define EFUSE_RD_BLOCK2_1 0xffffffff +#define EFUSE_RD_BLOCK2_1_M (EFUSE_RD_BLOCK2_1_V << EFUSE_RD_BLOCK2_1_S) +#define EFUSE_RD_BLOCK2_1_V 0xffffffff +#define EFUSE_RD_BLOCK2_1_S 0 -#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) +/* EFUSE_BLK2_RDATA2_REG register */ -/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x60) -#define EFUSE_BLK1_DIN7 0xffffffff -#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V) << \ - (EFUSE_BLK1_DIN7_S)) -#define EFUSE_BLK1_DIN7_V 0xffffffff -#define EFUSE_BLK1_DIN7_S 0 +/* EFUSE_RD_BLOCK2_2 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) +#define EFUSE_RD_BLOCK2_2 0xffffffff +#define EFUSE_RD_BLOCK2_2_M (EFUSE_RD_BLOCK2_2_V << EFUSE_RD_BLOCK2_2_S) +#define EFUSE_RD_BLOCK2_2_V 0xffffffff +#define EFUSE_RD_BLOCK2_2_S 0 -/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ +/* EFUSE_BLK2_RDATA3_REG register */ -#define EFUSE_BLK2_DIN0 0xffffffff -#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V) << \ - (EFUSE_BLK2_DIN0_S)) -#define EFUSE_BLK2_DIN0_V 0xffffffff -#define EFUSE_BLK2_DIN0_S 0 +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x64) -#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) +/* EFUSE_RD_BLOCK2_3 : R; bitpos: [31:0]; default: 0; */ -/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ +#define EFUSE_RD_BLOCK2_3 0xffffffff +#define EFUSE_RD_BLOCK2_3_M (EFUSE_RD_BLOCK2_3_V << EFUSE_RD_BLOCK2_3_S) +#define EFUSE_RD_BLOCK2_3_V 0xffffffff +#define EFUSE_RD_BLOCK2_3_S 0 -#define EFUSE_BLK2_DIN1 0xffffffff -#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V) << \ - (EFUSE_BLK2_DIN1_S)) -#define EFUSE_BLK2_DIN1_V 0xffffffff -#define EFUSE_BLK2_DIN1_S 0 +/* EFUSE_BLK2_RDATA4_REG register */ -#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x68) -/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ +/* EFUSE_RD_BLOCK2_4 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_DIN2 0xffffffff -#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V) << \ - (EFUSE_BLK2_DIN2_S)) -#define EFUSE_BLK2_DIN2_V 0xffffffff -#define EFUSE_BLK2_DIN2_S 0 - -#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) +#define EFUSE_RD_BLOCK2_4 0xffffffff +#define EFUSE_RD_BLOCK2_4_M (EFUSE_RD_BLOCK2_4_V << EFUSE_RD_BLOCK2_4_S) +#define EFUSE_RD_BLOCK2_4_V 0xffffffff +#define EFUSE_RD_BLOCK2_4_S 0 -/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ +/* EFUSE_BLK2_RDATA5_REG register */ -#define EFUSE_BLK2_DIN3 0xffffffff -#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V) << \ - (EFUSE_BLK2_DIN3_S)) -#define EFUSE_BLK2_DIN3_V 0xffffffff -#define EFUSE_BLK2_DIN3_S 0 - -#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x6c) -/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ +/* EFUSE_RD_BLOCK2_5 : R; bitpos: [31:0]; default: 0; */ -#define EFUSE_BLK2_DIN4 0xffffffff -#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V) << \ - (EFUSE_BLK2_DIN4_S)) -#define EFUSE_BLK2_DIN4_V 0xffffffff -#define EFUSE_BLK2_DIN4_S 0 - -#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) - -/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN5 0xffffffff -#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V) << \ - (EFUSE_BLK2_DIN5_S)) -#define EFUSE_BLK2_DIN5_V 0xffffffff -#define EFUSE_BLK2_DIN5_S 0 - -#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) - -/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN6 0xffffffff -#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V) << \ - (EFUSE_BLK2_DIN6_S)) -#define EFUSE_BLK2_DIN6_V 0xffffffff -#define EFUSE_BLK2_DIN6_S 0 - -#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) - -/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN7 0xffffffff -#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V) << \ - (EFUSE_BLK2_DIN7_S)) -#define EFUSE_BLK2_DIN7_V 0xffffffff -#define EFUSE_BLK2_DIN7_S 0 - -#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) - -/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN0 0xffffffff -#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V) << \ - (EFUSE_BLK3_DIN0_S)) -#define EFUSE_BLK3_DIN0_V 0xffffffff -#define EFUSE_BLK3_DIN0_S 0 - -#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) - -/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN1 0xffffffff -#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V) << \ - (EFUSE_BLK3_DIN1_S)) -#define EFUSE_BLK3_DIN1_V 0xffffffff -#define EFUSE_BLK3_DIN1_S 0 - -#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) - -/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN2 0xffffffff -#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V) << \ - (EFUSE_BLK3_DIN2_S)) -#define EFUSE_BLK3_DIN2_V 0xffffffff -#define EFUSE_BLK3_DIN2_S 0 - -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for - * calibration purposes. This usage is indicated by the - * EFUSE_RD_BLK3_PART_RESERVE bit. - */ - -#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) - -/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN3 0xffffffff -#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V) << \ - (EFUSE_BLK3_DIN3_S)) -#define EFUSE_BLK3_DIN3_V 0xffffffff -#define EFUSE_BLK3_DIN3_S 0 - -/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; - * Description: ADC2 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC2_TP_HIGH 0x1ff -#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V) << \ - (EFUSE_ADC2_TP_HIGH_S)) -#define EFUSE_ADC2_TP_HIGH_V 0x1ff -#define EFUSE_ADC2_TP_HIGH_S 23 - -/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; - * Description: ADC2 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC2_TP_LOW 0x7f -#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V) << \ - (EFUSE_ADC2_TP_LOW_S)) -#define EFUSE_ADC2_TP_LOW_V 0x7f -#define EFUSE_ADC2_TP_LOW_S 16 - -/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; - * Description: ADC1 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC1_TP_HIGH 0x1ff -#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V) << \ - (EFUSE_ADC1_TP_HIGH_S)) -#define EFUSE_ADC1_TP_HIGH_V 0x1ff -#define EFUSE_ADC1_TP_HIGH_S 7 - -/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; - * Description: ADC1 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC1_TP_LOW 0x7f -#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V) << \ - (EFUSE_ADC1_TP_LOW_S)) -#define EFUSE_ADC1_TP_LOW_V 0x7f -#define EFUSE_ADC1_TP_LOW_S 0 - -#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) - -/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN4 0xffffffff -#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V) << \ - (EFUSE_BLK3_DIN4_S)) -#define EFUSE_BLK3_DIN4_V 0xffffffff -#define EFUSE_BLK3_DIN4_S 0 - -/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; - * Description: Reserved for future calibration use. Indicated by - * EFUSE_BLK3_PART_RESERVE - */ - -#define EFUSE_CAL_RESERVED 0x0000ffff -#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V) << \ - (EFUSE_CAL_RESERVED_S)) -#define EFUSE_CAL_RESERVED_V 0xffff -#define EFUSE_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) - -/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN5 0xffffffff -#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V) << \ - (EFUSE_BLK3_DIN5_S)) -#define EFUSE_BLK3_DIN5_V 0xffffffff -#define EFUSE_BLK3_DIN5_S 0 - -#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) - -/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN6 0xffffffff -#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V) << \ - (EFUSE_BLK3_DIN6_S)) -#define EFUSE_BLK3_DIN6_V 0xffffffff -#define EFUSE_BLK3_DIN6_S 0 - -#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) - -/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN7 0xffffffff -#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V) << \ - (EFUSE_BLK3_DIN7_S)) -#define EFUSE_BLK3_DIN7_V 0xffffffff -#define EFUSE_BLK3_DIN7_S 0 - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) - -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 - -/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; - * Description: efuse timing configure - */ - -#define EFUSE_CLK_SEL1 0x000000ff -#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V) << \ - (EFUSE_CLK_SEL1_S)) -#define EFUSE_CLK_SEL1_V 0xff +#define EFUSE_RD_BLOCK2_5 0xffffffff +#define EFUSE_RD_BLOCK2_5_M (EFUSE_RD_BLOCK2_5_V << EFUSE_RD_BLOCK2_5_S) +#define EFUSE_RD_BLOCK2_5_V 0xffffffff +#define EFUSE_RD_BLOCK2_5_S 0 + +/* EFUSE_BLK2_RDATA6_REG register */ + +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_RD_BLOCK2_6 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_6 0xffffffff +#define EFUSE_RD_BLOCK2_6_M (EFUSE_RD_BLOCK2_6_V << EFUSE_RD_BLOCK2_6_S) +#define EFUSE_RD_BLOCK2_6_V 0xffffffff +#define EFUSE_RD_BLOCK2_6_S 0 + +/* EFUSE_BLK2_RDATA7_REG register */ + +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_RD_BLOCK2_7 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_7 0xffffffff +#define EFUSE_RD_BLOCK2_7_M (EFUSE_RD_BLOCK2_7_V << EFUSE_RD_BLOCK2_7_S) +#define EFUSE_RD_BLOCK2_7_V 0xffffffff +#define EFUSE_RD_BLOCK2_7_S 0 + +/* EFUSE_BLK3_RDATA0_REG register */ + +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_RD_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_M (EFUSE_RD_CUSTOM_MAC_V << EFUSE_RD_CUSTOM_MAC_S) +#define EFUSE_RD_CUSTOM_MAC_V 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_S 8 + +/* EFUSE_RD_CUSTOM_MAC_CRC : R; bitpos: [7:0]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC_CRC 0x000000ff +#define EFUSE_RD_CUSTOM_MAC_CRC_M (EFUSE_RD_CUSTOM_MAC_CRC_V << EFUSE_RD_CUSTOM_MAC_CRC_S) +#define EFUSE_RD_CUSTOM_MAC_CRC_V 0x000000ff +#define EFUSE_RD_CUSTOM_MAC_CRC_S 0 + +/* EFUSE_BLK3_RDATA1_REG register */ + +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_RESERVED_3_56 : R; bitpos: [31:24]; default: 0; */ + +#define EFUSE_RESERVED_3_56 0x000000ff +#define EFUSE_RESERVED_3_56_M (EFUSE_RESERVED_3_56_V << EFUSE_RESERVED_3_56_S) +#define EFUSE_RESERVED_3_56_V 0x000000ff +#define EFUSE_RESERVED_3_56_S 24 + +/* EFUSE_RD_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC_1 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_1_M (EFUSE_RD_CUSTOM_MAC_1_V << EFUSE_RD_CUSTOM_MAC_1_S) +#define EFUSE_RD_CUSTOM_MAC_1_V 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_1_S 0 + +/* EFUSE_BLK3_RDATA2_REG register */ + +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_RD_BLK3_RESERVED_2 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_2 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_2_M (EFUSE_RD_BLK3_RESERVED_2_V << EFUSE_RD_BLK3_RESERVED_2_S) +#define EFUSE_RD_BLK3_RESERVED_2_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_2_S 0 + +/* EFUSE_BLK3_RDATA3_REG register */ + +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_RD_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; */ + +#define EFUSE_RD_ADC2_TP_HIGH 0x000001ff +#define EFUSE_RD_ADC2_TP_HIGH_M (EFUSE_RD_ADC2_TP_HIGH_V << EFUSE_RD_ADC2_TP_HIGH_S) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x000001ff +#define EFUSE_RD_ADC2_TP_HIGH_S 23 + +/* EFUSE_RD_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; */ + +#define EFUSE_RD_ADC2_TP_LOW 0x0000007f +#define EFUSE_RD_ADC2_TP_LOW_M (EFUSE_RD_ADC2_TP_LOW_V << EFUSE_RD_ADC2_TP_LOW_S) +#define EFUSE_RD_ADC2_TP_LOW_V 0x0000007f +#define EFUSE_RD_ADC2_TP_LOW_S 16 + +/* EFUSE_RD_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; */ + +#define EFUSE_RD_ADC1_TP_HIGH 0x000001ff +#define EFUSE_RD_ADC1_TP_HIGH_M (EFUSE_RD_ADC1_TP_HIGH_V << EFUSE_RD_ADC1_TP_HIGH_S) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x000001ff +#define EFUSE_RD_ADC1_TP_HIGH_S 7 + +/* EFUSE_RD_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; */ + +#define EFUSE_RD_ADC1_TP_LOW 0x0000007f +#define EFUSE_RD_ADC1_TP_LOW_M (EFUSE_RD_ADC1_TP_LOW_V << EFUSE_RD_ADC1_TP_LOW_S) +#define EFUSE_RD_ADC1_TP_LOW_V 0x0000007f +#define EFUSE_RD_ADC1_TP_LOW_S 0 + +/* EFUSE_BLK3_RDATA4_REG register */ + +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_RD_SECURE_VERSION : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_SECURE_VERSION 0xffffffff +#define EFUSE_RD_SECURE_VERSION_M (EFUSE_RD_SECURE_VERSION_V << EFUSE_RD_SECURE_VERSION_S) +#define EFUSE_RD_SECURE_VERSION_V 0xffffffff +#define EFUSE_RD_SECURE_VERSION_S 0 + +/* EFUSE_BLK3_RDATA5_REG register */ + +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_RD_MAC_VERSION : R; bitpos: [31:24]; default: 0; */ + +#define EFUSE_RD_MAC_VERSION 0x000000ff +#define EFUSE_RD_MAC_VERSION_M (EFUSE_RD_MAC_VERSION_V << EFUSE_RD_MAC_VERSION_S) +#define EFUSE_RD_MAC_VERSION_V 0x000000ff +#define EFUSE_RD_MAC_VERSION_S 24 + +/* EFUSE_RESERVED_3_160 : R; bitpos: [23:0]; default: 0; */ + +#define EFUSE_RESERVED_3_160 0x00ffffff +#define EFUSE_RESERVED_3_160_M (EFUSE_RESERVED_3_160_V << EFUSE_RESERVED_3_160_S) +#define EFUSE_RESERVED_3_160_V 0x00ffffff +#define EFUSE_RESERVED_3_160_S 0 + +/* EFUSE_BLK3_RDATA6_REG register */ + +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_RD_BLK3_RESERVED_6 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_6 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_6_M (EFUSE_RD_BLK3_RESERVED_6_V << EFUSE_RD_BLK3_RESERVED_6_S) +#define EFUSE_RD_BLK3_RESERVED_6_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_6_S 0 + +/* EFUSE_BLK3_RDATA7_REG register */ + +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_RD_BLK3_RESERVED_7 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_7 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_7_M (EFUSE_RD_BLK3_RESERVED_7_V << EFUSE_RD_BLK3_RESERVED_7_S) +#define EFUSE_RD_BLK3_RESERVED_7_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_7_S 0 + +/* EFUSE_BLK1_WDATA0_REG register */ + +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_BLK1_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN0 0xffffffff +#define EFUSE_BLK1_DIN0_M (EFUSE_BLK1_DIN0_V << EFUSE_BLK1_DIN0_S) +#define EFUSE_BLK1_DIN0_V 0xffffffff +#define EFUSE_BLK1_DIN0_S 0 + +/* EFUSE_BLK1_WDATA1_REG register */ + +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_BLK1_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN1 0xffffffff +#define EFUSE_BLK1_DIN1_M (EFUSE_BLK1_DIN1_V << EFUSE_BLK1_DIN1_S) +#define EFUSE_BLK1_DIN1_V 0xffffffff +#define EFUSE_BLK1_DIN1_S 0 + +/* EFUSE_BLK1_WDATA2_REG register */ + +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_BLK1_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN2 0xffffffff +#define EFUSE_BLK1_DIN2_M (EFUSE_BLK1_DIN2_V << EFUSE_BLK1_DIN2_S) +#define EFUSE_BLK1_DIN2_V 0xffffffff +#define EFUSE_BLK1_DIN2_S 0 + +/* EFUSE_BLK1_WDATA3_REG register */ + +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_BLK1_DIN3 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN3 0xffffffff +#define EFUSE_BLK1_DIN3_M (EFUSE_BLK1_DIN3_V << EFUSE_BLK1_DIN3_S) +#define EFUSE_BLK1_DIN3_V 0xffffffff +#define EFUSE_BLK1_DIN3_S 0 + +/* EFUSE_BLK1_WDATA4_REG register */ + +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_BLK1_DIN4 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN4 0xffffffff +#define EFUSE_BLK1_DIN4_M (EFUSE_BLK1_DIN4_V << EFUSE_BLK1_DIN4_S) +#define EFUSE_BLK1_DIN4_V 0xffffffff +#define EFUSE_BLK1_DIN4_S 0 + +/* EFUSE_BLK1_WDATA5_REG register */ + +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_BLK1_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN5 0xffffffff +#define EFUSE_BLK1_DIN5_M (EFUSE_BLK1_DIN5_V << EFUSE_BLK1_DIN5_S) +#define EFUSE_BLK1_DIN5_V 0xffffffff +#define EFUSE_BLK1_DIN5_S 0 + +/* EFUSE_BLK1_WDATA6_REG register */ + +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_BLK1_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN6 0xffffffff +#define EFUSE_BLK1_DIN6_M (EFUSE_BLK1_DIN6_V << EFUSE_BLK1_DIN6_S) +#define EFUSE_BLK1_DIN6_V 0xffffffff +#define EFUSE_BLK1_DIN6_S 0 + +/* EFUSE_BLK1_WDATA7_REG register */ + +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_BLK1_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN7 0xffffffff +#define EFUSE_BLK1_DIN7_M (EFUSE_BLK1_DIN7_V << EFUSE_BLK1_DIN7_S) +#define EFUSE_BLK1_DIN7_V 0xffffffff +#define EFUSE_BLK1_DIN7_S 0 + +/* EFUSE_BLK2_WDATA0_REG register */ + +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_BLK2_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN0 0xffffffff +#define EFUSE_BLK2_DIN0_M (EFUSE_BLK2_DIN0_V << EFUSE_BLK2_DIN0_S) +#define EFUSE_BLK2_DIN0_V 0xffffffff +#define EFUSE_BLK2_DIN0_S 0 + +/* EFUSE_BLK2_WDATA1_REG register */ + +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_BLK2_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN1 0xffffffff +#define EFUSE_BLK2_DIN1_M (EFUSE_BLK2_DIN1_V << EFUSE_BLK2_DIN1_S) +#define EFUSE_BLK2_DIN1_V 0xffffffff +#define EFUSE_BLK2_DIN1_S 0 + +/* EFUSE_BLK2_WDATA2_REG register */ + +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_BLK2_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN2 0xffffffff +#define EFUSE_BLK2_DIN2_M (EFUSE_BLK2_DIN2_V << EFUSE_BLK2_DIN2_S) +#define EFUSE_BLK2_DIN2_V 0xffffffff +#define EFUSE_BLK2_DIN2_S 0 + +/* EFUSE_BLK2_WDATA3_REG register */ + +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_BLK2_DIN3 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN3 0xffffffff +#define EFUSE_BLK2_DIN3_M (EFUSE_BLK2_DIN3_V << EFUSE_BLK2_DIN3_S) +#define EFUSE_BLK2_DIN3_V 0xffffffff +#define EFUSE_BLK2_DIN3_S 0 + +/* EFUSE_BLK2_WDATA4_REG register */ + +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_BLK2_DIN4 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN4 0xffffffff +#define EFUSE_BLK2_DIN4_M (EFUSE_BLK2_DIN4_V << EFUSE_BLK2_DIN4_S) +#define EFUSE_BLK2_DIN4_V 0xffffffff +#define EFUSE_BLK2_DIN4_S 0 + +/* EFUSE_BLK2_WDATA5_REG register */ + +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_BLK2_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN5 0xffffffff +#define EFUSE_BLK2_DIN5_M (EFUSE_BLK2_DIN5_V << EFUSE_BLK2_DIN5_S) +#define EFUSE_BLK2_DIN5_V 0xffffffff +#define EFUSE_BLK2_DIN5_S 0 + +/* EFUSE_BLK2_WDATA6_REG register */ + +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_BLK2_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN6 0xffffffff +#define EFUSE_BLK2_DIN6_M (EFUSE_BLK2_DIN6_V << EFUSE_BLK2_DIN6_S) +#define EFUSE_BLK2_DIN6_V 0xffffffff +#define EFUSE_BLK2_DIN6_S 0 + +/* EFUSE_BLK2_WDATA7_REG register */ + +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_BLK2_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN7 0xffffffff +#define EFUSE_BLK2_DIN7_M (EFUSE_BLK2_DIN7_V << EFUSE_BLK2_DIN7_S) +#define EFUSE_BLK2_DIN7_V 0xffffffff +#define EFUSE_BLK2_DIN7_S 0 + +/* EFUSE_BLK3_WDATA0_REG register */ + +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_BLK3_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN0 0xffffffff +#define EFUSE_BLK3_DIN0_M (EFUSE_BLK3_DIN0_V << EFUSE_BLK3_DIN0_S) +#define EFUSE_BLK3_DIN0_V 0xffffffff +#define EFUSE_BLK3_DIN0_S 0 + +/* EFUSE_BLK3_WDATA1_REG register */ + +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_BLK3_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN1 0xffffffff +#define EFUSE_BLK3_DIN1_M (EFUSE_BLK3_DIN1_V << EFUSE_BLK3_DIN1_S) +#define EFUSE_BLK3_DIN1_V 0xffffffff +#define EFUSE_BLK3_DIN1_S 0 + +/* EFUSE_BLK3_WDATA2_REG register */ + +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_BLK3_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN2 0xffffffff +#define EFUSE_BLK3_DIN2_M (EFUSE_BLK3_DIN2_V << EFUSE_BLK3_DIN2_S) +#define EFUSE_BLK3_DIN2_V 0xffffffff +#define EFUSE_BLK3_DIN2_S 0 + +/* EFUSE_BLK3_WDATA3_REG register */ + +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; */ + +#define EFUSE_ADC2_TP_HIGH 0x000001ff +#define EFUSE_ADC2_TP_HIGH_M (EFUSE_ADC2_TP_HIGH_V << EFUSE_ADC2_TP_HIGH_S) +#define EFUSE_ADC2_TP_HIGH_V 0x000001ff +#define EFUSE_ADC2_TP_HIGH_S 23 + +/* EFUSE_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; */ + +#define EFUSE_ADC2_TP_LOW 0x0000007f +#define EFUSE_ADC2_TP_LOW_M (EFUSE_ADC2_TP_LOW_V << EFUSE_ADC2_TP_LOW_S) +#define EFUSE_ADC2_TP_LOW_V 0x0000007f +#define EFUSE_ADC2_TP_LOW_S 16 + +/* EFUSE_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; */ + +#define EFUSE_ADC1_TP_HIGH 0x000001ff +#define EFUSE_ADC1_TP_HIGH_M (EFUSE_ADC1_TP_HIGH_V << EFUSE_ADC1_TP_HIGH_S) +#define EFUSE_ADC1_TP_HIGH_V 0x000001ff +#define EFUSE_ADC1_TP_HIGH_S 7 + +/* EFUSE_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; */ + +#define EFUSE_ADC1_TP_LOW 0x0000007f +#define EFUSE_ADC1_TP_LOW_M (EFUSE_ADC1_TP_LOW_V << EFUSE_ADC1_TP_LOW_S) +#define EFUSE_ADC1_TP_LOW_V 0x0000007f +#define EFUSE_ADC1_TP_LOW_S 0 + +/* EFUSE_BLK3_WDATA4_REG register */ + +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_SECURE_VERSION : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_SECURE_VERSION 0xffffffff +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0xffffffff +#define EFUSE_SECURE_VERSION_S 0 + +/* EFUSE_BLK3_WDATA5_REG register */ + +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_BLK3_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN5 0xffffffff +#define EFUSE_BLK3_DIN5_M (EFUSE_BLK3_DIN5_V << EFUSE_BLK3_DIN5_S) +#define EFUSE_BLK3_DIN5_V 0xffffffff +#define EFUSE_BLK3_DIN5_S 0 + +/* EFUSE_BLK3_WDATA6_REG register */ + +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_BLK3_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN6 0xffffffff +#define EFUSE_BLK3_DIN6_M (EFUSE_BLK3_DIN6_V << EFUSE_BLK3_DIN6_S) +#define EFUSE_BLK3_DIN6_V 0xffffffff +#define EFUSE_BLK3_DIN6_S 0 + +/* EFUSE_BLK3_WDATA7_REG register */ + +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_BLK3_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN7 0xffffffff +#define EFUSE_BLK3_DIN7_M (EFUSE_BLK3_DIN7_V << EFUSE_BLK3_DIN7_S) +#define EFUSE_BLK3_DIN7_V 0xffffffff +#define EFUSE_BLK3_DIN7_S 0 + +/* EFUSE_CLK_REG register */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_CLK_EN : RW; bitpos: [16]; default: 0; */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_CLK_SEL1 : RW; bitpos: [15:8]; default: 64; */ + +#define EFUSE_CLK_SEL1 0x000000ff +#define EFUSE_CLK_SEL1_M (EFUSE_CLK_SEL1_V << EFUSE_CLK_SEL1_S) +#define EFUSE_CLK_SEL1_V 0x000000ff #define EFUSE_CLK_SEL1_S 8 -/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; - * Description: efuse timing configure - */ +/* EFUSE_CLK_SEL0 : RW; bitpos: [7:0]; default: 82; */ -#define EFUSE_CLK_SEL0 0x000000ff -#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V) << \ - (EFUSE_CLK_SEL0_S)) -#define EFUSE_CLK_SEL0_V 0xff -#define EFUSE_CLK_SEL0_S 0 +#define EFUSE_CLK_SEL0 0x000000ff +#define EFUSE_CLK_SEL0_M (EFUSE_CLK_SEL0_V << EFUSE_CLK_SEL0_S) +#define EFUSE_CLK_SEL0_V 0x000000ff +#define EFUSE_CLK_SEL0_S 0 -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) +/* EFUSE_CONF_REG register */ -/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; - * Description: - */ +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0xfc) -#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 -#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 +/* EFUSE_FORCE_NO_WR_RD_DIS : RW; bitpos: [16]; default: 1; */ -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; - * Description: efuse operation code - */ +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (EFUSE_FORCE_NO_WR_RD_DIS_V << EFUSE_FORCE_NO_WR_RD_DIS_S) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x00000001 +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 -#define EFUSE_OP_CODE 0x0000ffff -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << \ - (EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xffff -#define EFUSE_OP_CODE_S 0 +/* EFUSE_OP_CODE : RW; bitpos: [15:0]; default: 0; */ -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) +#define EFUSE_OP_CODE 0x0000ffff +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000ffff +#define EFUSE_OP_CODE_S 0 -/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: - */ +/* EFUSE_STATUS_REG register */ -#define EFUSE_DEBUG 0xffffffff -#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V) << \ - (EFUSE_DEBUG_S)) -#define EFUSE_DEBUG_V 0xffffffff -#define EFUSE_DEBUG_S 0 +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) +/* EFUSE_DEBUG : R; bitpos: [31:0]; default: 0; */ -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: command for program - */ +#define EFUSE_DEBUG 0xffffffff +#define EFUSE_DEBUG_M (EFUSE_DEBUG_V << EFUSE_DEBUG_S) +#define EFUSE_DEBUG_V 0xffffffff +#define EFUSE_DEBUG_S 0 -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 +/* EFUSE_CMD_REG register */ -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: command for read - */ +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 -#define EFUSE_READ_CMD_S 0 +/* EFUSE_PGM_CMD : RW; bitpos: [1]; default: 0; */ -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt raw status - */ +/* EFUSE_READ_CMD : RW; bitpos: [0]; default: 0; */ -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt raw status - */ +/* EFUSE_INT_RAW_REG register */ -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 -#define EFUSE_READ_DONE_INT_RAW_S 0 +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) +/* EFUSE_PGM_DONE_INT_RAW : R; bitpos: [1]; default: 0; */ -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt status - */ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 +/* EFUSE_READ_DONE_INT_RAW : R; bitpos: [0]; default: 0; */ -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt status - */ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 -#define EFUSE_READ_DONE_INT_ST_S 0 +/* EFUSE_INT_ST_REG register */ -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt enable - */ +/* EFUSE_PGM_DONE_INT_ST : R; bitpos: [1]; default: 0; */ -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt enable - */ +/* EFUSE_READ_DONE_INT_ST : R; bitpos: [0]; default: 0; */ -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 -#define EFUSE_READ_DONE_INT_ENA_S 0 +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) +/* EFUSE_INT_ENA_REG register */ -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt clear - */ +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 +/* EFUSE_PGM_DONE_INT_ENA : RW; bitpos: [1]; default: 0; */ -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt clear - */ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 -#define EFUSE_READ_DONE_INT_CLR_S 0 +/* EFUSE_READ_DONE_INT_ENA : RW; bitpos: [0]; default: 0; */ -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; - * Description: - */ +/* EFUSE_INT_CLR_REG register */ -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; - * Description: efuse timing configure - */ +/* EFUSE_PGM_DONE_INT_CLR : W; bitpos: [1]; default: 0; */ -#define EFUSE_DAC_CLK_DIV 0x000000ff -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << \ - (EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xff -#define EFUSE_DAC_CLK_DIV_S 0 +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 -#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) +/* EFUSE_READ_DONE_INT_CLR : W; bitpos: [0]; default: 0; */ -/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; - * Description: the decode result of 3/4 coding scheme has warning - */ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 -#define EFUSE_DEC_WARNINGS 0x00000fff -#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V) << \ - (EFUSE_DEC_WARNINGS_S)) -#define EFUSE_DEC_WARNINGS_V 0xfff -#define EFUSE_DEC_WARNINGS_S 0 +/* EFUSE_DAC_CONF_REG register */ -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; - * Description: - */ +/* EFUSE_DAC_CLK_PAD_SEL : RW; bitpos: [8]; default: 0; */ -#define EFUSE_DATE 0xffffffff -#define EFUSE_DATE_M ((EFUSE_DATE_V) << \ - (EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xffffffff -#define EFUSE_DATE_S 0 +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_CLK_DIV : RW; bitpos: [7:0]; default: 40; */ + +#define EFUSE_DAC_CLK_DIV 0x000000ff +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000ff +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_DEC_STATUS_REG register */ + +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_DEC_WARNINGS : R; bitpos: [11:0]; default: 0; */ + +#define EFUSE_DEC_WARNINGS 0x00000fff +#define EFUSE_DEC_WARNINGS_M (EFUSE_DEC_WARNINGS_V << EFUSE_DEC_WARNINGS_S) +#define EFUSE_DEC_WARNINGS_V 0x00000fff +#define EFUSE_DEC_WARNINGS_S 0 + +/* EFUSE_DATE_REG register */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_DATE : RW; bitpos: [31:0]; default: 369370624; */ + +#define EFUSE_DATE 0xffffffff +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xffffffff +#define EFUSE_DATE_S 0 #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h b/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h new file mode 100644 index 0000000000..7b4025cba8 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/* Write disable bits */ + +#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +/* Read disable bits for efuse blocks 1-3 */ + +#define EFUSE_RD_DIS_BLK1 (1 << 16) +#define EFUSE_RD_DIS_BLK2 (1 << 17) +#define EFUSE_RD_DIS_BLK3 (1 << 18) + +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ +#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 1128e4a49c..896c9a7afd 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -29,6 +29,8 @@ #include #include "xtensa_attr.h" +#include "hardware/esp32_efuse.h" + #include /**************************************************************************** @@ -366,8 +368,6 @@ #define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */ #define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */ -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) /* Interrupt cpu using table */ @@ -430,14 +430,6 @@ #define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) #define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) -/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -#define APB_CTRL_PRE_DIV_CNT 0x000003ff -#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \ - (APB_CTRL_PRE_DIV_CNT_S)) -#define APB_CTRL_PRE_DIV_CNT_V 0x3ff -#define APB_CTRL_PRE_DIV_CNT_S 0 - #define I2C_BBPLL_IR_CAL_DELAY 0 #define I2C_BBPLL_IR_CAL_EXT_CAP 1 #define I2C_BBPLL_OC_ENB_FCAL 4 @@ -487,84 +479,6 @@ extern int rom_i2c_writereg(int block, int block_id, int reg_add, #define BBPLL_OC_ENB_VCON_VAL 0x00 #define BBPLL_BBADC_CAL_7_0_VAL 0x00 -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) - -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ - -/* description: This field stores the voltage level for - * CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) - */ - -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 - -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ - -/* description: read for sdio_force */ - -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 - -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ - -/* description: read for XPD_SDIO_REG */ - -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 - -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ - -/* description: read for SDIO_TIEH */ - -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 - -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ - -/* description: If set, this bit indicates that - * BLOCK3[143:96] is reserved for internal use - */ - -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 - -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 - -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 - -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ - -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 - #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)