diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.h b/arch/arm/src/lpc17xx/lpc17_pwm.h
index b689a0779a..6db271a47e 100755
--- a/arch/arm/src/lpc17xx/lpc17_pwm.h
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.h
@@ -75,27 +75,27 @@
 
 /* Register addresses ***************************************************************/
 
-#define LPC17_PWM1_IR          (LPVC17_PWM1_BASE+LPC17_PWM_IR_OFFSET)
-#define LPC17_PWM1_TCR         (LPVC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET)
-#define LPC17_PWM1_TC          (LPVC17_PWM1_BASE+LPC17_PWM_TC_OFFSET)
-#define LPC17_PWM1_PR          (LPVC17_PWM1_BASE+LPC17_PWM_PR_OFFSET)
-#define LPC17_PWM1_PC          (LPVC17_PWM1_BASE+LPC17_PWM_PC_OFFSET)
-#define LPC17_PWM1_MCR         (LPVC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET)
-#define LPC17_PWM1_MR0         (LPVC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET)
-#define LPC17_PWM1_MR1         (LPVC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET)
-#define LPC17_PWM1_MR2         (LPVC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET)
-#define LPC17_PWM1_MR3         (LPVC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET)
-#define LPC17_PWM1_MR4         (LPVC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET)
-#define LPC17_PWM1_MR5         (LPVC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET)
-#define LPC17_PWM1_MR6         (LPVC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET)
-#define LPC17_PWM1_CCR         (LPVC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET)
-#define LPC17_PWM1_CR0         (LPVC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET)
-#define LPC17_PWM1_CR1         (LPVC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET)
-#define LPC17_PWM1_CR2         (LPVC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET)
-#define LPC17_PWM1_CR3         (LPVC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET)
-#define LPC17_PWM1_PCR         (LPVC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET)
-#define LPC17_PWM1_LER         (LPVC17_PWM1_BASE+LPC17_PWM_LER_OFFSET)
-#define LPC17_PWM1_CTCR        (LPVC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET)
+#define LPC17_PWM1_IR          (LPC17_PWM1_BASE+LPC17_PWM_IR_OFFSET)
+#define LPC17_PWM1_TCR         (LPC17_PWM1_BASE+LPC17_PWM_TCR_OFFSET)
+#define LPC17_PWM1_TC          (LPC17_PWM1_BASE+LPC17_PWM_TC_OFFSET)
+#define LPC17_PWM1_PR          (LPC17_PWM1_BASE+LPC17_PWM_PR_OFFSET)
+#define LPC17_PWM1_PC          (LPC17_PWM1_BASE+LPC17_PWM_PC_OFFSET)
+#define LPC17_PWM1_MCR         (LPC17_PWM1_BASE+LPC17_PWM_MCR_OFFSET)
+#define LPC17_PWM1_MR0         (LPC17_PWM1_BASE+LPC17_PWM_MR0_OFFSET)
+#define LPC17_PWM1_MR1         (LPC17_PWM1_BASE+LPC17_PWM_MR1_OFFSET)
+#define LPC17_PWM1_MR2         (LPC17_PWM1_BASE+LPC17_PWM_MR2_OFFSET)
+#define LPC17_PWM1_MR3         (LPC17_PWM1_BASE+LPC17_PWM_MR3_OFFSET)
+#define LPC17_PWM1_MR4         (LPC17_PWM1_BASE+LPC17_PWM_MR4_OFFSET)
+#define LPC17_PWM1_MR5         (LPC17_PWM1_BASE+LPC17_PWM_MR5_OFFSET)
+#define LPC17_PWM1_MR6         (LPC17_PWM1_BASE+LPC17_PWM_MR6_OFFSET)
+#define LPC17_PWM1_CCR         (LPC17_PWM1_BASE+LPC17_PWM_CCR_OFFSET)
+#define LPC17_PWM1_CR0         (LPC17_PWM1_BASE+LPC17_PWM_CR0_OFFSET)
+#define LPC17_PWM1_CR1         (LPC17_PWM1_BASE+LPC17_PWM_CR1_OFFSET)
+#define LPC17_PWM1_CR2         (LPC17_PWM1_BASE+LPC17_PWM_CR2_OFFSET)
+#define LPC17_PWM1_CR3         (LPC17_PWM1_BASE+LPC17_PWM_CR3_OFFSET)
+#define LPC17_PWM1_PCR         (LPC17_PWM1_BASE+LPC17_PWM_PCR_OFFSET)
+#define LPC17_PWM1_LER         (LPC17_PWM1_BASE+LPC17_PWM_LER_OFFSET)
+#define LPC17_PWM1_CTCR        (LPC17_PWM1_BASE+LPC17_PWM_CTCR_OFFSET)
 
 /* Register bit definitions *********************************************************/
 /* Registers holding 32-bit numeric values (no bit field definitions):