SAMV7 SPI: Revise support for Peripheral Chip Select Decoding to address up to 15 slaved
This commit is contained in:
Frank Benkert
Gregory Nutt
parent
f1a196cd40
commit
2980985933
@ -738,6 +738,12 @@ endchoice # SPI1 Configuration
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if SAMV7_SPI_MASTER
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comment "SPI Master Configuration"
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config SAMV7_SPI_CS_DECODING
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bool "SPI Peripheral Chip Select Decoding"
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default n
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---help---
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Use Peripheral Chip Select Decoding on SPI Master
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config SAMV7_SPI_DMA
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bool "SPI DMA"
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default n
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@ -297,13 +297,24 @@ static void spi_recvblock(struct spi_dev_s *dev, void *buffer,
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* Private Data
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****************************************************************************/
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/* This array maps chip select numbers (0-3) to CSR register offsets */
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/* This array maps chip select numbers (0-3 or 1-15) to CSR register offsets */
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#if defined(CONFIG_SAMV7_SPI_CS_DECODING)
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static const uint8_t g_csroffset[16] =
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{
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0, /* the CS counts from 1 to 15 */
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SAM_SPI_CSR0_OFFSET, SAM_SPI_CSR0_OFFSET, SAM_SPI_CSR0_OFFSET, SAM_SPI_CSR0_OFFSET,
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SAM_SPI_CSR1_OFFSET, SAM_SPI_CSR1_OFFSET, SAM_SPI_CSR1_OFFSET, SAM_SPI_CSR1_OFFSET,
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SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR2_OFFSET,
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SAM_SPI_CSR3_OFFSET, SAM_SPI_CSR3_OFFSET, SAM_SPI_CSR3_OFFSET
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};
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#else
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static const uint8_t g_csroffset[4] =
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{
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SAM_SPI_CSR0_OFFSET, SAM_SPI_CSR1_OFFSET,
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SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR3_OFFSET
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};
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#endif
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#ifdef CONFIG_SAMV7_SPI0_MASTER
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/* SPI0 driver operations */
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@ -581,7 +592,11 @@ static inline void spi_flush(struct sam_spidev_s *spi)
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* registers. A chip select number is used for indexing and identifying
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* chip selects. However, the chip select information is represented by
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* a bit set in the SPI registers. This function maps those chip select
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* numbers to the correct bit set:
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* numbers to the correct bit set.
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*
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* The SAMx7 Processors can handle the chip selects in two different modes.
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* The first and default mode assigns one of the four chip select pins
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* to one hardware slave. In this mode the function behaviors like:
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*
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* CS Returned Spec Effective
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* No. PCS Value NPCS
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@ -591,17 +606,28 @@ static inline void spi_flush(struct sam_spidev_s *spi)
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* 2 0011 x011 1011
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* 3 0111 0111 0111
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*
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* The second mode, activated via CONFIG_SAMV7_SPI_CS_DECODING uses the four
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* chip select pins in "encoded mode" which means, that up to 15 slaves can
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* be selected via an additional multiplex electronic to decode the values
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* represented by the four lines. In that mode this function returns the
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* Bitmask the chip select number represents itself.
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*
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* Input Parameters:
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* spics - Device-specific state data
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*
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* Returned Value:
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* None
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* Bitmask the pcs part of the SPI data transfer register should be switched
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* to for the chip select used.
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*
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****************************************************************************/
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static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics)
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{
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#ifndef CONFIG_SAMV7_SPI_CS_DECODING
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return ((uint32_t)1 << (spics->cs)) - 1;
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#else
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return spics->cs;
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#endif
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}
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/****************************************************************************
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@ -1855,7 +1881,14 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
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/* Configure the SPI mode register */
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#if defined(CONFIG_SAMV7_SPI_CS_DECODING)
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/* Enable Peripheral Chip Select Decoding? */
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spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCSDEC,
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SAM_SPI_MR_OFFSET);
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#else
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spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR_OFFSET);
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#endif
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/* And enable the SPI */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_spi.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -63,26 +63,72 @@
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* sam_spibus_initialize().
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*/
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#define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */
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#define __SPI_CS_MASK (3 << __SPI_CS_SHIFT)
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# define __SPI_CS0 (0 << __SPI_CS_SHIFT)
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# define __SPI_CS1 (1 << __SPI_CS_SHIFT)
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# define __SPI_CS2 (2 << __SPI_CS_SHIFT)
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# define __SPI_CS3 (3 << __SPI_CS_SHIFT)
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#define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */
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#define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT)
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# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */
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# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */
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#ifdef CONFIG_SAMV7_SPI_CS_DECODING
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#define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0)
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#define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1)
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#define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2)
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#define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3)
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# define __SPI_CS_SHIFT (0) /* Bits 0-3: SPI chip select number */
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# define __SPI_CS_MASK (15 << __SPI_CS_SHIFT)
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#define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0)
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#define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1)
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#define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2)
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#define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3)
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# define __SPI_SPI_SHIFT (4) /* Bit 4: SPI controller number */
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# define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT)
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# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */
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# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */
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# define SPI0_CS1 (__SPI_SPI0 | 1)
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# define SPI0_CS2 (__SPI_SPI0 | 2)
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# define SPI0_CS3 (__SPI_SPI0 | 3)
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# define SPI0_CS4 (__SPI_SPI0 | 4)
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# define SPI0_CS5 (__SPI_SPI0 | 5)
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# define SPI0_CS6 (__SPI_SPI0 | 6)
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# define SPI0_CS7 (__SPI_SPI0 | 7)
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# define SPI0_CS8 (__SPI_SPI0 | 8)
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# define SPI0_CS9 (__SPI_SPI0 | 9)
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# define SPI0_CS10 (__SPI_SPI0 | 10)
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# define SPI0_CS11 (__SPI_SPI0 | 11)
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# define SPI0_CS12 (__SPI_SPI0 | 12)
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# define SPI0_CS13 (__SPI_SPI0 | 13)
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# define SPI0_CS14 (__SPI_SPI0 | 14)
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# define SPI0_CS15 (__SPI_SPI0 | 15)
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# define SPI1_CS1 (__SPI_SPI1 | 1)
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# define SPI1_CS2 (__SPI_SPI1 | 2)
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# define SPI1_CS3 (__SPI_SPI1 | 3)
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# define SPI1_CS4 (__SPI_SPI1 | 4)
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# define SPI1_CS5 (__SPI_SPI1 | 5)
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# define SPI1_CS6 (__SPI_SPI1 | 6)
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# define SPI1_CS7 (__SPI_SPI1 | 7)
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# define SPI1_CS8 (__SPI_SPI1 | 8)
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# define SPI1_CS9 (__SPI_SPI1 | 9)
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# define SPI1_CS10 (__SPI_SPI1 | 10)
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# define SPI1_CS11 (__SPI_SPI1 | 11)
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# define SPI1_CS12 (__SPI_SPI1 | 12)
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# define SPI1_CS13 (__SPI_SPI1 | 13)
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# define SPI1_CS14 (__SPI_SPI1 | 14)
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# define SPI1_CS15 (__SPI_SPI1 | 15)
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#else /* CONFIG_SAMV7_SPI_CS_DECODING */
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# define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */
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# define __SPI_CS_MASK (3 << __SPI_CS_SHIFT)
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# define __SPI_CS0 (0 << __SPI_CS_SHIFT)
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# define __SPI_CS1 (1 << __SPI_CS_SHIFT)
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# define __SPI_CS2 (2 << __SPI_CS_SHIFT)
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# define __SPI_CS3 (3 << __SPI_CS_SHIFT)
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# define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */
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# define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT)
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# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */
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# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */
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# define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0)
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# define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1)
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# define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2)
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# define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3)
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# define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0)
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# define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1)
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# define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2)
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# define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3)
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#endif /* CONFIG_SAMV7_SPI_CS_DECODING */
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/****************************************************************************
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* Public Types
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