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More fixes to problems noted by cppcheck. Some are kind of risky; some are real bugs.

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This commit is contained in:
Gregory Nutt 2014-11-25 13:15:09 -06:00
parent e0fc5a86c8
commit 2994448d85
37 changed files with 156 additions and 140 deletions
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24
arch/arm/src/c5471/c5471_serial.c
View File

@ -84,20 +84,20 @@ struct uart_regs_s
struct up_dev_s
{
unsigned int uartbase; /* Base address of UART registers */
unsigned int baud_base; /* Base baud for conversions */
unsigned int baud; /* Configured baud */
uint8_t xmit_fifo_size; /* Size of transmit FIFO */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
unsigned int uartbase; /* Base address of UART registers */
unsigned int baud_base; /* Base baud for conversions */
unsigned int baud; /* Configured baud */
uint8_t xmit_fifo_size; /* Size of transmit FIFO */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
#ifdef CONFIG_UART_HWFLOWCONTROL
bool flowcontrol; /* true: Hardware flow control
* is enabled. */
bool flowcontrol; /* true: Hardware flow control
* is enabled. */
#endif
bool stopbits2; /* true: Configure with 2
* stop bits instead of 1 */
struct uart_regs_s regs; /* Shadow copy of readonly regs */
bool stopbits2; /* true: Configure with 2
* stop bits instead of 1 */
struct uart_regs_s regs; /* Shadow copy of readonly regs */
};
/****************************************************************************

26
arch/arm/src/calypso/calypso_serial.c
View File

@ -94,23 +94,23 @@ struct uart_regs_s
struct up_dev_s
{
unsigned int uartbase; /* Base address of UART registers */
unsigned int baud_base; /* Base baud for conversions */
unsigned int baud; /* Configured baud */
uint8_t xmit_fifo_size; /* Size of transmit FIFO */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
unsigned int uartbase; /* Base address of UART registers */
unsigned int baud_base; /* Base baud for conversions */
unsigned int baud; /* Configured baud */
uint8_t xmit_fifo_size; /* Size of transmit FIFO */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
#ifdef CONFIG_UART_HWFLOWCONTROL
bool flowcontrol; /* true: Hardware flow control
* is enabled. */
bool flowcontrol; /* true: Hardware flow control
* is enabled. */
#endif
bool stopbits2; /* true: Configure with 2
* stop bits instead of 1 */
struct uart_regs_s regs; /* Shadow copy of readonly regs */
bool stopbits2; /* true: Configure with 2
* stop bits instead of 1 */
struct uart_regs_s regs; /* Shadow copy of readonly regs */
#ifdef CONFIG_SERCOMM_CONSOLE
bool sercomm; /* Call sercomm in interrupt if true */
bool sercomm; /* Call sercomm in interrupt if true */
#endif
};

2
arch/arm/src/efm32/efm32_dma.c
View File

@ -717,7 +717,7 @@ void efm32_dmastop(DMA_HANDLE handle)
uint32_t regval;
uint32_t bit;
DEBUGASSERT(dmach && dmach);
DEBUGASSERT(dmach);
bit = 1 << dmach->chan;
/* Disable the channel */

2
arch/arm/src/str71x/str71x_serial.c
View File

@ -631,8 +631,8 @@ static int up_attach(struct uart_dev_s *dev)
/* Set the uart interrupt priority (the default value is one) */
up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
}
#endif
}
return ret;
}

3
arch/arm/src/tiva/tiva_ssi.c
View File

@ -951,7 +951,6 @@ static int ssi_interrupt(int irq, void *context)
{
struct tiva_ssidev_s *priv = ssi_mapirq(irq);
uint32_t regval;
int ntxd;
DEBUGASSERT(priv != NULL);
@ -975,7 +974,7 @@ static int ssi_interrupt(int irq, void *context)
/* Handle outgoing Tx FIFO transfers */
ntxd = ssi_performtx(priv);
(void)ssi_performtx(priv);
/* Handle incoming Rx FIFO transfers */

4
arch/avr/src/avr/up_spi.c
View File

@ -267,6 +267,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
actual = BOARD_CPU_CLOCK / 128;
}
#warning REVIST: spcr/spsr are never used
/* Save the frequency setting */
#ifndef CONFIG_SPI_OWNBUS
@ -531,6 +533,8 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
#ifndef CONFIG_SPI_OWNBUS
sem_init(&priv->exclsem, 0, 1);
#endif
irqrestore(flags);
return &priv->spidev;
}
#endif /* CONFIG_AVR_SPI */

3
arch/z80/src/ez80/ez80_spi.c
View File

@ -359,13 +359,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
size_t buflen)
{
FAR const uint8_t *ptr = (FAR const uint8_t*)buffer;
uint8_t response;
/* Loop while there are bytes remaining to be sent */
while (buflen-- > 0)
{
response = spi_transfer(*ptr++);
(void)spi_transfer(*ptr++);
}
}

13
arch/z80/src/ez80/ez80_timerisr.c
View File

@ -76,16 +76,14 @@
int up_timerisr(int irq, chipreg_t *regs)
{
volatile uint8_t reg;
/* Read the appropropriate timer0 registr to clear the interrupt */
/* Read the appropriate timer0 register to clear the interrupt */
#ifdef _EZ80F91
reg = inp(EZ80_TMR0_IIR);
(void)inp(EZ80_TMR0_IIR);
#else
/* _EZ80190, _EZ80L92, _EZ80F92, _EZ80F93 */
reg = inp(EZ80_TMR0_CTL);
(void)inp(EZ80_TMR0_CTL);
#endif
/* Process timer interrupt */
@ -113,7 +111,6 @@ int up_timerisr(int irq, chipreg_t *regs)
void up_timer_initialize(void)
{
uint16_t reload;
uint8_t reg;
/* Disable the timer */
@ -149,9 +146,9 @@ void up_timer_initialize(void)
/* Clear any pending timer interrupts */
#if defined(_EZ80F91)
reg = inp(EZ80_TMR0_IIR);
(void)inp(EZ80_TMR0_IIR);
#elif defined(_EZ80L92) || defined(_EZ80F92) ||defined(_EZ80F93)
reg = inp(EZ80_TMR0_CTL);
(void)inp(EZ80_TMR0_CTL);
#endif
/* Configure and enable the timer */

2
arch/z80/src/z180/z180_scc.c
View File

@ -575,8 +575,6 @@ static bool z180_txempty(struct uart_dev_s *dev)
void up_serialinit(void)
{
uint8_t regval;
/* Make sure that all UART interrupts are disabled */
#warning "Missing logic"

8
arch/z80/src/z180/z180_timerisr.c
View File

@ -94,16 +94,14 @@
int up_timerisr(int irq, chipreg_t *regs)
{
volatile uint8_t regval;
/* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt
* request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and
* the higher or lower byte of TMDR0 is read."
*/
regval = inp(Z180_PRT_TCR);
regval = inp(Z180_PRT0_DRL);
regval = inp(Z180_PRT0_DRH);
(void)inp(Z180_PRT_TCR);
(void)inp(Z180_PRT0_DRL);
(void)inp(Z180_PRT0_DRH);
/* Process timer interrupt */

3
arch/z80/src/z8/z8_lowuart.c
View File

@ -75,9 +75,12 @@ extern uint32_t get_freq(void);
void up_lowserialinit(void)
{
#if defined(CONFIG_UART0_SERIAL_CONSOLE) || \
(defined(EZ8_UART1) && defined(CONFIG_UART1_SERIAL_CONSOLE))
uint32_t freq = get_freq();
uint16_t brg;
uint8_t val;
#endif
#ifdef CONFIG_UART0_SERIAL_CONSOLE
/* Set the baudrate */

34
audio/pcm_decode.c
View File

@ -442,8 +442,8 @@ static void pcm_subsample_configure(FAR struct pcm_decode_s *priv,
if (priv->subsample == AUDIO_SUBSAMPLE_NONE)
{
/* Ignore request to stop fast forwarding if we are already
* fast forwarding.
/* Ignore request to stop fast forwarding if we are already playing
* normally.
*/
if (subsample != AUDIO_SUBSAMPLE_NONE)
@ -460,24 +460,11 @@ static void pcm_subsample_configure(FAR struct pcm_decode_s *priv,
}
}
/* 2. Were already fast forwarding and we have been asked to change the
* sub-sampling rate.
*/
else if (subsample != AUDIO_SUBSAMPLE_NONE)
{
/* Just save the current subsample setting. It will take effect
* on the next audio buffer that we receive.
*/
priv->subsample = subsample;
}
/* 3. We were already fast forwarding and we have been asked to return to
/* 2. We were already fast forwarding and we have been asked to return to
* normal play.
*/
else if (subsample != AUDIO_SUBSAMPLE_NONE)
else if (subsample == AUDIO_SUBSAMPLE_NONE)
{
audvdbg("Stop sub-sampling\n");
@ -489,6 +476,19 @@ static void pcm_subsample_configure(FAR struct pcm_decode_s *priv,
priv->skip = 0;
priv->subsample = AUDIO_SUBSAMPLE_NONE;
}
/* 3. Were already fast forwarding and we have been asked to change the
* sub-sampling rate.
*/
else if (priv->subsample != subsample)
{
/* Just save the new subsample setting. It will take effect on the
* next audio buffer that we receive.
*/
priv->subsample = subsample;
}
}
#endif

3
configs/ea3131/src/up_mem.c
View File

@ -157,7 +157,6 @@
static void lpc31_sdraminitialize(void)
{
uint32_t tmp;
uint32_t regval;
/* These run-time calculations can be reduced dramatically if hclk is
@ -266,7 +265,7 @@ static void lpc31_sdraminitialize(void)
* 16bit mode
*/
tmp = getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
(void)getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
LPC31_MPMC_DYNCONFIG0);

3
configs/ea3152/src/up_mem.c
View File

@ -157,7 +157,6 @@
static void lpc31_sdraminitialize(void)
{
uint32_t tmp;
uint32_t regval;
/* These run-time calculations can be reduced dramatically if hclk is
@ -266,7 +265,7 @@ static void lpc31_sdraminitialize(void)
* 16bit mode
*/
tmp = getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
(void)getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 13));
putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16),
LPC31_MPMC_DYNCONFIG0);

2
configs/mikroe-stm32f4/src/up_clockconfig.c
View File

@ -146,5 +146,5 @@ void stm32_board_clockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
;
#endif
}
#endif

4
configs/mikroe-stm32f4/src/up_nsh.c
View File

@ -169,7 +169,11 @@ int nsh_archinitialize(void)
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
#endif
#if defined(NSH_HAVEMMCSD) || defined(HAVE_USBHOST) || \
defined(HAVE_USBMONITOR) || defined(CONFIG_LCD_MIO283QT2) || \
defined(CONFIG_LCD_MIO283QT9A)
int ret;
#endif
/* Configure SPI-based devices */

1
configs/mikroe-stm32f4/src/up_touchscreen.c
View File

@ -435,7 +435,6 @@ static void tc_adc_init(void)
regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED;
regval |= LCD_YD_CHANNEL;
tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval);
regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET);
/* Set the number of conversions = 1 */

4
configs/mx1ads/src/up_boot.c
View File

@ -101,7 +101,7 @@ void imx_boardinitialize(void)
imxgpio_configprimary(GPIOA, 21);
imxgpio_configprimary(GPIOA, 22);
regval = getreg32(IMX_CS4_VSECTION + 0x0c);
regval = getreg32(IMX_CS4_VSECTION + 0x0c);
(void)getreg32(IMX_CS4_VSECTION + 0x0c);
(void)getreg32(IMX_CS4_VSECTION + 0x0c);
#endif
}

3
configs/olimex-lpc-h3131/src/lpc31_mem.c
View File

@ -137,7 +137,6 @@ static uint32_t lpc31_ns2clk(uint32_t ns, uint32_t hclk2)
static inline void lpc31_sdraminitialize(void)
{
uint32_t tmp;
uint32_t regval;
/* These run-time calculations can be reduced dramatically if hclk is
@ -254,7 +253,7 @@ static inline void lpc31_sdraminitialize(void)
* 16bit mode
*/
tmp = getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 12));
(void)getreg32(LPC31_EXTSDRAM0_VSECTION | (0x23 << 12));
/* Select normal operating mode */

6
configs/olimex-stm32-h405/src/stm32_nsh.c
View File

@ -59,6 +59,10 @@
* Pre-Processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2)
# undef CONFIG_CAN
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@ -84,7 +88,7 @@ int nsh_archinitialize(void)
int ret;
#endif
#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2))
#ifdef CONFIG_CAN
/* Configure on-board CAN if CAN support has been selected. */
ret = stm32_can_initialize();

9
configs/open1788/src/lpc17_sdraminitialize.c
View File

@ -109,11 +109,6 @@
void open1788_sdram_initialize(void)
{
uint32_t regval;
#ifdef CONFIG_LPC17_SDRAM_16BIT
volatile uint16_t dummy;
#else
volatile uint32_t dummy;
#endif
int i;
/* Reconfigure delays:
@ -211,9 +206,9 @@ void open1788_sdram_initialize(void)
LPC17_EMC_DYNAMICCONTROL);
#ifdef CONFIG_LPC17_SDRAM_16BIT
dummy = getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */
(void)getreg16(SDRAM_BASE | (0x33 << 12)); /* 8 burst, 3 CAS latency */
#elif defined CONFIG_LPC17_SDRAM_32BIT
dummy = getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */
(void)getreg32(SDRAM_BASE | (0x32 << 13)); /* 4 burst, 3 CAS latency */
#endif
/* Issue NORMAL command */

4
configs/shenzhou/src/up_ili93xx.c
View File

@ -1197,14 +1197,14 @@ static int stm32_setpower(struct lcd_dev_s *dev, int power)
else
#endif
#ifndef CONFIG_STM32_ILI9320_DISABLE
if (priv->type == LCD_TYPE_ILI9300)
if (priv->type == LCD_TYPE_ILI9320)
{
stm32_writereg(priv, LCD_REG_7, 0x0173);
}
else
#endif
#ifndef CONFIG_STM32_ILI9321_DISABLE
if (priv->type == LCD_TYPE_ILI9300)
if (priv->type == LCD_TYPE_ILI9321)
{
stm32_writereg(priv, LCD_REG_7, 0x0173);
}

3
configs/stm32f4discovery/src/stm32_usb.c
View File

@ -170,7 +170,10 @@ void stm32_usbinitialize(void)
int stm32_usbhost_initialize(void)
{
int pid;
#if defined(CONFIG_USBHOST_MSC) || defined(CONFIG_USBHOST_HIDKBD) || \
defined(CONFIG_USBHOST_HIDMOUSE)
int ret;
#endif
/* First, register all of the class drivers needed to support the drivers
* that we care about:

7
configs/vsn/src/sif.c
View File

@ -577,7 +577,8 @@ int sif_main(int argc, char *argv[])
}
else if (status != 0) {
if (stpage != 0xFFFF) {
printf("Free Range:\t%d\t-\t%d\n", stpage, page-2);
printf("Free Range:\t%lu\t-\t%lu\n",
(unsigned long)stpage, (unsigned long)(page-2));
stpage = 0xFFFF;
}
}
@ -594,8 +595,8 @@ int sif_main(int argc, char *argv[])
size_t page = atoi(argv[2]);
size_t addr = page * up_progmem_pagesize(page);
printf("Write result: %d (writing to address %xh)\n",
up_progmem_write(addr, "Test", 4), addr);
printf("Write result: %d (writing to address %lxh)\n",
up_progmem_write(addr, "Test", 4), (unsigned long)addr);
return 0;
}
else if (!strcmp(argv[1], "i2c") && argc == 3) {

24
crypto/crypto.c
View File

@ -66,21 +66,31 @@
void up_cryptoinitialize(void)
{
int res = OK;
#if defined(CONFIG_CRYPTO_AES) || defined(CONFIG_CRYPTO_ALGTEST)
int res;
#if defined(CONFIG_CRYPTO_AES)
#ifdef CONFIG_CRYPTO_AES
res = up_aesinitialize();
if (res)
return res;
{
return res;
}
#endif
#if defined(CONFIG_CRYPTO_ALGTEST)
#if CONFIG_CRYPTO_ALGTEST
res = crypto_test();
if (res)
cryptlldbg("crypto test failed\n");
{
cryptlldbg("crypto test failed\n");
}
else
cryptllvdbg("crypto test OK\n");
{
cryptllvdbg("crypto test OK\n");
}
#endif
return res;
}
#else
return OK;
#endif
}

14
drivers/analog/ads1255.c
View File

@ -168,23 +168,25 @@ static uint8_t getspsreg(uint16_t sps)
{
static const unsigned short sps_tab[]=
{
3,7,12,20,27,40,55,80,300,750,1500,3000,5000,10000,20000,65535,
3, 7, 12, 20, 27, 40, 55, 80,
300, 750, 1500, 3000, 5000, 10000, 20000, 65535,
};
static const unsigned char sps_reg[]=
{
0x03,0x13,0x23,0x33,0x43,0x53,0x63,0x72,0x82,0x92,0xa1,0xb0,0xc0,0xd0,0xe0,0xf0,
0x03, 0x13, 0x23, 0x33, 0x43, 0x53, 0x63, 0x72,
0x82, 0x92, 0xa1, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0,
};
int i;
for (i=0; i<16; i++)
for (i = 0; i < 16; i++)
{
if (sps<sps_tab[i])
if (sps < sps_tab[i])
{
break;
return sps_reg[i];
}
}
return sps_reg[i];
return sps_reg[15];
}
/****************************************************************************

2
drivers/audio/wm8904.c
View File

@ -1685,7 +1685,7 @@ static int wm8904_enqueuebuffer(FAR struct audio_lowerhalf_s *dev,
{
FAR struct wm8904_dev_s *priv = (FAR struct wm8904_dev_s *)dev;
struct audio_msg_s term_msg;
int ret = -EAGAIN;
int ret;
audvdbg("Enqueueing: apb=%p curbyte=%d nbytes=%d flags=%04x\n",
apb, apb->curbyte, apb->nbytes, apb->flags);

2
drivers/input/mxt.c
View File

@ -750,6 +750,8 @@ static void mxt_button_event(FAR struct mxt_dev_s *priv,
button = (msg->body[0] & mask) == 0;
/* Now what? */
UNUSED(button);
}
}
}

8
drivers/lcd/mio283qt9a.c
View File

@ -719,11 +719,13 @@ static int mio283qt9a_setcontrast(FAR struct lcd_dev_s *dev, unsigned int contra
static inline int mio283qt9a_hwinitialize(FAR struct mio283qt9a_dev_s *priv)
{
FAR struct mio283qt9a_lcd_s *lcd = priv->lcd;
#ifndef CONFIG_LCD_NOGETRUN
#if !defined(CONFIG_LCD_NOGETRUN) || defined(CONFIG_DEBUG_LCD)
uint16_t id_a;
uint16_t id_b;
uint16_t id_c;
uint16_t id_d;
#endif
#ifdef CONFIG_DEBUG_LCD
uint16_t id_e;
#endif
int ret;
@ -741,6 +743,8 @@ static inline int mio283qt9a_hwinitialize(FAR struct mio283qt9a_dev_s *priv)
id_d = lcd->read(lcd);
lcdvdbg("LCD ID: %04x %04x %04x %04x\n", id_a, id_b, id_c, id_d);
UNUSED(id_a);
UNUSED(id_b);
/* Check if the ID is for the ILI9341 */
@ -773,6 +777,7 @@ static inline int mio283qt9a_hwinitialize(FAR struct mio283qt9a_dev_s *priv)
mio283qt9a_putreg(lcd, 0x11, 0); /* Sleep out mode */
up_mdelay(25);
#ifdef CONFIG_DEBUG_LCD
/* Read back some info from the panel */
id_a = mio283qt9a_readreg(lcd, 0x04); /* Read display information */
@ -811,6 +816,7 @@ static inline int mio283qt9a_hwinitialize(FAR struct mio283qt9a_dev_s *priv)
id_a = mio283qt9a_readreg(lcd, 0x0f); /* read self diag */
id_b = lcd->read(lcd);
lcdvdbg("Self diag %02x, %02x\n", id_a, id_b);
#endif
ret = OK;
}
#ifndef CONFIG_LCD_NOGETRUN

2
drivers/mtd/rammtd.c
View File

@ -453,7 +453,7 @@ FAR struct mtd_dev_s *rammtd_initialize(FAR uint8_t *start, size_t size)
/* Force the size to be an even number of the erase block size */
nblocks = size / CONFIG_RAMMTD_ERASESIZE;
if (nblocks <= 0)
if (nblocks < 1)
{
fdbg("Need to provide at least one full erase block\n");
return NULL;

6
drivers/mtd/smart.c
View File

@ -836,11 +836,11 @@ static int smart_scan(struct smart_struct_s *dev)
rootdirdev->dev = dev;
rootdirdev->rootdirnum = x;
ret = register_blockdriver(dev->rwbuffer, &g_bops, 0, rootdirdev);
(void)register_blockdriver(dev->rwbuffer, &g_bops, 0, rootdirdev);
/* Inode private data is a reference to the SMART device structure */
ret = register_blockdriver(devname, &g_bops, 0, rootdirdev);
(void)register_blockdriver(devname, &g_bops, 0, rootdirdev);
}
#endif
}
@ -1359,7 +1359,7 @@ static int smart_garbagecollect(struct smart_struct_s *dev)
/* Write the data to the new physical sector location */
ret = MTD_BWRITE(dev->mtd, newsector * dev->mtdBlksPerSector,
(void)MTD_BWRITE(dev->mtd, newsector * dev->mtdBlksPerSector,
dev->mtdBlksPerSector, (uint8_t *) dev->rwbuffer);
/* Commit the sector */

2
drivers/mtd/sst25.c
View File

@ -714,7 +714,7 @@ static void sst25_wordwrite(struct sst25_dev_s *priv, FAR const uint8_t *buffer,
* we are finished.
*/
if (nwords <= 0)
if (nwords < 1)
{
return;
}

6
drivers/net/dm90x0.c
View File

@ -891,8 +891,6 @@ static void dm9x_receive(struct dm9x_driver_s *dm9x)
{
union rx_desc_u rx;
bool bchecksumready;
uint8_t mdrah;
uint8_t mdral;
uint8_t rxbyte;
nvdbg("Packet received\n");
@ -901,8 +899,8 @@ static void dm9x_receive(struct dm9x_driver_s *dm9x)
{
/* Store the value of memory data read address register */
mdrah = getreg(DM9X_MDRAH);
mdral = getreg(DM9X_MDRAL);
(void)getreg(DM9X_MDRAH);
(void)getreg(DM9X_MDRAL);
getreg(DM9X_MRCMDX); /* Dummy read */
rxbyte = (uint8_t)DM9X_DATA; /* Get the most up-to-date data */

50
drivers/net/e1000.c
View File

@ -270,7 +270,7 @@ void e1000_turn_off(struct e1000_dev *dev)
void e1000_init(struct e1000_dev *dev)
{
uint32_t rxd_phy;
uint32_t rxd_phys;
uint32_t txd_phys;
uint32_t kmem_phys;
uint32_t rx_control;
@ -570,35 +570,33 @@ static void e1000_receive(struct e1000_dev *e1000)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
#else
{
if (BUF->type == HTONS(ETHTYPE_IP))
if (BUF->type == HTONS(ETHTYPE_IP))
#endif
{
arp_ipin(&e1000->netdev);
devif_input(&e1000->netdev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (e1000->netdev.d_len > 0)
{
arp_ipin(&e1000->netdev);
devif_input(&e1000->netdev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (e1000->netdev.d_len > 0)
{
arp_out(&e1000->netdev);
e1000_transmit(e1000);
}
arp_out(&e1000->netdev);
e1000_transmit(e1000);
}
else if (BUF->type == htons(ETHTYPE_ARP))
}
else if (BUF->type == htons(ETHTYPE_ARP))
{
arp_arpin(&e1000->netdev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (e1000->netdev.d_len > 0)
{
arp_arpin(&e1000->netdev);
/* If the above function invocation resulted in data that should be
* sent out on the network, the field d_len will set to a value > 0.
*/
if (e1000->netdev.d_len > 0)
{
e1000_transmit(e1000);
}
e1000_transmit(e1000);
}
}

1
drivers/power/max1704x.c
View File

@ -271,7 +271,6 @@ static int max1704x_getreg16(FAR struct max1704x_dev_s *priv, uint8_t regaddr,
/* Return the 16-bit value */
return (uint16_t)buffer[0] << 8 | (uint16_t)buffer[1];
return OK;
}
/****************************************************************************

2
drivers/power/pm_activity.c
View File

@ -156,7 +156,7 @@ void pm_activity(int priority)
* controlled priority.
*/
(void)pm_update(accum);
(void)pm_update(tmp);
}
irqrestore(flags);

4
drivers/usbdev/usbmsc_scsi.c
View File

@ -365,7 +365,7 @@ static void usbmsc_putle32(uint8_t *buf, uint32_t val)
static void usbmsc_scsi_wait(FAR struct usbmsc_dev_s *priv)
{
irqstate_t flags = irqsave();
irqstate_t flags;
int ret;
/* We must hold the SCSI lock to call this function */
@ -2802,7 +2802,7 @@ int usbmsc_scsi_main(int argc, char *argv[])
void usbmsc_scsi_signal(FAR struct usbmsc_dev_s *priv)
{
irqstate_t flags = irqsave();
irqstate_t flags;
/* A flag is used to prevent driving up the semaphore count. This function
* is called (primarily) from interrupt level logic so we must disable