STM32: Add support for the IAR compiler
This commit is contained in:
Aleksandr Vyhovanec
Gregory Nutt
parent
2234d7d8e5
commit
29ab0fb991
@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_vectors.S
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* arch/arm/src/stm32/gnu/stm32_vectors.S
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*
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* Copyright (C) 2009-2013, 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2013, 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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691
arch/arm/src/stm32/iar/stm32_vectors.S
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691
arch/arm/src/stm32/iar/stm32_vectors.S
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/************************************************************************************
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* arch/arm/src/stm32/iar/stm32_vectors.S
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*
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* Copyright (C) 2009-2013, 2015-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include "chip.h"
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#include "exc_return.h"
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/************************************************************************************
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* Configuration
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************************************************************************************/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#ifdef CONFIG_ARCH_HIPRI_INTERRUPT
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/* In kernel mode without an interrupt stack, this interrupt handler will set the
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* MSP to the stack pointer of the interrupted thread. If the interrupted thread
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* was a privileged thread, that will be the MSP otherwise it will be the PSP. If
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* the PSP is used, then the value of the MSP will be invalid when the interrupt
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* handler returns because it will be a pointer to an old position in the
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* unprivileged stack. Then when the high priority interrupt occurs and uses this
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* stale MSP, there will most likely be a system failure.
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*
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* If the interrupt stack is selected, on the other hand, then the interrupt
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* handler will always set the the MSP to the interrupt stack. So when the high
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* priority interrupt occurs, it will either use the MSP of the last privileged
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* thread to run or, in the case of the nested interrupt, the interrupt stack if
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* no privileged task has run.
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*/
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# if defined(CONFIG_BUILD_PROTECTED) && CONFIG_ARCH_INTERRUPTSTACK < 4
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# error Interrupt stack must be used with high priority interrupts in kernel mode
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# endif
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/* Use the the BASEPRI to control interrupts is required if nested, high
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* priority interrupts are supported.
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*/
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# ifndef CONFIG_ARMV7M_USEBASEPRI
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# error CONFIG_ARMV7M_USEBASEPRI must be used with CONFIG_ARCH_HIPRI_INTERRUPT
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# endif
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#endif
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/* Memory Map ***********************************************************************/
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/*
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* 0x0800:0000 - Beginning of FLASH. Address of vectors (if not using bootloader)
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* Mapped to address 0x0000:0000 at boot time.
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* 0x0800:3000 - Address of vectors if using bootloader
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* 0x0803:ffff - End of flash
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* 0x2000:0000 - Start of SRAM and start of .data (_sdata)
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* - End of .data (_edata) abd start of .bss (_sbss)
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* - End of .bss (_ebss) and bottom of idle stack
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* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, start of heap
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* 0x2000:ffff - End of SRAM and end of heap
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*/
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MODULE stm32_vectors
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/* Forward declaration of sections. */
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SECTION CSTACK:DATA:NOROOT(3)
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IDLE_STACK EQU(sfb(CSTACK)+CONFIG_IDLETHREAD_STACKSIZE-4)
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HEAP_BASE EQU(sfb(CSTACK)+CONFIG_IDLETHREAD_STACKSIZE)
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/************************************************************************************
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* Public Symbols
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************************************************************************************/
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/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */
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#ifndef CONFIG_ARMV7M_CMNVECTOR
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PUBLIC __vector_table
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EXTERN __start
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EXTERN up_doirq
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/************************************************************************************
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* Macros
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************************************************************************************/
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/* On entry into an IRQ, the hardware automatically saves the xPSR, PC, LR, R12, R0-R3
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* registers on the stack, then branches to an instantantiation of the following
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* macro. This macro simply loads the IRQ number into R0, then jumps to the common
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* IRQ handling logic.
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*/
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HANDLER MACRO label, irqno
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THUMB
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label:
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mov r0, #irqno
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b exception_common
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ENDM
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/************************************************************************************
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* Vectors
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************************************************************************************/
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SECTION .intvec:CODE:ROOT(2)
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/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
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__vector_table:
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/* Processor Exceptions */
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DCD IDLE_STACK /* Vector 0: Reset stack pointer */
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DCD __start /* Vector 1: Reset vector */
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DCD stm32_nmi /* Vector 2: Non-Maskable Interrupt (NMI) */
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DCD stm32_hardfault /* Vector 3: Hard fault */
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DCD stm32_mpu /* Vector 4: Memory management (MPU) */
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DCD stm32_busfault /* Vector 5: Bus fault */
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DCD stm32_usagefault /* Vector 6: Usage fault */
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DCD stm32_reserved /* Vector 7: Reserved */
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DCD stm32_reserved /* Vector 8: Reserved */
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DCD stm32_reserved /* Vector 9: Reserved */
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DCD stm32_reserved /* Vector 10: Reserved */
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DCD stm32_svcall /* Vector 11: SVC call */
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DCD stm32_dbgmonitor /* Vector 12: Debug monitor */
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DCD stm32_reserved /* Vector 13: Reserved */
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DCD stm32_pendsv /* Vector 14: Pendable system service request */
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DCD stm32_systick /* Vector 15: System tick */
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/* External Interrupts */
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#if !defined(CONFIG_STM32_NOEXT_VECTORS)
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#undef VECTOR
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#define VECTOR(l,i) .word l
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/* IAR Assembler:
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* You must not mix assembler language and C-style preprocessor directives.
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* Conceptually, they are different languages and mixing them might lead to unexpected
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* behavior because an assembler directive is not necessarily accepted as a part of the C
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* preprocessor language.
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*/
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#if defined(CONFIG_STM32_STM32L15XX)
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# include "chip/stm32l15xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F10XX)
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# include "chip/stm32f10xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F20XX)
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DCD stm32_wwdg /* Vector 16+0: Window Watchdog interrupt */
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DCD stm32_pvd /* Vector 16+1: PVD through EXTI Line detection interrupt */
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DCD stm32_tamper /* Vector 16+2: Tamper and time stamp interrupts */
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DCD stm32_rtc_wkup /* Vector 16+3: RTC global interrupt */
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DCD stm32_flash /* Vector 16+4: Flash global interrupt */
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DCD stm32_rcc /* Vector 16+5: RCC global interrupt */
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DCD stm32_exti0 /* Vector 16+6: EXTI Line 0 interrupt */
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DCD stm32_exti1 /* Vector 16+7: EXTI Line 1 interrupt */
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DCD stm32_exti2 /* Vector 16+8: EXTI Line 2 interrupt */
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DCD stm32_exti3 /* Vector 16+9: EXTI Line 3 interrupt */
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DCD stm32_exti4 /* Vector 16+10: EXTI Line 4 interrupt */
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DCD stm32_dma1s0 /* Vector 16+11: DMA1 Stream 0 global interrupt */
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DCD stm32_dma1s1 /* Vector 16+12: DMA1 Stream 1 global interrupt */
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DCD stm32_dma1s2 /* Vector 16+13: DMA1 Stream 2 global interrupt */
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DCD stm32_dma1s3 /* Vector 16+14: DMA1 Stream 3 global interrupt */
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DCD stm32_dma1s4 /* Vector 16+15: DMA1 Stream 4 global interrupt */
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DCD stm32_dma1s5 /* Vector 16+16: DMA1 Stream 5 global interrupt */
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DCD stm32_dma1s6 /* Vector 16+17: DMA1 Stream 6 global interrupt */
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DCD stm32_adc /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
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DCD stm32_can1tx /* Vector 16+19: CAN1 TX interrupts */
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DCD stm32_can1rx0 /* Vector 16+20: CAN1 RX0 interrupts */
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DCD stm32_can1rx1 /* Vector 16+21: CAN1 RX1 interrupt */
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DCD stm32_can1sce /* Vector 16+22: CAN1 SCE interrupt */
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DCD stm32_exti95 /* Vector 16+23: EXTI Line[9:5] interrupts */
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DCD stm32_tim1brk /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
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DCD stm32_tim1up /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
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DCD stm32_tim1trgcom /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
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DCD stm32_tim1cc /* Vector 16+27: TIM1 Capture Compare interrupt */
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DCD stm32_tim2 /* Vector 16+28: TIM2 global interrupt */
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DCD stm32_tim3 /* Vector 16+29: TIM3 global interrupt */
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DCD stm32_tim4 /* Vector 16+30: TIM4 global interrupt */
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DCD stm32_i2c1ev /* Vector 16+31: I2C1 event interrupt */
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DCD stm32_i2c1er /* Vector 16+32: I2C1 error interrupt */
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DCD stm32_i2c2ev /* Vector 16+33: I2C2 event interrupt */
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DCD stm32_i2c2er /* Vector 16+34: I2C2 error interrupt */
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DCD stm32_spi1 /* Vector 16+35: SPI1 global interrupt */
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DCD stm32_spi2 /* Vector 16+36: SPI2 global interrupt */
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DCD stm32_usart1 /* Vector 16+37: USART1 global interrupt */
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DCD stm32_usart2 /* Vector 16+38: USART2 global interrupt */
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DCD stm32_usart3 /* Vector 16+39: USART3 global interrupt */
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DCD stm32_exti1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
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DCD stm32_rtcalrm /* Vector 16+41: RTC alarm through EXTI line interrupt */
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DCD stm32_otgfswkup /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
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DCD stm32_tim8brk /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
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DCD stm32_tim8up /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */
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DCD stm32_tim8trgcom /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
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DCD stm32_tim8cc /* Vector 16+46: TIM8 Capture Compare interrupt */
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DCD stm32_dma1s7 /* Vector 16+47: DMA1 Stream 7 global interrupt */
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DCD stm32_fsmc /* Vector 16+48: FSMC global interrupt */
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DCD stm32_sdio /* Vector 16+49: SDIO global interrupt */
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DCD stm32_tim5 /* Vector 16+50: TIM5 global interrupt */
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DCD stm32_spi3 /* Vector 16+51: SPI3 global interrupt */
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DCD stm32_uart4 /* Vector 16+52: UART4 global interrupt */
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DCD stm32_uart5 /* Vector 16+53: UART5 global interrupt */
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DCD stm32_tim6 /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
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DCD stm32_tim7 /* Vector 16+55: TIM7 global interrupt */
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DCD stm32_dma2s0 /* Vector 16+56: DMA2 Stream 0 global interrupt */
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DCD stm32_dma2s1 /* Vector 16+57: DMA2 Stream 1 global interrupt */
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DCD stm32_dma2s2 /* Vector 16+58: DMA2 Stream 2 global interrupt */
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DCD stm32_dma2s3 /* Vector 16+59: DMA2 Stream 3 global interrupt */
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DCD stm32_dma2s4 /* Vector 16+60: DMA2 Stream 4 global interrupt */
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DCD stm32_eth /* Vector 16+61: Ethernet global interrupt */
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DCD stm32_ethwkup /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
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DCD stm32_can2tx /* Vector 16+63: CAN2 TX interrupts */
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DCD stm32_can2rx0 /* Vector 16+64: CAN2 RX0 interrupts */
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DCD stm32_can2rx1 /* Vector 16+65: CAN2 RX1 interrupt */
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DCD stm32_can2sce /* Vector 16+66: CAN2 SCE interrupt */
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DCD stm32_otgfs /* Vector 16+67: USB On The Go FS global interrupt */
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DCD stm32_dma2s5 /* Vector 16+68: DMA2 Stream 5 global interrupt */
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DCD stm32_dma2s6 /* Vector 16+69: DMA2 Stream 6 global interrupt */
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DCD stm32_dma2s7 /* Vector 16+70: DMA2 Stream 7 global interrupt */
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DCD stm32_usart6 /* Vector 16+71: USART6 global interrupt */
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DCD stm32_i2c3ev /* Vector 16+72: I2C3 event interrupt */
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DCD stm32_i2c3er /* Vector 16+73: I2C3 error interrupt */
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DCD stm32_otghsep1out /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
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DCD stm32_otghsep1in /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
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DCD stm32_otghswkup /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
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DCD stm32_otghs /* Vector 16+77: USB On The Go HS global interrupt */
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DCD stm32_dcmi /* Vector 16+78: DCMI global interrupt */
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DCD stm32_cryp /* Vector 16+79: CRYP crypto global interrupt */
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DCD stm32_hash /* Vector 16+80: Hash and Rng global interrupt */
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#elif defined(CONFIG_STM32_STM32F30XX)
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# include "chip/stm32f30xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F37XX)
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# include "chip/stm32f37xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
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# include "chip/stm32f42xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F446)
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# include "chip/stm32f44xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F40XX)
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# include "chip/stm32f40xxx_vectors.h"
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#else
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# error "No vectors for STM32 chip"
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#endif
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#endif /* CONFIG_STM32_NOEXT_VECTORS */
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/************************************************************************************
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* .text
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************************************************************************************/
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SECTION .text:CODE:NOROOT(2)
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handlers:
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HANDLER stm32_reserved, STM32_IRQ_RESERVED /* Unexpected/reserved vector */
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HANDLER stm32_nmi, STM32_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
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HANDLER stm32_hardfault, STM32_IRQ_HARDFAULT /* Vector 3: Hard fault */
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HANDLER stm32_mpu, STM32_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
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HANDLER stm32_busfault, STM32_IRQ_BUSFAULT /* Vector 5: Bus fault */
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HANDLER stm32_usagefault, STM32_IRQ_USAGEFAULT /* Vector 6: Usage fault */
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HANDLER stm32_svcall, STM32_IRQ_SVCALL /* Vector 11: SVC call */
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HANDLER stm32_dbgmonitor, STM32_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
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HANDLER stm32_pendsv, STM32_IRQ_PENDSV /* Vector 14: Penable system service request */
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HANDLER stm32_systick, STM32_IRQ_SYSTICK /* Vector 15: System tick */
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#if !defined(CONFIG_STM32_NOEXT_VECTORS)
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/* IAR Assembler:
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* You must not mix assembler language and C-style preprocessor directives.
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* Conceptually, they are different languages and mixing them might lead to unexpected
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* behavior because an assembler directive is not necessarily accepted as a part of the C
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* preprocessor language.
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*/
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#if defined(CONFIG_STM32_STM32L15XX)
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# include "chip/stm32l15xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F10XX)
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# include "chip/stm32f10xxx_vectors.h"
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#elif defined(CONFIG_STM32_STM32F20XX)
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HANDLER stm32_wwdg, STM32_IRQ_WWDG /* Vector 16+0: Window Watchdog interrupt */
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HANDLER stm32_pvd, STM32_IRQ_PVD /* Vector 16+1: PVD through EXTI Line detection interrupt */
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HANDLER stm32_tamper, STM32_IRQ_TAMPER /* Vector 16+2: Tamper and time stamp interrupts */
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HANDLER stm32_rtc_wkup, STM32_IRQ_RTC_WKUP /* Vector 16+3: RTC global interrupt */
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HANDLER stm32_flash, STM32_IRQ_FLASH /* Vector 16+4: Flash global interrupt */
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HANDLER stm32_rcc, STM32_IRQ_RCC /* Vector 16+5: RCC global interrupt */
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HANDLER stm32_exti0, STM32_IRQ_EXTI0 /* Vector 16+6: EXTI Line 0 interrupt */
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HANDLER stm32_exti1, STM32_IRQ_EXTI1 /* Vector 16+7: EXTI Line 1 interrupt */
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HANDLER stm32_exti2, STM32_IRQ_EXTI2 /* Vector 16+8: EXTI Line 2 interrupt */
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HANDLER stm32_exti3, STM32_IRQ_EXTI3 /* Vector 16+9: EXTI Line 3 interrupt */
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HANDLER stm32_exti4, STM32_IRQ_EXTI4 /* Vector 16+10: EXTI Line 4 interrupt */
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HANDLER stm32_dma1s0, STM32_IRQ_DMA1S0 /* Vector 16+11: DMA1 Stream 0 global interrupt */
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HANDLER stm32_dma1s1, STM32_IRQ_DMA1S1 /* Vector 16+12: DMA1 Stream 1 global interrupt */
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HANDLER stm32_dma1s2, STM32_IRQ_DMA1S2 /* Vector 16+13: DMA1 Stream 2 global interrupt */
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HANDLER stm32_dma1s3, STM32_IRQ_DMA1S3 /* Vector 16+14: DMA1 Stream 3 global interrupt */
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HANDLER stm32_dma1s4, STM32_IRQ_DMA1S4 /* Vector 16+15: DMA1 Stream 4 global interrupt */
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HANDLER stm32_dma1s5, STM32_IRQ_DMA1S5 /* Vector 16+16: DMA1 Stream 5 global interrupt */
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HANDLER stm32_dma1s6, STM32_IRQ_DMA1S6 /* Vector 16+17: DMA1 Stream 6 global interrupt */
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HANDLER stm32_adc, STM32_IRQ_ADC /* Vector 16+18: ADC1, ADC2, and ADC3 global interrupt */
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HANDLER stm32_can1tx, STM32_IRQ_CAN1TX /* Vector 16+19: CAN1 TX interrupts */
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HANDLER stm32_can1rx0, STM32_IRQ_CAN1RX0 /* Vector 16+20: CAN1 RX0 interrupts */
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HANDLER stm32_can1rx1, STM32_IRQ_CAN1RX1 /* Vector 16+21: CAN1 RX1 interrupt */
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HANDLER stm32_can1sce, STM32_IRQ_CAN1SCE /* Vector 16+22: CAN1 SCE interrupt */
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HANDLER stm32_exti95, STM32_IRQ_EXTI95 /* Vector 16+23: EXTI Line[9:5] interrupts */
|
||||
HANDLER stm32_tim1brk, STM32_IRQ_TIM1BRK /* Vector 16+24: TIM1 Break interrupt/TIM9 global interrupt */
|
||||
HANDLER stm32_tim1up, STM32_IRQ_TIM1UP /* Vector 16+25: TIM1 Update interrupt/TIM10 global interrupt */
|
||||
HANDLER stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM /* Vector 16+26: TIM1 Trigger and Commutation interrupts/TIM11 global interrupt */
|
||||
HANDLER stm32_tim1cc, STM32_IRQ_TIM1CC /* Vector 16+27: TIM1 Capture Compare interrupt */
|
||||
HANDLER stm32_tim2, STM32_IRQ_TIM2 /* Vector 16+28: TIM2 global interrupt */
|
||||
HANDLER stm32_tim3, STM32_IRQ_TIM3 /* Vector 16+29: TIM3 global interrupt */
|
||||
HANDLER stm32_tim4, STM32_IRQ_TIM4 /* Vector 16+30: TIM4 global interrupt */
|
||||
HANDLER stm32_i2c1ev, STM32_IRQ_I2C1EV /* Vector 16+31: I2C1 event interrupt */
|
||||
HANDLER stm32_i2c1er, STM32_IRQ_I2C1ER /* Vector 16+32: I2C1 error interrupt */
|
||||
HANDLER stm32_i2c2ev, STM32_IRQ_I2C2EV /* Vector 16+33: I2C2 event interrupt */
|
||||
HANDLER stm32_i2c2er, STM32_IRQ_I2C2ER /* Vector 16+34: I2C2 error interrupt */
|
||||
HANDLER stm32_spi1, STM32_IRQ_SPI1 /* Vector 16+35: SPI1 global interrupt */
|
||||
HANDLER stm32_spi2, STM32_IRQ_SPI2 /* Vector 16+36: SPI2 global interrupt */
|
||||
HANDLER stm32_usart1, STM32_IRQ_USART1 /* Vector 16+37: USART1 global interrupt */
|
||||
HANDLER stm32_usart2, STM32_IRQ_USART2 /* Vector 16+38: USART2 global interrupt */
|
||||
HANDLER stm32_usart3, STM32_IRQ_USART3 /* Vector 16+39: USART3 global interrupt */
|
||||
HANDLER stm32_exti1510, STM32_IRQ_EXTI1510 /* Vector 16+40: EXTI Line[15:10] interrupts */
|
||||
HANDLER stm32_rtcalrm, STM32_IRQ_RTCALRM /* Vector 16+41: RTC alarm through EXTI line interrupt */
|
||||
HANDLER stm32_otgfswkup, STM32_IRQ_OTGFSWKUP /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
|
||||
HANDLER stm32_tim8brk, STM32_IRQ_TIM8BRK /* Vector 16+43: TIM8 Break interrupt/TIM12 global interrupt */
|
||||
HANDLER stm32_tim8up, STM32_IRQ_TIM8UP /* Vector 16+44: TIM8 Update interrup/TIM13 global interrupt */
|
||||
HANDLER stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM /* Vector 16+45: TIM8 Trigger and Commutation interrupts/TIM14 global interrupt */
|
||||
HANDLER stm32_tim8cc, STM32_IRQ_TIM8CC /* Vector 16+46: TIM8 Capture Compare interrupt */
|
||||
HANDLER stm32_dma1s7, STM32_IRQ_DMA1S7 /* Vector 16+47: DMA1 Stream 7 global interrupt */
|
||||
HANDLER stm32_fsmc, STM32_IRQ_FSMC /* Vector 16+48: FSMC global interrupt */
|
||||
HANDLER stm32_sdio, STM32_IRQ_SDIO /* Vector 16+49: SDIO global interrupt */
|
||||
HANDLER stm32_tim5, STM32_IRQ_TIM5 /* Vector 16+50: TIM5 global interrupt */
|
||||
HANDLER stm32_spi3, STM32_IRQ_SPI3 /* Vector 16+51: SPI3 global interrupt */
|
||||
HANDLER stm32_uart4, STM32_IRQ_UART4 /* Vector 16+52: UART4 global interrupt */
|
||||
HANDLER stm32_uart5, STM32_IRQ_UART5 /* Vector 16+53: UART5 global interrupt */
|
||||
HANDLER stm32_tim6, STM32_IRQ_TIM6 /* Vector 16+54: TIM6 global interrupt/DAC1 and DAC2 underrun error interrupts */
|
||||
HANDLER stm32_tim7, STM32_IRQ_TIM7 /* Vector 16+55: TIM7 global interrupt */
|
||||
HANDLER stm32_dma2s0, STM32_IRQ_DMA2S0 /* Vector 16+56: DMA2 Stream 0 global interrupt */
|
||||
HANDLER stm32_dma2s1, STM32_IRQ_DMA2S1 /* Vector 16+57: DMA2 Stream 1 global interrupt */
|
||||
HANDLER stm32_dma2s2, STM32_IRQ_DMA2S2 /* Vector 16+58: DMA2 Stream 2 global interrupt */
|
||||
HANDLER stm32_dma2s3, STM32_IRQ_DMA2S3 /* Vector 16+59: DMA2 Stream 3 global interrupt */
|
||||
HANDLER stm32_dma2s4, STM32_IRQ_DMA2S4 /* Vector 16+60: DMA2 Stream 4 global interrupt */
|
||||
HANDLER stm32_eth, STM32_IRQ_ETH /* Vector 16+61: Ethernet global interrupt */
|
||||
HANDLER stm32_ethwkup, STM32_IRQ_ETHWKUP /* Vector 16+62: Ethernet Wakeup through EXTI line interrupt */
|
||||
HANDLER stm32_can2tx, STM32_IRQ_CAN2TX /* Vector 16+63: CAN2 TX interrupts */
|
||||
HANDLER stm32_can2rx0, STM32_IRQ_CAN2RX0 /* Vector 16+64: CAN2 RX0 interrupts */
|
||||
HANDLER stm32_can2rx1, STM32_IRQ_CAN2RX1 /* Vector 16+65: CAN2 RX1 interrupt */
|
||||
HANDLER stm32_can2sce, STM32_IRQ_CAN2SCE /* Vector 16+66: CAN2 SCE interrupt */
|
||||
HANDLER stm32_otgfs, STM32_IRQ_OTGFS /* Vector 16+67: USB On The Go FS global interrupt */
|
||||
HANDLER stm32_dma2s5, STM32_IRQ_DMA2S5 /* Vector 16+68: DMA2 Stream 5 global interrupt */
|
||||
HANDLER stm32_dma2s6, STM32_IRQ_DMA2S6 /* Vector 16+69: DMA2 Stream 6 global interrupt */
|
||||
HANDLER stm32_dma2s7, STM32_IRQ_DMA2S7 /* Vector 16+70: DMA2 Stream 7 global interrupt */
|
||||
HANDLER stm32_usart6, STM32_IRQ_USART6 /* Vector 16+71: USART6 global interrupt */
|
||||
HANDLER stm32_i2c3ev, STM32_IRQ_I2C3EV /* Vector 16+72: I2C3 event interrupt */
|
||||
HANDLER stm32_i2c3er, STM32_IRQ_I2C3ER /* Vector 16+73: I2C3 error interrupt */
|
||||
HANDLER stm32_otghsep1out, STM32_IRQ_OTGHSEP1OUT /* Vector 16+74: USB On The Go HS End Point 1 Out global interrupt */
|
||||
HANDLER stm32_otghsep1in, STM32_IRQ_OTGHSEP1IN /* Vector 16+75: USB On The Go HS End Point 1 In global interrupt */
|
||||
HANDLER stm32_otghswkup, STM32_IRQ_OTGHSWKUP /* Vector 16+76: USB On The Go HS Wakeup through EXTI interrupt */
|
||||
HANDLER stm32_otghs, STM32_IRQ_OTGHS /* Vector 16+77: USB On The Go HS global interrupt */
|
||||
HANDLER stm32_dcmi, STM32_IRQ_DCMI /* Vector 16+78: DCMI global interrupt */
|
||||
HANDLER stm32_cryp, STM32_IRQ_CRYP /* Vector 16+79: CRYP crypto global interrupt */
|
||||
HANDLER stm32_hash, STM32_IRQ_HASH /* Vector 16+80: Hash and Rng global interrupt */
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
|
||||
# include "chip/stm32f42xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F446)
|
||||
# include "chip/stm32f44xxx_vectors.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
# include "chip/stm32f40xxx_vectors.h"
|
||||
#else
|
||||
# error "No handlers for STM32 chip"
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_NOEXT_VECTORS */
|
||||
|
||||
/* Common IRQ handling logic. On entry here, the return stack is on either
|
||||
* the PSP or the MSP and looks like the following:
|
||||
*
|
||||
* REG_XPSR
|
||||
* REG_R15
|
||||
* REG_R14
|
||||
* REG_R12
|
||||
* REG_R3
|
||||
* REG_R2
|
||||
* REG_R1
|
||||
* MSP->REG_R0
|
||||
*
|
||||
* And
|
||||
* R0 contains the IRQ number
|
||||
* R14 Contains the EXC_RETURN value
|
||||
* We are in handler mode and the current SP is the MSP
|
||||
*/
|
||||
|
||||
PUBLIC exception_common
|
||||
|
||||
exception_common:
|
||||
|
||||
/* Complete the context save */
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
|
||||
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
|
||||
* EXC_RETURN is 0xfffffffd (unprivileged thread)
|
||||
*/
|
||||
|
||||
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
|
||||
beq l1 /* Branch if context already on the MSP */
|
||||
mrs r1, psp /* R1=The process stack pointer (PSP) */
|
||||
mov sp, r1 /* Set the MSP to the PSP */
|
||||
|
||||
l1:
|
||||
#endif
|
||||
|
||||
/* r1 holds the value of the stack pointer AFTER the exception handling logic
|
||||
* pushed the various registers onto the stack. Get r2 = the value of the
|
||||
* stack pointer BEFORE the interrupt modified it.
|
||||
*/
|
||||
|
||||
mov r2, sp /* R2=Copy of the main/process stack pointer */
|
||||
add r2, r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
mrs r3, basepri /* R3=Current BASEPRI setting */
|
||||
#else
|
||||
mrs r3, primask /* R3=Current PRIMASK setting */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Skip over the block of memory reserved for floating pointer register save.
|
||||
* Lazy FPU register saving is used. FPU registers will be saved in this
|
||||
* block only if a context switch occurs (this means, of course, that the FPU
|
||||
* cannot be used in interrupt processing).
|
||||
*/
|
||||
|
||||
sub sp, #(4*SW_FPU_REGS)
|
||||
#endif
|
||||
|
||||
/* Save the remaining registers on the stack after the registers pushed
|
||||
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
|
||||
* r14=register values.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
stmdb sp!, {r2-r11,r14} /* Save the remaining registers plus the SP value */
|
||||
#else
|
||||
stmdb sp!, {r2-r11} /* Save the remaining registers plus the SP value */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
/* Disable interrupts, select the stack to use for interrupt handling
|
||||
* and call up_doirq to handle the interrupt
|
||||
*/
|
||||
|
||||
cpsid i /* Disable further interrupts */
|
||||
|
||||
#else
|
||||
/* Set the BASEPRI register so that further normal interrupts will be
|
||||
* masked. Nested, high priority may still occur, however.
|
||||
*/
|
||||
|
||||
mov r2, #NVIC_SYSH_DISABLE_PRIORITY
|
||||
msr basepri, r2 /* Set the BASEPRI */
|
||||
#endif
|
||||
|
||||
/* There are two arguments to up_doirq:
|
||||
*
|
||||
* R0 = The IRQ number
|
||||
* R1 = The top of the stack points to the saved state
|
||||
*/
|
||||
|
||||
mov r1, sp
|
||||
|
||||
/* Also save the top of the stack in a preserved register */
|
||||
|
||||
mov r4, sp
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
/* If CONFIG_ARCH_INTERRUPTSTACK is defined, we will set the MSP to use
|
||||
* a special special interrupt stack pointer. The way that this is done
|
||||
* here prohibits nested interrupts without some additional logic!
|
||||
*/
|
||||
|
||||
ldr sp, =g_intstackbase
|
||||
|
||||
#else
|
||||
/* Otherwise, we will re-use the interrupted thread's stack. That may
|
||||
* mean using either MSP or PSP stack for interrupt level processing (in
|
||||
* kernel mode).
|
||||
*/
|
||||
|
||||
bic r2, r4, #7 /* Get the stack pointer with 8-byte alignment */
|
||||
mov sp, r2 /* Instantiate the aligned stack */
|
||||
|
||||
#endif
|
||||
|
||||
bl up_doirq /* R0=IRQ, R1=register save (msp) */
|
||||
mov r1, r4 /* Recover R1=main stack pointer */
|
||||
|
||||
/* On return from up_doirq, R0 will hold a pointer to register context
|
||||
* array to use for the interrupt return. If that return value is the same
|
||||
* as current stack pointer, then things are relatively easy.
|
||||
*/
|
||||
|
||||
cmp r0, r1 /* Context switch? */
|
||||
beq l2 /* Branch if no context switch */
|
||||
|
||||
/* We are returning with a pending context switch.
|
||||
*
|
||||
* If the FPU is enabled, then we will need to restore FPU registers.
|
||||
* This is not done in normal interrupt save/restore because the cost
|
||||
* is prohibitive. This is only done when switching contexts. A
|
||||
* consequence of this is that floating point operations may not be
|
||||
* performed in interrupt handling logic.
|
||||
*
|
||||
* Here:
|
||||
* r0 = Address of the register save area
|
||||
*
|
||||
* NOTE: It is a requirement that up_restorefpu() preserve the value of
|
||||
* r0!
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
bl up_restorefpu /* Restore the FPU registers */
|
||||
#endif
|
||||
|
||||
/* We are returning with a pending context switch. This case is different
|
||||
* because in this case, the register save structure does not lie in the
|
||||
* stack but, rather, within a TCB structure. We'll have to copy some
|
||||
* values to the stack.
|
||||
*/
|
||||
|
||||
add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
|
||||
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
|
||||
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
|
||||
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
ldmia r0, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
|
||||
#else
|
||||
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
|
||||
#endif
|
||||
b l3 /* Re-join common logic */
|
||||
|
||||
/* We are returning with no context switch. We simply need to "unwind"
|
||||
* the same stack frame that we created
|
||||
*
|
||||
* Here:
|
||||
* r1 = Address of the return stack (same as r0)
|
||||
*/
|
||||
|
||||
l2:
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
ldmia r1!, {r2-r11,r14} /* Recover R4-R11, r14 + 2 temp values */
|
||||
#else
|
||||
ldmia r1!, {r2-r11} /* Recover R4-R11 + 2 temp values */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Skip over the block of memory reserved for floating pointer register
|
||||
* save. Then R1 is the address of the HW save area
|
||||
*/
|
||||
|
||||
add r1, #(4*SW_FPU_REGS)
|
||||
#endif
|
||||
|
||||
/* Set up to return from the exception
|
||||
*
|
||||
* Here:
|
||||
* r1 = Address on the target thread's stack position at the start of
|
||||
* the registers saved by hardware
|
||||
* r3 = primask or basepri
|
||||
* r4-r11 = restored register values
|
||||
*/
|
||||
|
||||
l3:
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* The EXC_RETURN value will be 0xfffffff9 (privileged thread) or 0xfffffff1
|
||||
* (handler mode) if the stack is on the MSP. It can only be on the PSP if
|
||||
* EXC_RETURN is 0xfffffffd (unprivileged thread)
|
||||
*/
|
||||
|
||||
mrs r2, control /* R2=Contents of the control register */
|
||||
tst r14, #EXC_RETURN_PROCESS_STACK /* nonzero if context on process stack */
|
||||
beq l4 /* Branch if privileged */
|
||||
|
||||
orr r2, r2, #1 /* Unprivileged mode */
|
||||
msr psp, r1 /* R1=The process stack pointer */
|
||||
b l5
|
||||
l4:
|
||||
bic r2, r2, #1 /* Privileged mode */
|
||||
msr msp, r1 /* R1=The main stack pointer */
|
||||
l5:
|
||||
msr control, r2 /* Save the updated control register */
|
||||
#else
|
||||
msr msp, r1 /* Recover the return MSP value */
|
||||
|
||||
/* Preload r14 with the special return value first (so that the return
|
||||
* actually occurs with interrupts still disabled).
|
||||
*/
|
||||
|
||||
ldr r14, =EXC_RETURN_PRIVTHR /* Load the special value */
|
||||
#endif
|
||||
|
||||
/* Restore the interrupt state */
|
||||
|
||||
#ifdef CONFIG_ARMV7M_USEBASEPRI
|
||||
msr basepri, r3 /* Restore interrupts priority masking */
|
||||
#ifndef CONFIG_ARCH_HIPRI_INTERRUPT
|
||||
cpsie i /* Re-enable interrupts */
|
||||
#endif
|
||||
|
||||
#else
|
||||
msr primask, r3 /* Restore interrupts */
|
||||
#endif
|
||||
|
||||
/* Always return with R14 containing the special value that will: (1)
|
||||
* return to thread mode, and (2) continue to use the MSP
|
||||
*/
|
||||
|
||||
bx r14 /* And return */
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc/g_intstackbase
|
||||
*
|
||||
* Description:
|
||||
* Shouldn't happen
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 7
|
||||
.bss
|
||||
.global g_intstackalloc
|
||||
.global g_intstackbase
|
||||
.align 8
|
||||
g_intstackalloc:
|
||||
.skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
|
||||
g_intstackbase:
|
||||
.size g_intstackalloc, .-g_intstackalloc
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_ARMV7M_CMNVECTOR */
|
||||
|
||||
/************************************************************************************
|
||||
* .rodata
|
||||
************************************************************************************/
|
||||
|
||||
SECTION .rodata:CONST:NOROOT(2)
|
||||
|
||||
/* Variables: _sbss is the start of the BSS region (see ld.script) _ebss is the end
|
||||
* of the BSS regsion (see ld.script). The idle task stack starts at the end of BSS
|
||||
* and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is the thread that
|
||||
* the system boots on and, eventually, becomes the idle, do nothing task that runs
|
||||
* only when there is nothing else to run. The heap continues from there until the
|
||||
* end of memory. See g_idle_topstack below.
|
||||
*/
|
||||
|
||||
PUBLIC g_idle_topstack
|
||||
|
||||
g_idle_topstack:
|
||||
DCD HEAP_BASE
|
||||
|
||||
END
|
||||
@ -83,11 +83,17 @@
|
||||
|
||||
volatile uint32_t *g_current_regs[1];
|
||||
|
||||
/* This is the address of the exception vector table (determined by the
|
||||
* linker script).
|
||||
*/
|
||||
/* This is the address of the exception vector table (determined by the
|
||||
* linker script).
|
||||
*/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
/* _vectors replaced on __vector_table for IAR C-SPY Simulator */
|
||||
|
||||
extern uint32_t __vector_table[];
|
||||
#else
|
||||
extern uint32_t _vectors[];
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
@ -329,7 +335,11 @@ void up_irqinitialize(void)
|
||||
* will need to set the NVIC vector location to this alternative location.
|
||||
*/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
putreg32((uint32_t)__vector_table, NVIC_VECTAB);
|
||||
#else
|
||||
putreg32((uint32_t)_vectors, NVIC_VECTAB);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMVECTORS
|
||||
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_start.c
|
||||
* arch/arm/src/chip/stm32_start.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011-2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -58,6 +57,24 @@
|
||||
# include "nvic.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
# define _START_BSS __sfb(".bss")
|
||||
# define _END_BSS __sfe(".bss")
|
||||
# define _DATA_INIT __sfb(".data_init")
|
||||
# define _START_DATA __sfb(".data")
|
||||
# define _END_DATA __sfe(".data")
|
||||
#else
|
||||
# define _START_BSS &_sbss
|
||||
# define _END_BSS &_ebss
|
||||
# define _DATA_INIT &_eronly
|
||||
# define _START_DATA &_sdata
|
||||
# define _END_DATA &_edata
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function prototypes
|
||||
****************************************************************************/
|
||||
@ -263,7 +280,7 @@ void __start(void)
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = &_sbss; dest < &_ebss; )
|
||||
for (dest = _START_BSS; dest < __END_BSS; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
@ -276,7 +293,7 @@ void __start(void)
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
|
||||
for (src = _DATA_INIT, dest = _START_DATA; dest < _END_DATA; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user