Fix some of the SSD1289 initial register settings
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4788 42af7a65-404d-4744-a932-0658087f49c3
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@ -2849,4 +2849,5 @@
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* arch/arm/src/stm32_i2c.c: Fix STM32 F2 I2C. It is apparently bug-for-bug
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compatible with the F4 and needs the same work-around for the missing BTF
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signal that was needed for the F4.
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* drivers/lcd/ssd1289.*: Fix some of the initial register settings.
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@ -224,7 +224,7 @@ static int ssd1289_setcontrast(FAR struct lcd_dev_s *dev, unsigned int contrast)
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/* Initialization */
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static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv);
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static inline int ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv);
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/**************************************************************************************
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* Private Data
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@ -823,7 +823,7 @@ static int ssd1289_setcontrast(FAR struct lcd_dev_s *dev, unsigned int contrast)
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*
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**************************************************************************************/
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static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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static inline int ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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{
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FAR struct ssd1289_lcd_s *lcd = priv->lcd;
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#ifndef CONFIG_LCD_NOGETRUN
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@ -997,7 +997,7 @@ static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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*/
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ssd1289_putreg(lcd, SSD1289_ENTRY,
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(SSD1289_ENTRY_ID_HINCVINC | SSD1289_ENTRY_TY_B |
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(SSD1289_ENTRY_ID_HINCVINC | SSD1289_ENTRY_TY_C |
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SSD1289_ENTRY_DMODE_RAM | SSD1289_ENTRY_DFM_65K));
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#else
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/* LG=0, AM=1, ID=3, TY=2, DMODE=0, WMODE=0, OEDEF=0, TRANS=0, DRM=3 */
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@ -1005,7 +1005,7 @@ static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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ssd1289_putreg(lcd, SSD1289_ENTRY,
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(SSD1289_ENTRY_AM | SSD1289_ENTRY_ID_HINCVINC |
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SSD1289_ENTRY_TY_B | SSD1289_ENTRY_DMODE_RAM |
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SSD1289_ENTRY_TY_C | SSD1289_ENTRY_DMODE_RAM |
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SSD1289_ENTRY_DFM_65K));
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#endif
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@ -1101,11 +1101,13 @@ static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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#if 0
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up_mdelay(50);
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#endif
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return OK;
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}
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#ifndef CONFIG_LCD_NOGETRUN
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else
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{
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lcddbg("Unsupported LCD type\n");
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return -ENODEV;
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}
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#endif
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@ -1130,6 +1132,8 @@ static inline void ssd1289_hwinitialize(FAR struct ssd1289_dev_s *priv)
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FAR struct lcd_dev_s *ssd1289_lcdinitialize(FAR struct ssd1289_lcd_s *lcd)
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{
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int ret;
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lcdvdbg("Initializing\n");
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/* If we ccould support multiple SSD1289 devices, this is where we would allocate
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@ -1151,16 +1155,20 @@ FAR struct lcd_dev_s *ssd1289_lcdinitialize(FAR struct ssd1289_lcd_s *lcd)
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/* Configure and enable LCD */
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ssd1289_hwinitialize(priv);
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ret = ssd1289_hwinitialize(priv);
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if (ret == OK)
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{
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/* Clear the display (setting it to the color 0=black) */
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/* Clear the display (setting it to the color 0=black) */
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ssd1289_clear(&priv->dev, 0);
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ssd1289_clear(&priv->dev, 0);
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/* Turn the display off */
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/* Turn the display off */
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ssd1289_poweroff(lcd);
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return &g_lcddev.dev;
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}
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ssd1289_poweroff(lcd);
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return &g_lcddev.dev;
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return NULL;
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}
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/**************************************************************************************
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@ -120,8 +120,8 @@
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/* Driver output control */
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#define SSD1289_OUTCTRL_MUX_SHIFT (0) /* Number of lines for the LCD driver */
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#define SSD1289_OUTCTRL_MUX_MASK (0x1ff < SSD1289_OUTCTRL_MUX_SHIFT)
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# define SSD1289_OUTCTRL_MUX(n) ((n) < SSD1289_OUTCTRL_MUX_SHIFT)
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#define SSD1289_OUTCTRL_MUX_MASK (0x1ff << SSD1289_OUTCTRL_MUX_SHIFT)
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# define SSD1289_OUTCTRL_MUX(n) ((n) << SSD1289_OUTCTRL_MUX_SHIFT)
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#define SSD1289_OUTCTRL_TB (1 << 9) /* Selects the output shift direction of the gate driver */
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#define SSD1289_OUTCTRL_SM (1 << 10) /* Scanning order of gate driver */
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#define SSD1289_OUTCTRL_BGR (1 << 11) /* Order from RGB to BGR in 18-bit GDDRAM data */
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@ -285,7 +285,7 @@
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/* Power control 4 */
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#define SSD1289_PWRCTRL4_VDV_SHIFT (9) /* Set amplitude magnification of VLCD63 */
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#define SSD1289_PWRCTRL4_VDV_SHIFT (8) /* Set amplitude magnification of VLCD63 */
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#define SSD1289_PWRCTRL4_VDV_MASK (32 << SSD1289_PWRCTRL4_VDV_SHIFT)
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# define SSD1289_PWRCTRL4_VDV(n) ((n) << SSD1289_PWRCTRL4_VDV_SHIFT)
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#define SSD1289_PWRCTRL4_VCOMG (1 << 13) /* VcomL variable */
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