Fleshs out a few more things needed to compile and build the S32K118EVB board configuration.
Squashed commit of the following:
arch/arm/include: Add interrupt IRQ numbers.
tools/: Add support for the S32K1XX family.
This commit is contained in:
Gregory Nutt
parent
8987a9e374
commit
2a228e8650
@ -46,6 +46,30 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value. The lower the value, the greater the
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* priority of the corresponding interrupt.
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*/
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#if defined(CONFIG_ARCH_CORTEXM4)
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/* The Cortex-M4F core supports 16 programmable interrupt priority levels. */
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# define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
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# define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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# define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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# define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
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#elif defined(CONFIG_ARCH_CORTEXM0)
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/* The Cortex-M0+ core supports 4 programmable interrupt priority levels. */
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# define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:4] set is minimum priority */
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# define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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# define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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# define NVIC_SYSH_PRIORITY_STEP 0x40 /* Steps between priorities */
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -47,9 +47,9 @@
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#include <nuttx/config.h>
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#if defined(CONFIG_ARCH_CHIP_S32K11X)
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# include <arch/chip/s32k11x_irq.h
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# include <arch/chip/s32k11x_irq.h>
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#elif defined(CONFIG_ARCH_CHIP_S32K14X)
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# include <arch/chip/s32k14x_irq.h
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# include <arch/chip/s32k14x_irq.h>
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#else
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# error Unrecognized S32K1XX part
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#endif
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@ -57,20 +57,59 @@
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/* Processor Exceptions (vectors 0-15) */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define S32K_IRQ_INTERRUPT (16)
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#warning Missing logic
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#define S32K_IRQ_INTERRUPT (16)
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#define S32K_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K_IRQ_DMACH_ERR (20) /* DMA error interrupt channels 0-15 */
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#define S32K_IRQ_ERM (21) /* ERM single/double bit error */
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#define S32K_IRQ_RTC_ALARM (22) /* RTC alarm interrupt */
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#define S32K_IRQ_RTC_SEC (23) /* RTC seconds interrupt */
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#define S32K_IRQ_LPTIMER (24) /* LPTIMER interrupt request */
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#define S32K_IRQ_PORT (25) /* PORTA-E Interrupt */
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#define S32K_IRQ_CAN0 (26) /* CAN0 OR'ed Interrupt */
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#define S32K_IRQ_CAN0_0_31 (27) /* CAN0 OR'ed Message buffer (0-31) */
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#define S32K_IRQ_FTM0_CH0_7 (28) /* FTM0 Channel 0..7 Interrupt */
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#define S32K_IRQ_FTM0_FAULT (29) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM0_OVERFLOW (30) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM1_CH0_7 (31) /* FTM1 Channel 0..7 Interrupt */
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#define S32K_IRQ_FTM1_FAULT (32) /* FTM1 Fault Interrupt */
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#define S32K_IRQ_FTM1_OVERFLOW (33) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTFC (34) /* FTFC Command Complete, Collision, Double bit */
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#define S32K_IRQ_PDB (35) /* PDB Interrupt */
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#define S32K_IRQ_LPIT (36) /* LPIT Interrupt */
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#define S32K_IRQ_PMC (37) /* PMC Interrupt */
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#define S32K_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K_IRQ_LPI2C0 (40) /* LPI2C Master/Slave Interrupt */
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#define S32K_IRQ_FLEXIO (41) /* FlexIO Interrupt */
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#define S32K_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K_IRQ_ADC0 (44) /* ADC0 Interrupt */
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#define S32K_IRQ_CMP0 (45) /* CMP0 Interrupt */
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#define S32K_IRQ_LPUART1 (46) /* LPUART1 Interrupt */
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#define S32K_IRQ_LPUART1 (47) /* LPUART0 Interrupt */
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#define S32K_IRQ_NIRQS (48)
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#define S32K_IRQ_NEXTINT (S32K_IRQ_NIRQS - S32K_IRQ_FIRST)
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/* Total number of IRQ numbers */
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#define NR_IRQS S32K_IRQ_NIRQS
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#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H */
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@ -59,24 +59,171 @@
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/* Processor Exceptions (vectors 0-15) */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define S32K_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define S32K_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define S32K_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define S32K_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define S32K_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define S32K_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define S32K_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define S32K_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define S32K_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define S32K_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define S32K_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define S32K_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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#warning Missing logic
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#define S32K_IRQ_FIRST (16) /* Vector number of the first external interrupt */
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#define S32K_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K_IRQ_DMACH4 (20) /* DMA channel 4 transfer complete */
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#define S32K_IRQ_DMACH5 (21) /* DMA channel 5 transfer complete */
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#define S32K_IRQ_DMACH6 (22) /* DMA channel 6 transfer complete */
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#define S32K_IRQ_DMACH7 (23) /* DMA channel 7 transfer complete */
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#define S32K_IRQ_DMACH8 (24) /* DMA channel 8 transfer complete */
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#define S32K_IRQ_DMACH9 (25) /* DMA channel 9 transfer complete */
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#define S32K_IRQ_DMACH10 (26) /* DMA channel 10 transfer complete */
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#define S32K_IRQ_DMACH11 (27) /* DMA channel 11 transfer complete */
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#define S32K_IRQ_DMACH12 (28) /* DMA channel 12 transfer complete */
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#define S32K_IRQ_DMACH13 (29) /* DMA channel 13 transfer complete */
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#define S32K_IRQ_DMACH14 (30) /* DMA channel 14 transfer complete */
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#define S32K_IRQ_DMACH15 (31) /* DMA channel 15 transfer complete */
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#define S32K_IRQ_DMACH_ERR (32) /* DMA error interrupt channels 0-15 */
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#define S32K_IRQ_MCM (33) /* FPU sources */
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#define S32K_IRQ_FTFCCMD (34) /* FTFC command complete */
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#define S32K_IRQ_FTFCCOL (35) /* FTFC read collition */
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#define S32K_IRQ_PMC (36) /* PMC Low voltage detect interrupt */
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#define S32K_IRQ_FTFCDBL (37) /* FTFC Double bit */
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#define S32K_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K_IRQ_EWM (38) /* EWM output as interrupt */
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#define S32K_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K_IRQ_LPI2C0M (40) /* LPI2C Master Interrupt */
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#define S32K_IRQ_LPI2C0S (41) /* LPI2C Slave Interrupt */
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#define S32K_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K_IRQ_LPSPI2 (44) /* LPSPI2 Interrupt */
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#define S32K_IRQ_LPI2C1M (45) /* LPI21 Master Interrupt */
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#define S32K_IRQ_LPI2C1S (46) /* LPI21 Slave Interrupt */
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#define S32K_IRQ_LPUART0 (47) /* LPUART0 Interrupt */
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/* Reserved (48) */
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#define S32K_IRQ_LPUART1 (49) /* LPUART1 Interrupt */
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/* Reserved (50) */
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#define S32K_IRQ_LPUART2 (51) /* LPUART0 Interrupt */
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/* Reserved (52-54) */
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#define S32K_IRQ_ADC0 (55) /* ADC0 Interrupt */
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#define S32K_IRQ_ADC1 (56) /* ADC1 Interrupt */
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#define S32K_IRQ_CMP0 (57) /* CMP0 Interrupt */
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/* Reserved (58-59) */
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#define S32K_IRQ_ERMS (60) /* ERM single bit error correction */
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#define S32K_IRQ_ERMD (61) /* ERM double bit error non-correctable */
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#define S32K_IRQ_RTC_ALARM (62) /* RTC alarm interrupt */
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#define S32K_IRQ_RTC_SEC (63) /* RTC seconds interrupt */
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#define S32K_IRQ_LPIT0 (64) /* LPIT interrupt */
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#define S32K_IRQ_LPIT1 (65) /* LPIT interrupt */
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#define S32K_IRQ_LPIT2 (66) /* LPIT interrupt */
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#define S32K_IRQ_LPIT3 (67) /* LPIT interrupt */
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#define S32K_IRQ_PDB0 (68) /* PDB0 interrupt */
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/* Reserved (69-70) */
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#define S32K_IRQ_SAI1TX (71) /* SAI1 Transmit Synchronous Interrupt */
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#define S32K_IRQ_SAI1RX (72) /* SAI1 Receive Synchronous Interrupt */
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#define S32K_IRQ_SCGBUS (73) /* SCG bus interrupt request */
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#define S32K_IRQ_LPTIMER (74) /* LPTIMER interrupt request */
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#define S32K_IRQ_PORTA (75) /* PORTA Interrupt */
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#define S32K_IRQ_PORTB (76) /* PORTB Interrupt */
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#define S32K_IRQ_PORTC (77) /* PORTC Interrupt */
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#define S32K_IRQ_PORTD (78) /* PORTD Interrupt */
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#define S32K_IRQ_PORTE (79) /* PORTE Interrupt */
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#define S32K_IRQ_SOFTWARE (80) /* Software Interrupt */
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#define S32K_IRQ_QUADSPI (81) /* QuadSPI Interrupts */
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/* Reserved (82-83) */
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#define S32K_IRQ_PDB1 (84) /* PDB1 Interrupt */
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#define S32K_IRQ_FLEXIO (85) /* FlexIO Interrupt */
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#define S32K_IRQ_SAI0_TX (86) /* SAI0 Transmit Synchronous Interrupt */
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#define S32K_IRQ_SAI0_RX (87) /* SAI0 Receive Synchronous Interrupt */
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#define S32K_IRQ_ENET_TIMER (88) /* ENET 1588 timer, time stamp, etc. */
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#define S32K_IRQ_ENET_TXDONE (89) /* ENET Data Tx Transfer Done Interrupt */
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#define S32K_IRQ_ENET_RXDONE (90) /* ENET Data Rx Transfer Done Interrupt */
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#define S32K_IRQ_ENET_ERROR (91) /* ENET Error Interrupt */
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#define S32K_IRQ_ENET_STOP (92) /* ENET Graceful Stop Interrupt */
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#define S32K_IRQ_ENET_WAKE (93) /* ENET Wake from Sleep Interrupt */
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#define S32K_IRQ_CAN0_BUS (94) /* CAN0 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN0_ERROR (95) /* CAN0 Bus Error Interrupt */
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#define S32K_IRQ_CAN0_LPRX (96) /* CAN0 Message Rx/Timeout in low power mode */
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#define S32K_IRQ_CAN0_0_15 (97) /* CAN0 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN0_16_31 (98) /* CAN0 OR'ed Message buffer (16-31) */
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/* Reserved (99-100) */
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#define S32K_IRQ_CAN1_BUS (101) /* CAN1 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN1_ERROR (102) /* CAN1 Bus Error Interrupt */
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/* Reserved (103) */
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#define S32K_IRQ_CAN1_0_15 (104) /* CAN1 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN1_16_31 (105) /* CAN1 OR'ed Message buffer (16-31) */
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/* Reserved (106-107) */
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#define S32K_IRQ_CAN2_BUS (108) /* CAN2 Bus On/Off Tx/Rx Warning */
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#define S32K_IRQ_CAN2_ERROR (109) /* CAN2 Bus Error Interrupt */
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/* Reserved (110) */
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#define S32K_IRQ_CAN2_0_15 (111) /* CAN2 OR'ed Message buffer (0-15) */
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#define S32K_IRQ_CAN2_16_31 (112) /* CAN2 OR'ed Message buffer (16-31) */
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/* Reserved (113-114) */
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#define S32K_IRQ_FTM0_CH0_1 (115) /* FTM0 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM0_CH2_2 (116) /* FTM0 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM0_CH4_5 (117) /* FTM0 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM0_CH6_7 (118) /* FTM0 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM0_FAULT (119) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM0_OVERFLOW (120) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM1_CH0_1 (121) /* FTM1 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM1_CH2_2 (122) /* FTM1 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM1_CH4_5 (123) /* FTM1 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM1_CH6_7 (124) /* FTM1 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM1_FAULT (125) /* FTM1 Fault Interrupt */
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#define S32K_IRQ_FTM1_OVERFLOW (126) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM2_CH0_1 (127) /* FTM0 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM2_CH2_2 (128) /* FTM0 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM2_CH4_5 (129) /* FTM0 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM2_CH6_7 (130) /* FTM0 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM2_FAULT (131) /* FTM0 Fault Interrupt */
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#define S32K_IRQ_FTM2_OVERFLOW (132) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM3_CH0_1 (133) /* FTM3 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM3_CH2_2 (134) /* FTM3 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM3_CH4_5 (135) /* FTM3 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM3_CH6_7 (136) /* FTM3 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM3_FAULT (137) /* FTM3 Fault Interrupt */
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#define S32K_IRQ_FTM3_OVERFLOW (138) /* FTM3 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM4_CH0_1 (139) /* FTM4 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM4_CH2_2 (140) /* FTM4 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM4_CH4_5 (141) /* FTM4 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM4_CH6_7 (142) /* FTM4 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM4_FAULT (143) /* FTM4 Fault Interrupt */
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#define S32K_IRQ_FTM4_OVERFLOW (144) /* FTM4 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM5_CH0_1 (145) /* FTM5 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM5_CH2_2 (146) /* FTM5 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM5_CH4_5 (147) /* FTM5 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM5_CH6_7 (148) /* FTM5 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM5_FAULT (149) /* FTM5 Fault Interrupt */
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#define S32K_IRQ_FTM5_OVERFLOW (150) /* FTM5 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM6_CH0_1 (151) /* FTM6 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM6_CH2_2 (152) /* FTM6 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM6_CH4_5 (153) /* FTM6 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM6_CH6_7 (154) /* FTM6 Channel 6/7 Interrupt */
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#define S32K_IRQ_FTM6_FAULT (155) /* FTM6 Fault Interrupt */
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#define S32K_IRQ_FTM6_OVERFLOW (156) /* FTM6 Counter Overflow/Reload Interrupt */
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#define S32K_IRQ_FTM7_CH0_1 (157) /* FTM7 Channel 0/1 Interrupt */
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#define S32K_IRQ_FTM7_CH2_2 (158) /* FTM7 Channel 2/3 Interrupt */
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#define S32K_IRQ_FTM7_CH4_5 (159) /* FTM7 Channel 4/5 Interrupt */
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#define S32K_IRQ_FTM7_CH6_7 (160) /* FTM7 Channel 6/7 Interrupt */
|
||||
#define S32K_IRQ_FTM7_FAULT (161) /* FTM7 Fault Interrupt */
|
||||
#define S32K_IRQ_FTM7_OVERFLOW (162) /* FTM7 Counter Overflow/Reload Interrupt */
|
||||
|
||||
#define S32K_IRQ_NIRQS (163)
|
||||
#define S32K_IRQ_NEXTINT (S32K_IRQ_NIRQS - S32K_IRQ_FIRST)
|
||||
|
||||
/* Total number of IRQ numbers */
|
||||
|
||||
#define NR_IRQS S32K_IRQ_NIRQS
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K14XX_IRQ_H */
|
||||
|
||||
|
||||
77
arch/arm/src/s32k1xx/chip.h
Normal file
77
arch/arm/src/s32k1xx/chip.h
Normal file
@ -0,0 +1,77 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/s32k1xx/chip.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
|
||||
#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the memory map and the chip definitions file. Other chip hardware files
|
||||
* should then include this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include "hardware/s32k1xx_memorymap.h"
|
||||
|
||||
/* The common ARMv6/7-M vector handling logic expects the following definitions in
|
||||
* this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
|
||||
* external interrupts which, for this architecture, is provided in the
|
||||
* arch/s32k1xx/irq.h header file.
|
||||
*/
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS S32K_IRQ_NEXTINT
|
||||
#define ARMV7M_PERIPHERAL_INTERRUPTS S32K_IRQ_NEXTINT
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
|
||||
@ -51,7 +51,7 @@
|
||||
# define S32K1XX_DMAC_BASE 0x40008000 /* DMA controller */
|
||||
# define S32K1XX_DMADESC_BASE 0x40008000 /* DMA transfer control descriptors */
|
||||
# define S32K1XX_MPU_BASE 0x4000d000 /* MPU */
|
||||
# define S32K1XX_GPIOC_BASE 0x4000f000 /* GPIO controller */
|
||||
# define S32K1XX_GPIOCTL_BASE 0x4000f000 /* GPIO controller */
|
||||
# define S32K1XX_GPIOALIAS_BASE 0x400ff000 /* GPIO controller (alias) */
|
||||
# define S32K1XX_ERM_BASE 0x40018000 /* ERM */
|
||||
# define S32K1XX_EIM_BASE 0x40019000 /* EIM */
|
||||
|
||||
@ -192,6 +192,7 @@ static const char *g_chipnames[] =
|
||||
"moxart",
|
||||
"nrf52",
|
||||
"nuc1xx",
|
||||
"s32k1xx",
|
||||
"sam34",
|
||||
"sama5",
|
||||
"samd2l2",
|
||||
|
||||
@ -140,7 +140,7 @@ fi
|
||||
archs="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
|
||||
chips="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
|
||||
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
|
||||
nuc1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
|
||||
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
|
||||
ez80 z180 z8 z80"
|
||||
|
||||
@ -118,7 +118,7 @@ ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
|
||||
ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
|
||||
CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
|
||||
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
|
||||
nuc1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
|
||||
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
|
||||
ez80 z180 z8 z80"
|
||||
|
||||
@ -295,7 +295,7 @@ for line in $testlist; do
|
||||
ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80"
|
||||
CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450
|
||||
lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52
|
||||
nuc1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7
|
||||
stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx
|
||||
pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811
|
||||
ez80 z180 z8 z80"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user