Updated comments; minor correction in some naming
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@ -498,11 +498,25 @@
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* NMRR[19:18] = 0b00, Region is Non-cacheable
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* NMRR[19:18] = 0b00, Region is Non-cacheable
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* NMRR[21:20] = 0b10, Region is Write-Through, no Write-Allocate
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* NMRR[21:20] = 0b10, Region is Write-Through, no Write-Allocate
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* NMRR[23:22] = 0b11, Region is Write-Back, no Write-Allocate
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* NMRR[23:22] = 0b11, Region is Write-Back, no Write-Allocate
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*
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* Interpretation of Cacheable (C) and Bufferable (B) Bits:
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*
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* Write-Through Write-Back Write-Through/Write-Back
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* C B Cache Only Cache Cache
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* --- --- -------------- ------------- -------------------------
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* 0 0 Uncached/ Uncached/ Uncached/
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* Unbuffered Unbuffered Unbuffered
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* 0 1 Uncached/ Uncached/ Uncached/
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* Buffered Buffered Buffered
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* 1 0 Cached/ UNPREDICTABLE Write-Through cached
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* Unbuffered Buffered
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* 1 1 Cached/ Cached/ Write-Back cached
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* Buffered Buffered Buffered
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*/
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*/
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#define PMD_STRONGLY_ORDERED (0)
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#define PMD_STRONGLY_ORDERED (0)
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#define PMD_DEVICE (PMD_SECT_B)
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#define PMD_DEVICE (PMD_SECT_B)
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#define PM_CACHEABLE (PMD_SECT_B | PMD_SECT_C)
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#define PMD_CACHEABLE (PMD_SECT_B | PMD_SECT_C)
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#define PTE_STRONGLY_ORDER (0)
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#define PTE_STRONGLY_ORDER (0)
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#define PTE_DEVICE (PTE_B)
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#define PTE_DEVICE (PTE_B)
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@ -514,9 +528,9 @@
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* REVISIT: Here we expect all threads to be running at PL1
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* REVISIT: Here we expect all threads to be running at PL1
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*/
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*/
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#define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PM_CACHEABLE | \
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#define MMU_ROMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_R1 | PMD_CACHEABLE | \
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PMD_SECT_DOM(0))
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PMD_SECT_DOM(0))
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#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PM_CACHEABLE | \
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#define MMU_MEMFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_CACHEABLE | \
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PMD_SECT_DOM(0))
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PMD_SECT_DOM(0))
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#define MMU_IOFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \
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#define MMU_IOFLAGS (PMD_TYPE_SECT | PMD_SECT_AP_RW1 | PMD_DEVICE | \
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PMD_SECT_DOM(0) | PMD_SECT_XN)
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PMD_SECT_DOM(0) | PMD_SECT_XN)
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