diff --git a/arch/arm/src/imx6/Make.defs b/arch/arm/src/imx6/Make.defs index 43771dc63e..bc6502d47a 100644 --- a/arch/arm/src/imx6/Make.defs +++ b/arch/arm/src/imx6/Make.defs @@ -133,4 +133,4 @@ CHIP_ASRCS = # i.MX6-specific C source files CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_irq.c -CHIP_CSRCS = imx_gpio.c # imx_serial.c +CHIP_CSRCS = imx_gpio.c imx_iomuxc.c # imx_serial.c diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c index c1d2175924..fe4c7b513b 100644 --- a/arch/arm/src/imx6/imx_gpio.c +++ b/arch/arm/src/imx6/imx_gpio.c @@ -428,7 +428,7 @@ static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) return -EINVAL; } - index = table[pin]; + index = (unsigned int)table[pin]; if (index >= IMX_PADMUX_NREGISTERS) { return -EINVAL; @@ -438,9 +438,16 @@ static inline int imx_gpio_configinput(gpio_pinset_t pinset, int port, int pin) putreg32(PADMUX_MUXMODE_ALT5, regaddr); /* Configure pin pad settings */ -#warning Missing logic - return OK; + index = imx_padmux_map(index); + index = table[pin]; + if (index >= IMX_PADCTL_NREGISTERS) + { + return -EINVAL; + } + + regaddr = IMX_PADCTL_ADDRESS(index); + return imx_iomux_configure(regaddr, pinset); } /**************************************************************************** diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h index c8f3661ede..2eb2dc11b6 100644 --- a/arch/arm/src/imx6/imx_gpio.h +++ b/arch/arm/src/imx6/imx_gpio.h @@ -229,7 +229,7 @@ extern "C" #ifdef CONFIG_IMX6_GPIO_IRQ void imx_gpioirq_initialize(void); #else -# define imx_gpioirqinitialize() +# define imx_gpio_irqinitialize() #endif /************************************************************************************ diff --git a/arch/arm/src/imx6/imx_iomuxc.c b/arch/arm/src/imx6/imx_iomuxc.c new file mode 100644 index 0000000000..e5ccc2361a --- /dev/null +++ b/arch/arm/src/imx6/imx_iomuxc.c @@ -0,0 +1,365 @@ +/**************************************************************************** + * arch/arm/src/imx6/imx_irq.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "imx_iomuxc.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* This table is indexed by the Pad Mux register index and provides the index + * to the corresponding Pad Control register. + * + * REVISIT: This could be greatly simplified: The Pad Control registers + * map 1-to-1 with the Pad Mux registers except for two regions where + * there are no corresponding Pad Mux registers. + */ + +static const uint8_t g_mux2ctl_map[IMX_PADMUX_NREGISTERS] = +{ + /* The first mappings are simple 1-to-1 mappings. This may be a little wasteful */ + + IMX_PADCTL_SD2_DATA1_INDEX, /* IMX_PADMUX_SD2_DATA1_INDEX */ + IMX_PADCTL_SD2_DATA2_INDEX, /* IMX_PADMUX_SD2_DATA2_INDEX */ + IMX_PADCTL_SD2_DATA0_INDEX, /* IMX_PADMUX_SD2_DATA0_INDEX */ + IMX_PADCTL_RGMII_TXC_INDEX, /* IMX_PADMUX_RGMII_TXC_INDEX */ + IMX_PADCTL_RGMII_TD0_INDEX, /* IMX_PADMUX_RGMII_TD0_INDEX */ + IMX_PADCTL_RGMII_TD1_INDEX, /* IMX_PADMUX_RGMII_TD1_INDEX */ + IMX_PADCTL_RGMII_TD2_INDEX, /* IMX_PADMUX_RGMII_TD2_INDEX */ + IMX_PADCTL_RGMII_TD3_INDEX, /* IMX_PADMUX_RGMII_TD3_INDEX */ + IMX_PADCTL_RGMII_RX_CTL_INDEX, /* IMX_PADMUX_RGMII_RX_CTL_INDEX */ + IMX_PADCTL_RGMII_RD0_INDEX, /* IMX_PADMUX_RGMII_RD0_INDEX */ + IMX_PADCTL_RGMII_TX_CTL_INDEX, /* IMX_PADMUX_RGMII_TX_CTL_INDEX */ + IMX_PADCTL_RGMII_RD1_INDEX, /* IMX_PADMUX_RGMII_RD1_INDEX */ + IMX_PADCTL_RGMII_RD2_INDEX, /* IMX_PADMUX_RGMII_RD2_INDEX */ + IMX_PADCTL_RGMII_RD3_INDEX, /* IMX_PADMUX_RGMII_RD3_INDEX */ + IMX_PADCTL_RGMII_RXC_INDEX, /* IMX_PADMUX_RGMII_RXC_INDEX */ + IMX_PADCTL_EIM_ADDR25_INDEX, /* IMX_PADMUX_EIM_ADDR25_INDEX */ + IMX_PADCTL_EIM_EB2_INDEX, /* IMX_PADMUX_EIM_EB2_INDEX */ + IMX_PADCTL_EIM_DATA16_INDEX, /* IMX_PADMUX_EIM_DATA16_INDEX */ + IMX_PADCTL_EIM_DATA17_INDEX, /* IMX_PADMUX_EIM_DATA17_INDEX */ + IMX_PADCTL_EIM_DATA18_INDEX, /* IMX_PADMUX_EIM_DATA18_INDEX */ + IMX_PADCTL_EIM_DATA19_INDEX, /* IMX_PADMUX_EIM_DATA19_INDEX */ + IMX_PADCTL_EIM_DATA20_INDEX, /* IMX_PADMUX_EIM_DATA20_INDEX */ + IMX_PADCTL_EIM_DATA21_INDEX, /* IMX_PADMUX_EIM_DATA21_INDEX */ + IMX_PADCTL_EIM_DATA22_INDEX, /* IMX_PADMUX_EIM_DATA22_INDEX */ + IMX_PADCTL_EIM_DATA23_INDEX, /* IMX_PADMUX_EIM_DATA23_INDEX */ + IMX_PADCTL_EIM_EB3_INDEX, /* IMX_PADMUX_EIM_EB3_INDEX */ + IMX_PADCTL_EIM_DATA24_INDEX, /* IMX_PADMUX_EIM_DATA24_INDEX */ + IMX_PADCTL_EIM_DATA25_INDEX, /* IMX_PADMUX_EIM_DATA25_INDEX */ + IMX_PADCTL_EIM_DATA26_INDEX, /* IMX_PADMUX_EIM_DATA26_INDEX */ + IMX_PADCTL_EIM_DATA27_INDEX, /* IMX_PADMUX_EIM_DATA27_INDEX */ + IMX_PADCTL_EIM_DATA28_INDEX, /* IMX_PADMUX_EIM_DATA28_INDEX */ + IMX_PADCTL_EIM_DATA29_INDEX, /* IMX_PADMUX_EIM_DATA29_INDEX */ + IMX_PADCTL_EIM_DATA30_INDEX, /* IMX_PADMUX_EIM_DATA30_INDEX */ + IMX_PADCTL_EIM_DATA31_INDEX, /* IMX_PADMUX_EIM_DATA31_INDEX */ + IMX_PADCTL_EIM_ADDR24_INDEX, /* IMX_PADMUX_EIM_ADDR24_INDEX */ + IMX_PADCTL_EIM_ADDR23_INDEX, /* IMX_PADMUX_EIM_ADDR23_INDEX */ + IMX_PADCTL_EIM_ADDR22_INDEX, /* IMX_PADMUX_EIM_ADDR22_INDEX */ + IMX_PADCTL_EIM_ADDR21_INDEX, /* IMX_PADMUX_EIM_ADDR21_INDEX */ + IMX_PADCTL_EIM_ADDR20_INDEX, /* IMX_PADMUX_EIM_ADDR20_INDEX */ + IMX_PADCTL_EIM_ADDR19_INDEX, /* IMX_PADMUX_EIM_ADDR19_INDEX */ + IMX_PADCTL_EIM_ADDR18_INDEX, /* IMX_PADMUX_EIM_ADDR18_INDEX */ + IMX_PADCTL_EIM_ADDR17_INDEX, /* IMX_PADMUX_EIM_ADDR17_INDEX */ + IMX_PADCTL_EIM_ADDR16_INDEX, /* IMX_PADMUX_EIM_ADDR16_INDEX */ + IMX_PADCTL_EIM_CS0_INDEX, /* IMX_PADMUX_EIM_CS0_INDEX */ + IMX_PADCTL_EIM_CS1_INDEX, /* IMX_PADMUX_EIM_CS1_INDEX */ + IMX_PADCTL_EIM_OE_INDEX, /* IMX_PADMUX_EIM_OE_INDEX */ + IMX_PADCTL_EIM_RW_INDEX, /* IMX_PADMUX_EIM_RW_INDEX */ + IMX_PADCTL_EIM_LBA_INDEX, /* IMX_PADMUX_EIM_LBA_INDEX */ + IMX_PADCTL_EIM_EB0_INDEX, /* IMX_PADMUX_EIM_EB0_INDEX */ + IMX_PADCTL_EIM_EB1_INDEX, /* IMX_PADMUX_EIM_EB1_INDEX */ + IMX_PADCTL_EIM_AD00_INDEX, /* IMX_PADMUX_EIM_AD00_INDEX */ + IMX_PADCTL_EIM_AD01_INDEX, /* IMX_PADMUX_EIM_AD01_INDEX */ + IMX_PADCTL_EIM_AD02_INDEX, /* IMX_PADMUX_EIM_AD02_INDEX */ + IMX_PADCTL_EIM_AD03_INDEX, /* IMX_PADMUX_EIM_AD03_INDEX */ + IMX_PADCTL_EIM_AD04_INDEX, /* IMX_PADMUX_EIM_AD04_INDEX */ + IMX_PADCTL_EIM_AD05_INDEX, /* IMX_PADMUX_EIM_AD05_INDEX */ + IMX_PADCTL_EIM_AD06_INDEX, /* IMX_PADMUX_EIM_AD06_INDEX */ + IMX_PADCTL_EIM_AD07_INDEX, /* IMX_PADMUX_EIM_AD07_INDEX */ + IMX_PADCTL_EIM_AD08_INDEX, /* IMX_PADMUX_EIM_AD08_INDEX */ + IMX_PADCTL_EIM_AD09_INDEX, /* IMX_PADMUX_EIM_AD09_INDEX */ + IMX_PADCTL_EIM_AD10_INDEX, /* IMX_PADMUX_EIM_AD10_INDEX */ + IMX_PADCTL_EIM_AD11_INDEX, /* IMX_PADMUX_EIM_AD11_INDEX */ + IMX_PADCTL_EIM_AD12_INDEX, /* IMX_PADMUX_EIM_AD12_INDEX */ + IMX_PADCTL_EIM_AD13_INDEX, /* IMX_PADMUX_EIM_AD13_INDEX */ + IMX_PADCTL_EIM_AD14_INDEX, /* IMX_PADMUX_EIM_AD14_INDEX */ + IMX_PADCTL_EIM_AD15_INDEX, /* IMX_PADMUX_EIM_AD15_INDEX */ + IMX_PADCTL_EIM_WAIT_INDEX, /* IMX_PADMUX_EIM_WAIT_INDEX */ + IMX_PADCTL_EIM_BCLK_INDEX, /* IMX_PADMUX_EIM_BCLK_INDEX */ + IMX_PADCTL_DI0_DISP_CLK_INDEX, /* IMX_PADMUX_DI0_DISP_CLK_INDEX */ + IMX_PADCTL_DI0_PIN15_INDEX, /* IMX_PADMUX_DI0_PIN15_INDEX */ + IMX_PADCTL_DI0_PIN02_INDEX, /* IMX_PADMUX_DI0_PIN02_INDEX */ + IMX_PADCTL_DI0_PIN03_INDEX, /* IMX_PADMUX_DI0_PIN03_INDEX */ + IMX_PADCTL_DI0_PIN04_INDEX, /* IMX_PADMUX_DI0_PIN04_INDEX */ + IMX_PADCTL_DISP0_DATA00_INDEX, /* IMX_PADMUX_DISP0_DATA00_INDEX */ + IMX_PADCTL_DISP0_DATA01_INDEX, /* IMX_PADMUX_DISP0_DATA01_INDEX */ + IMX_PADCTL_DISP0_DATA02_INDEX, /* IMX_PADMUX_DISP0_DATA02_INDEX */ + IMX_PADCTL_DISP0_DATA03_INDEX, /* IMX_PADMUX_DISP0_DATA03_INDEX */ + IMX_PADCTL_DISP0_DATA04_INDEX, /* IMX_PADMUX_DISP0_DATA04_INDEX */ + IMX_PADCTL_DISP0_DATA05_INDEX, /* IMX_PADMUX_DISP0_DATA05_INDEX */ + IMX_PADCTL_DISP0_DATA06_INDEX, /* IMX_PADMUX_DISP0_DATA06_INDEX */ + IMX_PADCTL_DISP0_DATA07_INDEX, /* IMX_PADMUX_DISP0_DATA07_INDEX */ + IMX_PADCTL_DISP0_DATA08_INDEX, /* IMX_PADMUX_DISP0_DATA08_INDEX */ + IMX_PADCTL_DISP0_DATA09_INDEX, /* IMX_PADMUX_DISP0_DATA09_INDEX */ + IMX_PADCTL_DISP0_DATA10_INDEX, /* IMX_PADMUX_DISP0_DATA10_INDEX */ + IMX_PADCTL_DISP0_DATA11_INDEX, /* IMX_PADMUX_DISP0_DATA11_INDEX */ + IMX_PADCTL_DISP0_DATA12_INDEX, /* IMX_PADMUX_DISP0_DATA12_INDEX */ + IMX_PADCTL_DISP0_DATA13_INDEX, /* IMX_PADMUX_DISP0_DATA13_INDEX */ + IMX_PADCTL_DISP0_DATA14_INDEX, /* IMX_PADMUX_DISP0_DATA14_INDEX */ + IMX_PADCTL_DISP0_DATA15_INDEX, /* IMX_PADMUX_DISP0_DATA15_INDEX */ + + + IMX_PADCTL_DISP0_DATA16_INDEX, /* IMX_PADMUX_DISP0_DATA16_INDEX */ + IMX_PADCTL_DISP0_DATA17_INDEX, /* IMX_PADMUX_DISP0_DATA17_INDEX */ + IMX_PADCTL_DISP0_DATA18_INDEX, /* IMX_PADMUX_DISP0_DATA18_INDEX */ + IMX_PADCTL_DISP0_DATA19_INDEX, /* IMX_PADMUX_DISP0_DATA19_INDEX */ + IMX_PADCTL_DISP0_DATA20_INDEX, /* IMX_PADMUX_DISP0_DATA20_INDEX */ + IMX_PADCTL_DISP0_DATA21_INDEX, /* IMX_PADMUX_DISP0_DATA21_INDEX */ + IMX_PADCTL_DISP0_DATA22_INDEX, /* IMX_PADMUX_DISP0_DATA22_INDEX */ + IMX_PADCTL_DISP0_DATA23_INDEX, /* IMX_PADMUX_DISP0_DATA23_INDEX */ + IMX_PADCTL_ENET_MDIO_INDEX, /* IMX_PADMUX_ENET_MDIO_INDEX */ + IMX_PADCTL_ENET_REF_CLK_INDEX, /* IMX_PADMUX_ENET_REF_CLK_INDEX */ + IMX_PADCTL_ENET_RX_ER_INDEX, /* IMX_PADMUX_ENET_RX_ER_INDEX */ + IMX_PADCTL_ENET_CRS_DV_INDEX, /* IMX_PADMUX_ENET_CRS_DV_INDEX */ + IMX_PADCTL_ENET_RX_DATA1_INDEX, /* IMX_PADMUX_ENET_RX_DATA1_INDEX */ + IMX_PADCTL_ENET_RX_DATA0_INDEX, /* IMX_PADMUX_ENET_RX_DATA0_INDEX */ + IMX_PADCTL_ENET_TX_EN_INDEX, /* IMX_PADMUX_ENET_TX_EN_INDEX */ + IMX_PADCTL_ENET_TX_DATA1_INDEX, /* IMX_PADMUX_ENET_TX_DATA1_INDEX */ + IMX_PADCTL_ENET_TX_DATA0_INDEX, /* IMX_PADMUX_ENET_TX_DATA0_INDEX */ + IMX_PADCTL_ENET_MDC_INDEX, /* IMX_PADMUX_ENET_MDC_INDEX */ + + /* There is then a group of Pad Control registers with no Pad Mux register counterpart */ + + /* IMX_PADCTL_DRAM_SDQS5_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM5_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM4_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS4_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS3_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM3_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS2_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM2_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR00_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR01_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR02_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR03_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR04_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR05_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR06_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR07_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR08_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR09_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR10_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR11_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR12_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR13_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR14_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ADDR15_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_CAS_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_CS0_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_CS1_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_RAS_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_RESET_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDBA0_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDBA1_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDCLK0_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDBA2_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDCKE0_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDCLK1_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDCKE1_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ODT0_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_ODT1_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDWE_B_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS0_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM0_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS1_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM1_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS6_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM6_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_SDQS7_P_INDEX - No counterpart */ + /* IMX_PADCTL_DRAM_DQM7_INDEX - No counterpart */ + + /* The mapping is again 1-to-1 with an offset for the above registers that + * have no Pad Mux register counterpart. + */ + + IMX_PADCTL_KEY_COL0_INDEX, /* IMX_PADMUX_KEY_COL0_INDEX */ + IMX_PADCTL_KEY_ROW0_INDEX, /* IMX_PADMUX_KEY_ROW0_INDEX */ + IMX_PADCTL_KEY_COL1_INDEX, /* IMX_PADMUX_KEY_COL1_INDEX */ + IMX_PADCTL_KEY_ROW1_INDEX, /* IMX_PADMUX_KEY_ROW1_INDEX */ + IMX_PADCTL_KEY_COL2_INDEX, /* IMX_PADMUX_KEY_COL2_INDEX */ + IMX_PADCTL_KEY_ROW2_INDEX, /* IMX_PADMUX_KEY_ROW2_INDEX */ + IMX_PADCTL_KEY_COL3_INDEX, /* IMX_PADMUX_KEY_COL3_INDEX */ + IMX_PADCTL_KEY_ROW3_INDEX, /* IMX_PADMUX_KEY_ROW3_INDEX */ + IMX_PADCTL_KEY_COL4_INDEX, /* IMX_PADMUX_KEY_COL4_INDEX */ + IMX_PADCTL_KEY_ROW4_INDEX, /* IMX_PADMUX_KEY_ROW4_INDEX */ + IMX_PADCTL_GPIO00_INDEX, /* IMX_PADMUX_GPIO00_INDEX */ + IMX_PADCTL_GPIO01_INDEX, /* IMX_PADMUX_GPIO01_INDEX */ + IMX_PADCTL_GPIO09_INDEX, /* IMX_PADMUX_GPIO09_INDEX */ + IMX_PADCTL_GPIO03_INDEX, /* IMX_PADMUX_GPIO03_INDEX */ + IMX_PADCTL_GPIO06_INDEX, /* IMX_PADMUX_GPIO06_INDEX */ + IMX_PADCTL_GPIO02_INDEX, /* IMX_PADMUX_GPIO02_INDEX */ + IMX_PADCTL_GPIO04_INDEX, /* IMX_PADMUX_GPIO04_INDEX */ + IMX_PADCTL_GPIO05_INDEX, /* IMX_PADMUX_GPIO05_INDEX */ + IMX_PADCTL_GPIO07_INDEX, /* IMX_PADMUX_GPIO07_INDEX */ + IMX_PADCTL_GPIO08_INDEX, /* IMX_PADMUX_GPIO08_INDEX */ + IMX_PADCTL_GPIO16_INDEX, /* IMX_PADMUX_GPIO16_INDEX */ + IMX_PADCTL_GPIO17_INDEX, /* IMX_PADMUX_GPIO17_INDEX */ + IMX_PADCTL_GPIO18_INDEX, /* IMX_PADMUX_GPIO18_INDEX */ + IMX_PADCTL_GPIO19_INDEX, /* IMX_PADMUX_GPIO19_INDEX */ + IMX_PADCTL_CSI0_PIXCLK_INDEX, /* IMX_PADMUX_CSI0_PIXCLK_INDEX */ + IMX_PADCTL_CSI0_HSYNC_INDEX, /* IMX_PADMUX_CSI0_HSYNC_INDEX */ + IMX_PADCTL_CSI0_DATA_EN_INDEX, /* IMX_PADMUX_CSI0_DATA_EN_INDEX */ + IMX_PADCTL_CSI0_VSYNC_INDEX, /* IMX_PADMUX_CSI0_VSYNC_INDEX */ + IMX_PADCTL_CSI0_DATA04_INDEX, /* IMX_PADMUX_CSI0_DATA04_INDEX */ + IMX_PADCTL_CSI0_DATA05_INDEX, /* IMX_PADMUX_CSI0_DATA05_INDEX */ + IMX_PADCTL_CSI0_DATA06_INDEX, /* IMX_PADMUX_CSI0_DATA06_INDEX */ + IMX_PADCTL_CSI0_DATA07_INDEX, /* IMX_PADMUX_CSI0_DATA07_INDEX */ + IMX_PADCTL_CSI0_DATA08_INDEX, /* IMX_PADMUX_CSI0_DATA08_INDEX */ + IMX_PADCTL_CSI0_DATA09_INDEX, /* IMX_PADMUX_CSI0_DATA09_INDEX */ + IMX_PADCTL_CSI0_DATA10_INDEX, /* IMX_PADMUX_CSI0_DATA10_INDEX */ + IMX_PADCTL_CSI0_DATA11_INDEX, /* IMX_PADMUX_CSI0_DATA11_INDEX */ + IMX_PADCTL_CSI0_DATA12_INDEX, /* IMX_PADMUX_CSI0_DATA12_INDEX */ + IMX_PADCTL_CSI0_DATA13_INDEX, /* IMX_PADMUX_CSI0_DATA13_INDEX */ + IMX_PADCTL_CSI0_DATA14_INDEX, /* IMX_PADMUX_CSI0_DATA14_INDEX */ + IMX_PADCTL_CSI0_DATA15_INDEX, /* IMX_PADMUX_CSI0_DATA15_INDEX */ + IMX_PADCTL_CSI0_DATA16_INDEX, /* IMX_PADMUX_CSI0_DATA16_INDEX */ + IMX_PADCTL_CSI0_DATA17_INDEX, /* IMX_PADMUX_CSI0_DATA17_INDEX */ + IMX_PADCTL_CSI0_DATA18_INDEX, /* IMX_PADMUX_CSI0_DATA18_INDEX */ + IMX_PADCTL_CSI0_DATA19_INDEX, /* IMX_PADMUX_CSI0_DATA19_INDEX */ + + /* There is a second group of Pad Control registers with no Pad Mux register counterpart */ + + /* IMX_PADCTL_JTAG_TMS_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_MOD_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_TRSTB_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_TDI_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_TCK_INDEX - No counterpart */ + /* IMX_PADCTL_JTAG_TDO_INDEX - No counterpart */ + + /* The mapping is again 1-to-1 with an offset for the above registers that + * have no Pad Mux register counterpart. + */ + + IMX_PADCTL_SD3_DATA7_INDEX, /* IMX_PADMUX_SD3_DATA7_INDEX */ + IMX_PADCTL_SD3_DATA6_INDEX, /* IMX_PADMUX_SD3_DATA6_INDEX */ + IMX_PADCTL_SD3_DATA5_INDEX, /* IMX_PADMUX_SD3_DATA5_INDEX */ + IMX_PADCTL_SD3_DATA4_INDEX, /* IMX_PADMUX_SD3_DATA4_INDEX */ + IMX_PADCTL_SD3_CMD_INDEX, /* IMX_PADMUX_SD3_CMD_INDEX */ + IMX_PADCTL_SD3_CLK_INDEX, /* IMX_PADMUX_SD3_CLK_INDEX */ + IMX_PADCTL_SD3_DATA0_INDEX, /* IMX_PADMUX_SD3_DATA0_INDEX */ + IMX_PADCTL_SD3_DATA1_INDEX, /* IMX_PADMUX_SD3_DATA1_INDEX */ + IMX_PADCTL_SD3_DATA2_INDEX, /* IMX_PADMUX_SD3_DATA2_INDEX */ + IMX_PADCTL_SD3_DATA3_INDEX, /* IMX_PADMUX_SD3_DATA3_INDEX */ + IMX_PADCTL_SD3_RESET_INDEX, /* IMX_PADMUX_SD3_RESET_INDEX */ + IMX_PADCTL_NAND_CLE_INDEX, /* IMX_PADMUX_NAND_CLE_INDEX */ + IMX_PADCTL_NAND_ALE_INDEX, /* IMX_PADMUX_NAND_ALE_INDEX */ + IMX_PADCTL_NAND_WP_INDEX, /* IMX_PADMUX_NAND_WP_INDEX */ + IMX_PADCTL_NAND_READY_INDEX, /* IMX_PADMUX_NAND_READY_INDEX */ + IMX_PADCTL_NAND_CS0_INDEX, /* IMX_PADMUX_NAND_CS0_INDEX */ + IMX_PADCTL_NAND_CS1_INDEX, /* IMX_PADMUX_NAND_CS1_INDEX */ + IMX_PADCTL_NAND_CS2_INDEX, /* IMX_PADMUX_NAND_CS2_INDEX */ + IMX_PADCTL_NAND_CS3_INDEX, /* IMX_PADMUX_NAND_CS3_INDEX */ + IMX_PADCTL_SD4_CMD_INDEX, /* IMX_PADMUX_SD4_CMD_INDEX */ + IMX_PADCTL_SD4_CLK_INDEX, /* IMX_PADMUX_SD4_CLK_INDEX */ + IMX_PADCTL_NAND_DATA00_INDEX, /* IMX_PADMUX_NAND_DATA00_INDEX */ + IMX_PADCTL_NAND_DATA01_INDEX, /* IMX_PADMUX_NAND_DATA01_INDEX */ + IMX_PADCTL_NAND_DATA02_INDEX, /* IMX_PADMUX_NAND_DATA02_INDEX */ + IMX_PADCTL_NAND_DATA03_INDEX, /* IMX_PADMUX_NAND_DATA03_INDEX */ + IMX_PADCTL_NAND_DATA04_INDEX, /* IMX_PADMUX_NAND_DATA04_INDEX */ + IMX_PADCTL_NAND_DATA05_INDEX, /* IMX_PADMUX_NAND_DATA05_INDEX */ + IMX_PADCTL_NAND_DATA06_INDEX, /* IMX_PADMUX_NAND_DATA06_INDEX */ + IMX_PADCTL_NAND_DATA07_INDEX, /* IMX_PADMUX_NAND_DATA07_INDEX */ + IMX_PADCTL_SD4_DATA0_INDEX, /* IMX_PADMUX_SD4_DATA0_INDEX */ + IMX_PADCTL_SD4_DATA1_INDEX, /* IMX_PADMUX_SD4_DATA1_INDEX */ + IMX_PADCTL_SD4_DATA2_INDEX, /* IMX_PADMUX_SD4_DATA2_INDEX */ + IMX_PADCTL_SD4_DATA3_INDEX, /* IMX_PADMUX_SD4_DATA3_INDEX */ + IMX_PADCTL_SD4_DATA4_INDEX, /* IMX_PADMUX_SD4_DATA4_INDEX */ + IMX_PADCTL_SD4_DATA5_INDEX, /* IMX_PADMUX_SD4_DATA5_INDEX */ + IMX_PADCTL_SD4_DATA6_INDEX, /* IMX_PADMUX_SD4_DATA6_INDEX */ + IMX_PADCTL_SD4_DATA7_INDEX, /* IMX_PADMUX_SD4_DATA7_INDEX */ + IMX_PADCTL_SD1_DATA1_INDEX, /* IMX_PADMUX_SD1_DATA1_INDEX */ + IMX_PADCTL_SD1_DATA0_INDEX, /* IMX_PADMUX_SD1_DATA0_INDEX */ + IMX_PADCTL_SD1_DATA3_INDEX, /* IMX_PADMUX_SD1_DATA3_INDEX */ + IMX_PADCTL_SD1_CMD_INDEX, /* IMX_PADMUX_SD1_CMD_INDEX */ + IMX_PADCTL_SD1_DATA2_INDEX, /* IMX_PADMUX_SD1_DATA2_INDEX */ + IMX_PADCTL_SD1_CLK_INDEX, /* IMX_PADMUX_SD1_CLK_INDEX */ + IMX_PADCTL_SD2_CLK_INDEX, /* IMX_PADMUX_SD2_CLK_INDEX */ + IMX_PADCTL_SD2_CMD_INDEX, /* IMX_PADMUX_SD2_CMD_INDEX */ + IMX_PADCTL_SD2_DATA3_INDEX, /* IMX_PADMUX_SD2_DATA3_INDEX */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_padmux_map + * + * Description: + * This function map a Pad Mux register index to the corresponding Pad + * Control register index. + * + ****************************************************************************/ + +unsigned int imx_padmux_map(unsigned int padmux) +{ + DEBUGASSERT(padmx < IMX_PADMUX_NREGISTERS); + return (unsigned int)g_mux2ctl_map[padmux]; +} + +/**************************************************************************** + * Name: imx_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + ****************************************************************************/ + +int imx_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset) +{ +#warning Missing logic + return -ENOSYS; +} diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h index 402657c63d..06a256b095 100644 --- a/arch/arm/src/imx6/imx_iomuxc.h +++ b/arch/arm/src/imx6/imx_iomuxc.h @@ -42,6 +42,8 @@ #include +#include + #include "chip/imx_iomuxc.h" /**************************************************************************** @@ -52,16 +54,34 @@ * Public Types ****************************************************************************/ -/**************************************************************************** - * Inline Functions - ****************************************************************************/ + /* The smallest integer type that can hold the IOMUX encoding */ -/**************************************************************************** - * Public Data - ****************************************************************************/ +typedef uint16_t iomux_pinset_t; /**************************************************************************** * Public Function Prototypes ****************************************************************************/ + +/**************************************************************************** + * Name: imx_padmux_map + * + * Description: + * This function map a Pad Mux register index to the corresponding Pad + * Control register index. + * + ****************************************************************************/ + +unsigned int imx_padmux_map(unsigned int padmux); + +/**************************************************************************** + * Name: imx_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + ****************************************************************************/ + +int imx_iomux_configure(uintptr_t padctl, iomux_pinset_t ioset); #endif /* __ARCH_ARM_SRC_IMX6_IMX_IOMUXC_H */ diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index d49a9bc833..54ab9ad967 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -124,7 +124,7 @@ void up_irqinitialize(void) */ #ifdef CONFIG_IMX6_PIO_IRQ - imx_pioirq_initialize(); + imx_gpioirq_initialize(); #endif /* And finally, enable interrupts */