Add beginning of ethernet register definitions for the STM32 F4
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4145 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -79,7 +79,7 @@
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# define STM32_NADC 1 /* ADC1 */
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -106,7 +106,7 @@
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# define STM32_NADC 2 /* ADC1-2 */
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# define STM32_NETHERNET 0 /* No ethernet */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -133,7 +133,7 @@
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# define STM32_NADC 2 /* ADC1-2*/
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 0 /* No random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -162,7 +162,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No Ethernet MAC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -191,7 +191,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No Ethernet MAC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -220,7 +220,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No Ethernet MAC */
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# define STM32_NETHERNET 0 /* No Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
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@ -249,7 +249,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -278,7 +278,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -307,7 +307,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -336,7 +336,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -365,7 +365,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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@ -394,7 +394,7 @@
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# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
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# define STM32_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
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# define STM32_NRNG 1 /* Random number generator (RNG) */
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# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
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333
arch/arm/src/stm32/chip/stm32_eth.h
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333
arch/arm/src/stm32/chip/stm32_eth.h
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@ -0,0 +1,333 @@
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32_eth.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if STM32_NETHERNET > 1
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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/* MAC Registers */
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#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */
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#define STM32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */
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#define STM32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */
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#define STM32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */
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#define STM32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */
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#define STM32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */
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#define STM32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */
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#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */
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#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */
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#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */
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#define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */
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#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */
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#define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */
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#define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */
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#define STM32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */
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#define STM32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */
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#define STM32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */
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#define STM32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */
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#define STM32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */
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#define STM32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */
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#define STM32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */
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/* MMC Registers */
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#define STM32_ETH_MMCC_OFFSET 0x0100 /* Ethernet MMC control register */
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#define STM32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */
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#define STM32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */
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#define STM32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */
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#define STM32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */
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#define STM32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */
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#define STM32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */
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#define STM32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */
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#define STM32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */
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#define STM32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */
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#define STM32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */
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/* IEEE 1588 time stamp registers */
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#define STM32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */
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#define STM32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */
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#define STM32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */
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#define STM32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */
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#define STM32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */
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#define STM32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */
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#define STM32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */
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#define STM32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */
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#define STM32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */
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#define STM32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */
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/* DMA Registers */
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#define STM32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */
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#define STM32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */
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#define STM32_ETH_DMARPDR_OFFSET 0x1008 /* EHERNET DMA receive poll demand register */
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#define STM32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */
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#define STM32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */
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#define STM32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */
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#define STM32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */
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#define STM32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */
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#define STM32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */
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#define STM32_ETH_DMARSWTR_OFFSET 0x1024 /* Ethernet DMA receive status watchdog timer register */
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#define STM32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */
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#define STM32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */
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#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */
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#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */
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/* Register Base Addresses **************************************************************************/
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/* MAC Registers */
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#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET)
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#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET)
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#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET)
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#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET)
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#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET)
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#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET)
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#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET)
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#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET)
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#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET)
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#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET)
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#define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET)
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#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET)
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#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET)
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#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET)
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#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET)
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#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET)
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#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET)
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#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET)
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#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET)
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#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET)
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#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET)
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/* MMC Registers */
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#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCC_OFFSET)
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#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET)
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#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET)
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#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET)
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#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET)
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#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET)
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#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET)
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#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET)
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#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET)
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#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET)
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#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET)
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/* IEEE 1588 time stamp registers */
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#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET)
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#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET)
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#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET)
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#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET)
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#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET)
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#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET)
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#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET)
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#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET)
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#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET)
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#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET)
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/* DMA Registers */
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#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET)
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#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET)
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#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET)
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#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET)
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#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET)
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#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET)
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#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET)
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#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET)
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#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET)
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#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET)
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#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET)
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#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET)
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#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET)
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#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET)
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/* Register Bit-Field Definitions *******************************************************************/
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/* MAC Registers */
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/* Ethernet MAC configuration register */
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#define ETH_MACCR_
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/* Ethernet MAC frame filter register */
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#define ETH_MACFFR_
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/* Ethernet MAC hash table high register */
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#define ETH_MACHTHR_
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/* Ethernet MAC hash table low register */
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#define ETH_MACHTLR_
|
||||
/* Ethernet MAC MII address register */
|
||||
#define ETH_MACMIIAR_
|
||||
/* Ethernet MAC MII data register */
|
||||
#define ETH_MACMIIDR_
|
||||
/* Ethernet MAC flow control register */
|
||||
#define ETH_MACFCR_
|
||||
/* Ethernet MAC VLAN tag register */
|
||||
#define ETH_MACVLANTR_
|
||||
/* Ethernet MAC remote wakeup frame filter reg */
|
||||
#define ETH_MACRWUFFR_
|
||||
/* Ethernet MAC PMT control and status register */
|
||||
#define ETH_MACPMTCSR_
|
||||
/* Ethernet MAC debug register */
|
||||
#define ETH_MACDBGR_
|
||||
/* Ethernet MAC interrupt status register */
|
||||
#define ETH_MACSR_
|
||||
/* Ethernet MAC interrupt mask register */
|
||||
#define ETH_MACIMR_
|
||||
/* Ethernet MAC address 0 high register */
|
||||
#define ETH_MACA0HR_
|
||||
/* Ethernet MAC address 0 low register */
|
||||
#define ETH_MACA0LR_
|
||||
/* Ethernet MAC address 1 high register */
|
||||
#define ETH_MACA1HR_
|
||||
/* Ethernet MAC address1 low register */
|
||||
#define ETH_MACA1LR_
|
||||
/* Ethernet MAC address 2 high register */
|
||||
#define ETH_MACA2HR_
|
||||
/* Ethernet MAC address 2 low register */
|
||||
#define ETH_MACA2LR_
|
||||
/* Ethernet MAC address 3 high register */
|
||||
#define ETH_MACA3HR_
|
||||
/* Ethernet MAC address 3 low register */
|
||||
#define ETH_MACA3LR_
|
||||
|
||||
/* MMC Registers */
|
||||
|
||||
/* Ethernet MMC control register */
|
||||
#define ETH_MMCC_
|
||||
/* Ethernet MMC receive interrupt register */
|
||||
#define ETH_MMCRIR_
|
||||
/* Ethernet MMC transmit interrupt register */
|
||||
#define ETH_MMCTIR_
|
||||
/* Ethernet MMC receive interrupt mask register */
|
||||
#define ETH_MMCRIMR_
|
||||
/* Ethernet MMC transmit interrupt mask register */
|
||||
#define ETH_MMCTIMR_
|
||||
/* Ethernet MMC transmitted good frames counter register (single collision) */
|
||||
#define ETH_MMCTGFSCCR_
|
||||
/* Ethernet MMC transmitted good frames counter register (multiple-collision) */
|
||||
#define ETH_MMCTGFMSCCR_
|
||||
/* Ethernet MMC transmitted good frames counter register */
|
||||
#define ETH_MMCTGFCR_
|
||||
/* Ethernet MMC received frames with CRC error counter register */
|
||||
#define ETH_MMCRFCECR_
|
||||
/* Ethernet MMC received frames with alignment error counter */
|
||||
#define ETH_MMCRFAECR_
|
||||
/* MMC received good unicast frames counter register */
|
||||
#define ETH_MMCRGUFCR_
|
||||
|
||||
/* IEEE 1588 time stamp registers */
|
||||
|
||||
/* Ethernet PTP time stamp control register */
|
||||
#define ETH_PTPTSCR_
|
||||
/* Ethernet PTP subsecond increment register */
|
||||
#define ETH_PTPSSIR_
|
||||
/* Ethernet PTP time stamp high register */
|
||||
#define ETH_PTPTSHR_
|
||||
/* Ethernet PTP time stamp low register */
|
||||
#define ETH_PTPTSLR_
|
||||
/* Ethernet PTP time stamp high update register */
|
||||
#define ETH_PTPTSHUR_
|
||||
/* Ethernet PTP time stamp low update register */
|
||||
#define ETH_PTPTSLUR_
|
||||
/* Ethernet PTP time stamp addend register */
|
||||
#define ETH_PTPTSAR_
|
||||
/* Ethernet PTP target time high register */
|
||||
#define ETH_PTPTTHR_
|
||||
/* Ethernet PTP target time low register */
|
||||
#define ETH_PTPTTLR_
|
||||
/* Ethernet PTP time stamp status register */
|
||||
#define ETH_PTPTSSR_
|
||||
|
||||
/* DMA Registers */
|
||||
|
||||
/* Ethernet DMA bus mode register */
|
||||
#define ETH_DMABMR_
|
||||
/* Ethernet DMA transmit poll demand register */
|
||||
#define ETH_DMATPDR_
|
||||
/* EHERNET DMA receive poll demand register */
|
||||
#define ETH_DMARPDR_
|
||||
/* Ethernet DMA receive descriptor list address register */
|
||||
#define ETH_DMARDLAR_
|
||||
/* Ethernet DMA transmit descriptor list address register */
|
||||
#define ETH_DMATDLAR_
|
||||
/* Ethernet DMA status register */
|
||||
#define ETH_DMASR_
|
||||
/* Ethernet DMA operation mode register */
|
||||
#define ETH_DMAOMR_
|
||||
/* Ethernet DMA interrupt enable register */
|
||||
#define ETH_DMAIER_
|
||||
/* Ethernet DMA missed frame and buffer overflow counter register */
|
||||
#define ETH_DMAMFBOC_
|
||||
/* Ethernet DMA receive status watchdog timer register */
|
||||
#define ETH_DMARSWTR_
|
||||
/* Ethernet DMA current host transmit descriptor register */
|
||||
#define ETH_DMACHTDR_
|
||||
/* Ethernet DMA current host receive descriptor register */
|
||||
#define ETH_DMACHRDR_
|
||||
/* Ethernet DMA current host transmit buffer address register */
|
||||
#define ETH_DMACHTBAR_
|
||||
/* Ethernet DMA current host receive buffer address register */
|
||||
#define ETH_DMACHRBAR_
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* STM32_NETHERNET > 1 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */
|
||||
|
||||
@ -169,7 +169,7 @@
|
||||
#define STM32_BKPSRAM_BASE 0x40024000 /* 0x40024000-0x40024fff: Backup SRAM (BKPSRAM) */
|
||||
#define STM32_DMA1_BASE 0x40026000 /* 0x40026000-0x400263ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40026400 /* 0x40026400-0x400267ff: DMA2 */
|
||||
#define STM32_ETHERNET_BASE 0x40029000 /* 0x40028000-0x400283ff: Ethernet MAC */
|
||||
#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000-0x400283ff: Ethernet MAC */
|
||||
/* 0x40028400-0x400287ff: Ethernet MAC */
|
||||
/* 0x40028800-0x40028bff: Ethernet MAC */
|
||||
/* 0x40028c00-0x40028fff: Ethernet MAC */
|
||||
|
||||
@ -44,6 +44,10 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if STM32_NETHERNET > 1
|
||||
|
||||
#include "chip/stm32_eth.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
@ -77,9 +81,7 @@ extern "C" {
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if STM32_NTHERNET > 1
|
||||
EXTERN int stm32_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
@ -87,5 +89,6 @@ EXTERN int stm32_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* STM32_NETHERNET > 1 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user