arch/z80/src/z180: Fix nxstyle errors
error: Long line found
This commit is contained in:
simbit18
Alin Jerpelea
parent
3403b983ec
commit
2b51111030
@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/z80/src/z180/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@ -16,23 +16,23 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_CHIP_H
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#define __ARCH_Z80_SRC_Z180_CHIP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <arch/z180/chip.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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****************************************************************************/
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#endif /* __ARCH_Z80_SRC_Z180_CHIP_H */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/z80/src/z180/switch.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@ -16,14 +16,14 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_SWITCH_H
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#define __ARCH_Z80_SRC_Z180_SWITCH_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/sched.h>
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@ -33,14 +33,14 @@
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#include "z180_iomap.h"
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#include "z80_internal.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Macros for portability ***********************************************************
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/* Macros for portability ***************************************************
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*
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* Common logic in arch/z80/src/common is customized for the z180 context switching
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* logic via the following macros.
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* Common logic in arch/z80/src/common is customized for
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* the z180 context switching logic via the following macros.
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*/
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/* Initialize the IRQ state */
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@ -48,34 +48,36 @@
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#define INIT_IRQCONTEXT() \
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g_current_regs = NULL
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/* IN_INTERRUPT returns true if the system is currently operating in the interrupt
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* context. IN_INTERRUPT is the inline equivalent of up_interrupt_context().
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/* IN_INTERRUPT returns true if the system is currently operating
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* in the interrupt context. IN_INTERRUPT is the inline equivalent
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* of up_interrupt_context().
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*/
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#define IN_INTERRUPT() \
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(g_current_regs != NULL)
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/* The following macro declares the variables need by IRQ_ENTER and IRQ_LEAVE.
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* These variables are used to support nested interrupts.
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/* The following macro declares the variables need by IRQ_ENTER
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* and IRQ_LEAVE. These variables are used to support nested interrupts.
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*
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* - savestate holds the previous value of current_state.
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* - savecpr holds the previous value of current_cpr.
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*
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* NOTE: Nested interrupts are not supported in this implementation. If you want
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* to implement nested interrupts, you would have to change the way that
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* g_current_regs/cbr is handled. The savestate/savecbr variables would not work
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* for that purpose as implemented here because only the outermost nested
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* interrupt can result in a context switch (they can probably be deleted).
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* NOTE: Nested interrupts are not supported in this implementation.
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* If you want to implement nested interrupts, you would have to change
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* the way that g_current_regs/cbr is handled. The savestate/savecbr
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* variables would not work for that purpose as implemented here because
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* only the outermost nested interrupt can result in a context switch
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* (they can probably be deleted).
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*/
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#define DECL_SAVESTATE() \
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FAR chipreg_t *savestate; \
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uint8_t savecbr;
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/* The following macro is used when the system enters interrupt handling logic.
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* The entry values of g_current_regs and current_cbr and stored in local variables.
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* Then g_current_regs and current_cbr are set to the values of the interrupted
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* task.
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/* The following macro is used when the system enters interrupt
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* handling logic. The entry values of g_current_regs and current_cbr
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* and stored in local variables. Then g_current_regs and current_cbr
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* are set to the values of the interrupted task.
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*/
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#define IRQ_ENTER(irq, regs) \
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@ -88,9 +90,10 @@
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} \
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while (0)
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/* The following macro is used when the system exits interrupt handling logic.
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* The value of g_current_regs is restored. If we are not processing a nested
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* interrupt (meaning that we going to return to the user task), then also
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/* The following macro is used when the system exits interrupt
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* handling logic. The value of g_current_regs is restored.
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* If we are not processing a nested interrupt (meaning
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* that we going to return to the user task), then also
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* set the MMU's CBR register.
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*/
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@ -109,7 +112,9 @@
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} \
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while (0)
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/* The following macro is used to sample the interrupt state (as a opaque handle) */
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/* The following macro is used to sample the interrupt state
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* (as a opaque handle)
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*/
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#define IRQ_STATE() \
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(g_current_regs)
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@ -132,8 +137,9 @@
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} \
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while (0)
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/* Save the user context in the specified TCB. User context saves can be simpler
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* because only those registers normally saved in a C called need be stored.
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/* Save the user context in the specified TCB. User context saves can be
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* simpler because only those registers normally saved in a C called
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* need be stored.
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*/
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#define SAVE_USERCONTEXT(tcb) \
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@ -154,33 +160,33 @@
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} \
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while (0)
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This holds a references to the current interrupt level register storage structure.
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* If is non-NULL only during interrupt processing.
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/* This holds a references to the current interrupt level register
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* storage structure. If is non-NULL only during interrupt processing.
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*/
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extern volatile chipreg_t *g_current_regs;
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/* This holds the value of the MMU's CBR register. This value is set to the
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* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR if
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* an interrupt level context switch occurs, and restored on interrupt exit. In
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* this way, the CBR is always correct on interrupt exit.
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* interrupted tasks's CBR on interrupt entry, changed to the new task's CBR
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* if an interrupt level context switch occurs, and restored on interrupt
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* exit. In this way, the CBR is always correct on interrupt exit.
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*/
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extern uint8_t current_cbr;
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#endif
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/************************************************************************************
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/****************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/z80/src/z180/z180_config.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@ -16,14 +16,14 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_Z180_CONFIG_H
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#define __ARCH_Z80_SRC_Z180_Z180_CONFIG_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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@ -31,9 +31,9 @@
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#include "z80_internal.h"
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Verify that selected features match the capability of the selected CPU */
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@ -71,8 +71,8 @@
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# define HAVE_SERIAL 1
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#endif
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/* Make sure all features are disabled for disabled UARTs/[E]SCC channels. This
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* simplifies checking later.
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/* Make sure all features are disabled for disabled UARTs/[E]SCC channels.
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* This simplifies checking later.
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*/
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#ifndef CONFIG_Z180_UART0
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@ -204,16 +204,16 @@
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#endif
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Functions Prototypes
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************************************************************************************/
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****************************************************************************/
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#endif /* __ARCH_Z80_SRC_Z180_Z180_CONFIG_H */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/z80/src/z180/z180_iomap.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@ -16,22 +16,22 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
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#define __ARCH_Z80_SRC_Z180_Z180_IOMAP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <arch/z180/chip.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Configuration ********************************************************************/
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/* Configuration ************************************************************/
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/* These registers may be relocated to multiples of 0x40 by setting the IO
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* Control Register (ICR). Relocatable to 0x40-0x7f, or 0x80-0xbf. The
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@ -45,7 +45,7 @@
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# define SFR_OFFSET 0
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#endif
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/* Z180 Register Bit addresses ******************************************************/
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/* Z180 Register Bit addresses **********************************************/
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/* ASCI Registers */
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@ -291,9 +291,9 @@
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#define Z18X_SCC_WR14 0x0e /* Miscellaneous control bits */
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#define Z18X_SCC_WR15 0x0f /* External status interrupt enable control */
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/* Z180 Register Bit definitions ****************************************************/
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/* Z180 Register Bit definitions ********************************************/
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/* ASCI Registers *******************************************************************/
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/* ASCI Registers ***********************************************************/
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/* ASCI Control Register A 0 (CNTLA0: 0x00) */
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@ -389,7 +389,7 @@
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* (Z8S180/L180-Class Processors Only) -- 8-bit data
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*/
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/* CSI/O Registers ******************************************************************/
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/* CSI/O Registers **********************************************************/
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/* CSI/O Control/Status Register (CNTR: 0x0a) */
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@ -411,7 +411,7 @@
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/* CSI/O Transmit/Receive Register (TRDR: 0x0b) -- 8-bit data */
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/* Timer Registers ******************************************************************/
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/* Timer Registers **********************************************************/
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/* Timer Data Register 0L (TMDR0L: 0x0c) -- 8-bit data */
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@ -442,7 +442,7 @@
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/* Free Running counter (FRC: 0x18) -- 8-bit data */
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/* DMA Registers ********************************************************************/
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/* DMA Registers ************************************************************/
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/* DMA Destination Address Register Channel 0
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* (DAR0 I/O Address 0x23 to 0x25) -- 8-bit data
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@ -527,7 +527,7 @@
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# define DCNTL_DIM_IO2MI (2 << DCNTL_DIM_SHIFT) /* I/O to memory, increment MARI */
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# define DCNTL_DIM_IO2MD (3 << DCNTL_DIM_SHIFT) /* I/O to memory, decrement MARI */
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/* System Control Registers *********************************************************/
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/* System Control Registers *************************************************/
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/* Clock Multiplier Register (CMR: 0x1e)
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* (Z8S180/L180-Class Processors Only)
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@ -577,7 +577,9 @@
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# define RCR_CYC0 (1 << RCR_CYC_SHIFT)
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# define RCR_CYC1 (2 << RCR_CYC_SHIFT)
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/* MMU Common Base Register (CBR: 0x38) - 8-bit base address of Common Area 1 */
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/* MMU Common Base Register (CBR: 0x38)
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* - 8-bit base address of Common Area 1
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*/
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/* MMU Bank Base Register (BBR: 0x39) - 8-bit address of Bank area */
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@ -602,7 +604,7 @@
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# define ICR_IOA7 (2 << ICR_IOA_SHIFT)
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#define ICR_IOSTP (0x20) /* Bit 5: Enable I/O stop mode */
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/* Registers unique to Z8x181 class CPUs ********************************************/
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/* Registers unique to Z8x181 class CPUs ************************************/
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#ifdef HAVE_Z8X181
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/* PIA Registers */
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@ -653,7 +655,7 @@
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#endif
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/* Registers unique to Z8x182 class CPUs ********************************************/
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/* Registers unique to Z8x182 class CPUs ************************************/
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#ifdef HAVE_Z8X182
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/* PIA Registers */
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@ -681,7 +683,7 @@
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#endif
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/* [E]SCC Internal Register Definitions *********************************************/
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/* [E]SCC Internal Register Definitions *************************************/
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/* Read Registers */
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@ -707,7 +709,9 @@
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#define RR0_RES2 (0x02) /* Bit 1: Residue Code 2 */
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#define RR0_ALL (0x01) /* Bit 0: All Sent */
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/* RR2: Interrupt vector (modified if VIS Bit in WR9 is set) -- 8-bit vector value */
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/* RR2: Interrupt vector (modified if VIS Bit in WR9 is set)
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* -- 8-bit vector value
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*/
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/* RR3: Interrupt pending bits */
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/z80/src/z180/z80_mem.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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@ -16,43 +16,44 @@
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_Z80_SRC_Z180_Z80_MEM_H
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#define __ARCH_Z80_SRC_Z180_Z80_MEM_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Locate the IDLE thread stack at the end of RAM. */
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#define CONFIG_STACK_END CONFIG_RAM_SIZE
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#define CONFIG_STACK_BASE (CONFIG_STACK_END - CONFIG_IDLETHREAD_STACKSIZE)
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/* The heap then extends from the linker determined beginning of the heap (s__HEAP).
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* to the bottom of the IDLE thread stack. NOTE: The symbol s__HEAP is not
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* accessible from C because it does not begin with the _ character. g_heapbase
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* is defined in z180_head.asm to provide that value to the C code.
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/* The heap then extends from the linker determined beginning of the
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* heap (s__HEAP). to the bottom of the IDLE thread stack.
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* NOTE: The symbol s__HEAP is not accessible from C because
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* it does not begin with the _ character. g_heapbase is defined
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* in z180_head.asm to provide that value to the C code.
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*/
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#define CONFIG_HEAP1_END CONFIG_STACK_BASE
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#define CONFIG_HEAP1_BASE g_heapbase
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/************************************************************************************
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/****************************************************************************
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* Public variables
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************************************************************************************/
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****************************************************************************/
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/* This is the bottom of the heap as provided by the linker symbol s__HEAP. NOTE:
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* The symbol s__HEAP is not accessible from C because it does not begin with the _
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* character. g_heapbase is defined in z180_head.asm to provide that value to the C
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* code.
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/* This is the bottom of the heap as provided by the linker symbol s__HEAP.
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* NOTE: The symbol s__HEAP is not accessible from C because
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* it does not begin with the _ character. g_heapbase is defined
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* in z180_head.asm to provide that value to the C code.
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*/
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extern const uint16_t g_heapbase;
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