From 2b8cd243648151bb4df0176761dfad7a52788b6a Mon Sep 17 00:00:00 2001 From: Dave Marples Date: Fri, 8 Nov 2019 09:49:41 -0600 Subject: [PATCH] arch/arm/src/armv7-m/nvic.h: Add BPIALL register address. --- arch/arm/src/armv7-m/nvic.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h index cd81f171fc..ced0a4ff7f 100644 --- a/arch/arm/src/armv7-m/nvic.h +++ b/arch/arm/src/armv7-m/nvic.h @@ -247,6 +247,7 @@ #define NVIC_DCCSW_OFFSET 0x0f6c /* D-Cache Clean by Set-way (Cortex-M7) */ #define NVIC_DCCIMVAC_OFFSET 0x0f70 /* D-Cache Clean and Invalidate by MVA to PoC (Cortex-M7) */ #define NVIC_DCCISW_OFFSET 0x0f74 /* D-Cache Clean and Invalidate by Set-way (Cortex-M7) */ +#define NVIC_BPIALL_OFFSET 0x0f78 /* Branch predictor invalidate all (Cortex-M7) */ #define NVIC_ITCMCR_OFFSET 0x0f90 /* Instruction Tightly-Coupled Memory Control Register */ #define NVIC_DTCMCR_OFFSET 0x0f94 /* Data Tightly-Coupled Memory Control Registers */ #define NVIC_AHBPCR_OFFSET 0x0f98 /* AHBP Control Register */ @@ -436,6 +437,7 @@ #define NVIC_DCCSW (ARMV7M_NVIC_BASE + NVIC_DCCSW_OFFSET) #define NVIC_DCCIMVAC (ARMV7M_NVIC_BASE + NVIC_DCCIMVAC_OFFSET) #define NVIC_DCCISW (ARMV7M_NVIC_BASE + NVIC_DCCISW_OFFSET) +#define NVIC_BPIALL (ARMV7M_NVIC_BASE + NVIC_BPIALL_OFFSET) #define NVIC_ITCMCR (ARMV7M_NVIC_BASE + NVIC_ITCMCR_OFFSET) #define NVIC_DTCMCR (ARMV7M_NVIC_BASE + NVIC_DTCMCR_OFFSET) #define NVIC_AHBPCR (ARMV7M_NVIC_BASE + NVIC_AHBPCR_OFFSET)