More changes from Uros
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3426 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
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commit
2bcb84af12
@ -33,14 +33,13 @@
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*
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************************************************************************************/
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/** \file
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* \author Gregory Nutt <spudmonkey@racsa.co.cr>
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* \brief Chip Definition provides over-all memory Map, and pin mapping
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**/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_H
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#define __ARCH_ARM_SRC_STM32_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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@ -76,7 +75,7 @@
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# define STM32_NDAC 0 /* No DAC */
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# define STM32_NCRC 0 /* No CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# include "stm32f103ze_pinmap.h"
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# include "chip/stm32f103ze_pinmap.h"
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#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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@ -97,7 +96,7 @@
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 0 /* No ethernet */
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# include "stm32f103re_pinmap.h"
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# include "chip/stm32f103re_pinmap.h"
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#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
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# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
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@ -118,7 +117,7 @@
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# define STM32_NDAC 2 /* DAC1-2 */
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# define STM32_NCRC 1 /* CRC */
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# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
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# include "stm32f107vc_pinmap.h"
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# include "chip/stm32f107vc_pinmap.h"
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#else
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# error "Unsupported STM32 chip"
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@ -128,6 +127,7 @@
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* Other chip hardware files should then include this file for the proper setup
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*/
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#include "stm32_memorymap.h"
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#include "chip/stm32_memorymap.h"
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */
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351
arch/arm/src/stm32/chip/stm32_dma.h
Normal file
351
arch/arm/src/stm32/chip/stm32_dma.h
Normal file
@ -0,0 +1,351 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_dma.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 7 DMA Channels */
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#define DMA1 0
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#define DMA2 1
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#define DMA3 2
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#define DMA4 3
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#define DMA5 4
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#define DMA6 5
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#define DMA7 6
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/* Register Offsets *****************************************************************/
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
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#define STM32_DMACHAN_CCR_OFFSET 0x0008
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c
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#define STM32_DMACHAN_CPAR_OFFSET 0x0010
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#define STM32_DMACHAN_CMAR_OFFSET 0x0014
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#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
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#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
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#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
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#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
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#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
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#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
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#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
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#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
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#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
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#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
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#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
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#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
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#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
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#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
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#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
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#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
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#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
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#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
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#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
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#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
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#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
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#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
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#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
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#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
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#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
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#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
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#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
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/* Register Addresses ***************************************************************/
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#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
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#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
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#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
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#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
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#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
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#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
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#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
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#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
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#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
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#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
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#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
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#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
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#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
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#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
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#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
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#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
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#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
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#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
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#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
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#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
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#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
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#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
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#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
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#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
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#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
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#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
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#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
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#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
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#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
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#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
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#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
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#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
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#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
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#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
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#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
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#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
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#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
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#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
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#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
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#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
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#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
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#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
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#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
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#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
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#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
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#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
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#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
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#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
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#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
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#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
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#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
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#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
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#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
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#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
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#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
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#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
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#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
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#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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#define DMA_CHAN_SHIFT(n) ((n) << 2)
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#define DMA_CHAN_MASK 0x0f
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#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
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#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
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#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
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#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
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/* DMA interrupt status register */
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#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
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#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
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#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
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#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
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#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
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#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
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#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
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#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
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#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
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#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
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#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
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#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
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#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
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#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
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#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
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#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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/* DMA interrupt flag clear register */
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#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
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#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
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#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
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#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
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#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
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#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
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#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
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#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
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#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
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#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
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#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
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#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
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#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
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#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
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#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
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#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
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#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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/* DMA channel configuration register */
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#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
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#define DMA_CCR_PL_SHIFT (12) /* Bits 13-12: Channel Priority level */
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#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
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# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
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# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
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# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
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# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 11-10: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 9-8: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given channel can be enabled at once.
|
||||
*/
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (1)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||
#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
|
||||
#define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
|
||||
#define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
|
||||
#define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
|
||||
#define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
|
||||
#define DMACHAN_UART4_RX STM32_DMA2_CHAN3
|
||||
#define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
|
||||
#define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
|
||||
#define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
|
||||
#define DMACHAN_SDIO STM32_DMA2_CHAN4
|
||||
#define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
|
||||
#define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
|
||||
#define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
|
||||
#define DMACHAN_ADC3 STM32_DMA2_CHAN5
|
||||
#define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
||||
#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
|
||||
#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_gpio.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -36,9 +36,8 @@
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions (Hardware Register Descriptions)
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_NGPIO_PORTS ((STM32_NGPIO + 15) >> 4)
|
||||
@ -362,3 +361,4 @@
|
||||
#define AFIO_EXTICR4_EXTI15_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H */
|
||||
|
||||
|
||||
173
arch/arm/src/stm32/chip/stm32_i2c.h
Normal file
173
arch/arm/src/stm32/chip/stm32_i2c.h
Normal file
@ -0,0 +1,173 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_i2c.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */
|
||||
#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */
|
||||
#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
|
||||
#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
|
||||
#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable*/
|
||||
#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */
|
||||
#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */
|
||||
#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */
|
||||
#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */
|
||||
#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */
|
||||
#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */
|
||||
#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */
|
||||
#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */
|
||||
#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
|
||||
#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */
|
||||
#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */
|
||||
#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
|
||||
#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
|
||||
#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
|
||||
#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */
|
||||
#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
|
||||
#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
|
||||
#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
|
||||
|
||||
/* Own address register 1 */
|
||||
|
||||
#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */
|
||||
#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */
|
||||
#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT)
|
||||
#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/
|
||||
#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT)
|
||||
#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */
|
||||
#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
|
||||
|
||||
/* Own address register 2 */
|
||||
|
||||
#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */
|
||||
#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */
|
||||
#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT)
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */
|
||||
#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT)
|
||||
|
||||
/* Status register 1 */
|
||||
|
||||
#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */
|
||||
#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
|
||||
#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
|
||||
#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
|
||||
#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
|
||||
#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
|
||||
#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
|
||||
#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */
|
||||
#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
|
||||
#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
|
||||
#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
|
||||
#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
|
||||
#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
|
||||
|
||||
/* Status register 2 */
|
||||
|
||||
#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
|
||||
#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */
|
||||
#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */
|
||||
#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */
|
||||
#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */
|
||||
#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */
|
||||
#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */
|
||||
#define I2C_SR2_PEC_SHIFT (1) /* Bits 15-8: Packet Error Checking Register */
|
||||
#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT)
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
|
||||
#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT)
|
||||
#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
|
||||
#define I2C_CCR_FS (1 << 15) /* Bit 15: I2C Master Mode Selection */
|
||||
|
||||
/* TRISE Register */
|
||||
|
||||
#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
|
||||
#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H */
|
||||
|
||||
136
arch/arm/src/stm32/chip/stm32_memorymap.h
Normal file
136
arch/arm/src/stm32/chip/stm32_memorymap.h
Normal file
@ -0,0 +1,136 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* FLASH and SRAM *******************************************************************/
|
||||
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000 - Up to 512Kb */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 64Kb SRAM */
|
||||
#define STM32_SRAMBB_BASE 0x22000000
|
||||
#define STM32_PERIPH_BASE 0x40000000
|
||||
|
||||
/* Register Base Address ************************************************************/
|
||||
|
||||
/* APB1 bus */
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000 - 0x400003ff: TIM2 timer */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400 - 0x400007ff: TIM3 timer */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800 - 0x40000bff: TIM4 timer */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00 - 0x40000fff: TIM5 timer */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000 - 0x400013ff: TIM6 timer */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400 - 0x400007ff: TIM7 timer */
|
||||
/* 0x40001800 - 0x40000fff: Reserved */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800 - 0x40002bff: RTC */
|
||||
#define STM32_WWDG_BASE 0x40002C00 /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
|
||||
/* 0x40003400 - 0x400037ff: Reserved */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800 - 0x40003bff: SPI2/I22 */
|
||||
#define STM32_I2S2_BASE 0x40003800
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00 - 0x40003fff: SPI3/I23 */
|
||||
#define STM32_I2S3_BASE 0x40003c00
|
||||
/* 0x40004000 - 0x400043ff: Reserved */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400 - 0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800 - 0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00 - 0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000 - 0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400 - 0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800 - 0x40005Bff: I2C2 */
|
||||
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00 - 0x40005fff: USB device FS registers */
|
||||
#define STM32_USBCANRAM_BASE 0x40006000 /* 0x40006000 - 0x400063ff: Shared USB/CAN SRAM 512 bytes */
|
||||
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400 - 0x400067ff: bxCAN1 */
|
||||
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800 - 0x40006bff: bxCAN2 */
|
||||
#define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */
|
||||
/* 0x40007800 - 0x4000ffff: Reserved */
|
||||
|
||||
/* APB2 bus */
|
||||
|
||||
#define STM32_AFIO_BASE 0x40010000 /* 0x40010000 - 0x400103ff: AFIO */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400 - 0x400107ff: EXTI */
|
||||
#define STM32_GPIOA_BASE 0x40010800 /* 0x40010800 - 0x40010bff: GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0X40010c00 /* 0X40010c00 - 0x40010fff: GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x40011000 /* 0x40011000 - 0x400113ff: GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0x40011400 /* 0x40011400 - 0x400117ff: GPIO Port D */
|
||||
#define STM32_GPIOE_BASE 0x40011800 /* 0x40011800 - 0x40011bff: GPIO Port E */
|
||||
#define STM32_GPIOF_BASE 0x40011c00 /* 0x4001c000 - 0x400111ff: GPIO Port F */
|
||||
#define STM32_GPIOG_BASE 0x40012000 /* 0x40012000 - 0x400123ff: GPIO Port G */
|
||||
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400 - 0x400127ff: ADC1 */
|
||||
#define STM32_ADC2_BASE 0x40012800 /* 0x40012800 - 0x40012bff: ADC2 */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00 - 0x40012fff: TIM1 timer */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000 - 0x400133ff: SPI1 */
|
||||
#define STM32_TIM8_BASE 0x40013400 /* 0x40013400 - 0x400137ff: TIM8 timer */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800 - 0x40013bff: USART1 */
|
||||
#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013fff: ADC3 */
|
||||
/* 0x40014000 - 0x40017fff: Reserved */
|
||||
/* AHB bus */
|
||||
|
||||
#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */
|
||||
/* 0x40018400 - 0x40017fff: Reserved */
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */
|
||||
/* 0x40020800 - 0x40020fff: Reserved */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
|
||||
/* 0x40021400 - 0x40021fff: Reserved */
|
||||
#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */
|
||||
#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: RC */
|
||||
/* 0x40023400 - 0x40027fff: Reserved */
|
||||
#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
|
||||
/* 0x40030000 - 0x4fffffff: Reserved */
|
||||
|
||||
/* Peripheral BB base */
|
||||
|
||||
#define STM32_PERIPHBB_BASE 0x42000000
|
||||
|
||||
/* Flexible SRAM controller (FSMC) */
|
||||
|
||||
#define STM32_FSMC_BASE 0xa0000000
|
||||
|
||||
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
|
||||
* address range
|
||||
*/
|
||||
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H */
|
||||
|
||||
297
arch/arm/src/stm32/chip/stm32_rcc.h
Normal file
297
arch/arm/src/stm32/chip/stm32_rcc.h
Normal file
@ -0,0 +1,297 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_rcc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RRC_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RRC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */
|
||||
#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */
|
||||
#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */
|
||||
#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT)
|
||||
#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */
|
||||
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_ADCPRE_SHIFT (14) /* Bits 15-14: ADC prescaler */
|
||||
#define RCC_CFGR_ADCPRE_MASK (3 << RCC_CFGR_ADCPRE_SHIFT)
|
||||
# define RCC_CFGR_PLCK2d2 (0 << RCC_CFGR_ADCPRE_SHIFT) /* 00: PLCK2 divided by 2 */
|
||||
# define RCC_CFGR_PLCK2d4 (1 << RCC_CFGR_ADCPRE_SHIFT) /* 01: PLCK2 divided by 4 */
|
||||
# define RCC_CFGR_PLCK2d6 (2 << RCC_CFGR_ADCPRE_SHIFT) /* 10: PLCK2 divided by 6 */
|
||||
# define RCC_CFGR_PLCK2d8 (3 << RCC_CFGR_ADCPRE_SHIFT) /* 11: PLCK2 divided by 8 */
|
||||
#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */
|
||||
#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */
|
||||
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */
|
||||
#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT)
|
||||
# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
|
||||
#define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB prescaler */
|
||||
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 26-24: Microcontroller Clock Output */
|
||||
#define RCC_CFGR_MCO_MASK (7 << RCC_CFGR_MCO_SHIFT)
|
||||
# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0xx: No clock */
|
||||
# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock selected */
|
||||
# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: Internal 8 MHz RC oscillator clock selected */
|
||||
# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 110: External 1-25 MHz oscillator clock selected */
|
||||
# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
|
||||
|
||||
/* Clock interrupt register */
|
||||
|
||||
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */
|
||||
#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */
|
||||
#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */
|
||||
#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */
|
||||
#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
|
||||
#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_AFIORST (1 << 0) /* Bit 0: Alternate Function I/O reset */
|
||||
#define RCC_APB2RSTR_IOPARST (1 << 2) /* Bit 2: I/O port A reset */
|
||||
#define RCC_APB2RSTR_IOPBRST (1 << 3) /* Bit 3: IO port B reset */
|
||||
#define RCC_APB2RSTR_IOPCRST (1 << 4) /* Bit 4: IO port C reset */
|
||||
#define RCC_APB2RSTR_IOPDRST (1 << 5) /* Bit 5: IO port D reset */
|
||||
#define RCC_APB2RSTR_IOPERST (1 << 6) /* Bit 6: IO port E reset */
|
||||
#define TCC_APB2RSTR_IOPFRST (1 << 7) /* Bit 7: IO port F reset */
|
||||
#define TCC_APB2RSTR_IOPGRST (1 << 8) /* Bit 8: IO port G reset */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC 1 interface reset */
|
||||
#define RCC_APB2RSTR_ADC2RST (1 << 10) /* Bit 10: ADC 2 interface reset */
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 Timer reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 Timer reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
#define RCC_APB2RTST_ADC2RST (1 << 15) /* Bit 15: ADC3 interface reset */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: Timer 4 reset */
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: Timer 5 reset */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window Watchdog reset */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 18: UART 5 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
|
||||
#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */
|
||||
#define RCC_APB1RSTR_BKPRST (1 << 27) /* Bit 27: Backup interface reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
|
||||
|
||||
/* AHB Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA1 clock enable */
|
||||
#define RCC_AHBENR_DMA2EN (1 << 1) /* Bit 1: DMA2 clock enable */
|
||||
#define RCC_AHBENR_SRAMEN (1 << 2) /* Bit 2: SRAM interface clock enable */
|
||||
#define RCC_AHBENR_FLITFEN (1 << 4) /* Bit 4: FLITF clock enable */
|
||||
#define RCC_AHBENR_CRCEN (1 << 6) /* Bit 6: CRC clock enable */
|
||||
#define RCC_AHBENR_FSMCEN (1 << 8) /* Bit 8: FSMC clock enable */
|
||||
#define RCC_AHBENR_SDIOEN (1 << 10) /* Bit 10: SDIO clock enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN (1 << 0) /* Bit 0: Alternate Function I/O clock enable */
|
||||
#define RCC_APB2ENR_IOPEN(n) (1 << ((n)+2))
|
||||
#define RCC_APB2ENR_IOPAEN (1 << 2) /* Bit 2: I/O port A clock enable */
|
||||
#define RCC_APB2ENR_IOPBEN (1 << 3) /* Bit 3: I/O port B clock enable */
|
||||
#define RCC_APB2ENR_IOPCEN (1 << 4) /* Bit 4: I/O port C clock enable */
|
||||
#define RCC_APB2ENR_IOPDEN (1 << 5) /* Bit 5: I/O port D clock enable */
|
||||
#define RCC_APB2ENR_IOPEEN (1 << 6) /* Bit 6: I/O port E clock enable */
|
||||
#define RCC_APB2ENR_IOPFEN (1 << 7) /* Bit 7: I/O port F clock enable */
|
||||
#define RCC_APB2ENR_IOPGEN (1 << 8) /* Bit 8: I/O port G clock enable */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 9) /* Bit 9: ADC 1 interface clock enable */
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 10) /* Bit 10: ADC 2 interface clock enable */
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 Timer clock enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 Timer clock enable */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 15) /* Bit 14: ADC3 interface clock enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: Timer 4 clock enable */
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: Timer 5 clock enable */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window Watchdog clock enable */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
|
||||
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
|
||||
#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */
|
||||
#define RCC_APB1ENR_BKPEN (1 << 27) /* Bit 27: Backup interface clock enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
|
||||
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RRC_H */
|
||||
|
||||
291
arch/arm/src/stm32/chip/stm32_sdio.h
Normal file
291
arch/arm/src/stm32/chip/stm32_sdio.h
Normal file
@ -0,0 +1,291 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_sdio.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */
|
||||
#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */
|
||||
#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */
|
||||
#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */
|
||||
#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */
|
||||
#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n))
|
||||
#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */
|
||||
#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */
|
||||
#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */
|
||||
#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */
|
||||
#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */
|
||||
#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */
|
||||
#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */
|
||||
#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */
|
||||
#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */
|
||||
#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */
|
||||
#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */
|
||||
#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */
|
||||
#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET)
|
||||
#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET)
|
||||
#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET)
|
||||
#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET)
|
||||
#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET)
|
||||
#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n))
|
||||
#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET)
|
||||
#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET)
|
||||
#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET)
|
||||
#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET)
|
||||
#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET)
|
||||
#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET)
|
||||
#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET)
|
||||
#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET)
|
||||
#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET)
|
||||
#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET)
|
||||
#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET)
|
||||
#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET)
|
||||
#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET)
|
||||
|
||||
/* Bit-band (BB) base addresses ****************************************************/
|
||||
|
||||
#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE)
|
||||
|
||||
#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5))
|
||||
#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5))
|
||||
#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5))
|
||||
#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5))
|
||||
#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5))
|
||||
#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5))
|
||||
#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5))
|
||||
#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5))
|
||||
#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5))
|
||||
#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5))
|
||||
#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5))
|
||||
#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5))
|
||||
#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5))
|
||||
#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5))
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
|
||||
#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT)
|
||||
# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
|
||||
# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
|
||||
# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
|
||||
|
||||
#define SDIO_POWER_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
|
||||
#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
|
||||
#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
|
||||
#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
|
||||
#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
|
||||
#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT)
|
||||
# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */
|
||||
# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */
|
||||
# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */
|
||||
#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
|
||||
#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
|
||||
|
||||
#define SDIO_CLKCR_RESET (0) /* Reset value */
|
||||
#define SDIO_ARG_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4))
|
||||
#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4))
|
||||
#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4))
|
||||
#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4))
|
||||
#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4))
|
||||
|
||||
#define SDIO_CMD_CMDINDEX_SHIFT (0)
|
||||
#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
|
||||
#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
|
||||
#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT)
|
||||
# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
|
||||
# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
|
||||
# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
|
||||
#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
|
||||
#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
|
||||
#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
|
||||
#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
|
||||
#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
|
||||
#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
|
||||
#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
|
||||
|
||||
#define SDIO_CMD_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4))
|
||||
#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4))
|
||||
#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4))
|
||||
#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4))
|
||||
#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4))
|
||||
#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4))
|
||||
#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4))
|
||||
|
||||
#define SDIO_RESPCMD_SHIFT (0)
|
||||
#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT)
|
||||
|
||||
#define SDIO_DTIMER_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DLEN_SHIFT (0)
|
||||
#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT)
|
||||
|
||||
#define SDIO_DLEN_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
|
||||
#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
|
||||
#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
|
||||
#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
|
||||
#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
|
||||
#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
|
||||
#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
|
||||
#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
|
||||
#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
|
||||
|
||||
#define SDIO_DCTRL_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4))
|
||||
#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4))
|
||||
#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4))
|
||||
#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4))
|
||||
#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4))
|
||||
#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4))
|
||||
#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4))
|
||||
#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4))
|
||||
|
||||
#define SDIO_DATACOUNT_SHIFT (0)
|
||||
#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT)
|
||||
|
||||
#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
|
||||
#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
|
||||
#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
|
||||
#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
|
||||
#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
|
||||
#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
|
||||
#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
|
||||
#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
|
||||
#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
|
||||
#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
|
||||
#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
|
||||
|
||||
#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
|
||||
#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
|
||||
#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
|
||||
|
||||
#define SDIO_ICR_RESET 0x00c007ff
|
||||
#define SDIO_ICR_STATICFLAGS 0x000005ff
|
||||
|
||||
#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
|
||||
#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
|
||||
#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
|
||||
#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
|
||||
#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
|
||||
#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
|
||||
#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
|
||||
|
||||
#define SDIO_MASK_RESET (0)
|
||||
|
||||
#define SDIO_FIFOCNT_SHIFT (0)
|
||||
#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H */
|
||||
|
||||
134
arch/arm/src/stm32/chip/stm32_spi.h
Normal file
134
arch/arm/src/stm32/chip/stm32_spi.h
Normal file
@ -0,0 +1,134 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_spi.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H
|
||||
#define __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_SPI_CLK_MAX 18000000UL /* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H */
|
||||
|
||||
852
arch/arm/src/stm32/chip/stm32_tim.h
Normal file
852
arch/arm/src/stm32/chip/stm32_tim.h
Normal file
@ -0,0 +1,852 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_tim.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
|
||||
/* General Timers - TIM2, TIM3, TIM4, and TIM5 */
|
||||
|
||||
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
|
||||
#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit) */
|
||||
#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 *(16-bit) */
|
||||
#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit) */
|
||||
#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#if STM32_NATIM > 0
|
||||
# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
|
||||
# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NATIM > 1
|
||||
# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
|
||||
# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* General Timers - TIM2, TIM3, TIM4, and TIM5 */
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#if STM32_NBTIM > 0
|
||||
# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
|
||||
# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NBTIM > 1
|
||||
# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
|
||||
# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
|
||||
#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */
|
||||
#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
|
||||
#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */
|
||||
#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */
|
||||
#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT)
|
||||
# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
|
||||
# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
|
||||
# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
|
||||
# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
|
||||
#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
|
||||
#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */
|
||||
#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT)
|
||||
# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
|
||||
# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
|
||||
# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */
|
||||
#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */
|
||||
#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */
|
||||
#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT)
|
||||
# define ATIM_CR2_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
|
||||
# define ATIM_CR2_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
|
||||
# define ATIM_CR2_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
|
||||
# define ATIM_CR2_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
|
||||
#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
|
||||
#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
|
||||
#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
|
||||
#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
|
||||
#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
|
||||
#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
|
||||
#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
|
||||
#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
|
||||
|
||||
/* Slave mode control register */
|
||||
|
||||
#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
|
||||
#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
|
||||
#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External trigger prescaler */
|
||||
#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT)
|
||||
# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
|
||||
# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
|
||||
# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
|
||||
# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
|
||||
#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External trigger filter */
|
||||
#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT)
|
||||
# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
|
||||
# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
|
||||
#define ATIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger selection */
|
||||
#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT)
|
||||
# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
|
||||
# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
|
||||
# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
|
||||
# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
|
||||
# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
|
||||
# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
|
||||
# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
|
||||
# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
|
||||
#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 2:0: Slave mode selection */
|
||||
#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT)
|
||||
# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
|
||||
# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
|
||||
# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
|
||||
# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
|
||||
# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
|
||||
# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
|
||||
# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
|
||||
# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
|
||||
#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
|
||||
#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
|
||||
#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
|
||||
#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */
|
||||
#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
|
||||
#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */
|
||||
#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
|
||||
#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
|
||||
#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
|
||||
#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
|
||||
#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */
|
||||
#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
|
||||
#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
|
||||
#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
|
||||
#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
|
||||
#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
|
||||
#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
|
||||
#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
|
||||
#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */
|
||||
#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
|
||||
#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
|
||||
#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
|
||||
#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */
|
||||
#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
|
||||
#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */
|
||||
#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */
|
||||
#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */
|
||||
#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */
|
||||
#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */
|
||||
#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */
|
||||
|
||||
/* Capture/compare mode register 1 -- Output compare mode */
|
||||
|
||||
#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
|
||||
#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
|
||||
#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
|
||||
#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
|
||||
#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
|
||||
#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */
|
||||
#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
|
||||
#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
|
||||
#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
|
||||
#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
|
||||
|
||||
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
|
||||
#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
|
||||
#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
|
||||
#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
|
||||
|
||||
/* Common CCMR (unshifted) Compare Mode bit field definitions */
|
||||
|
||||
#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
|
||||
#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
|
||||
#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
|
||||
#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
|
||||
#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
|
||||
#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
|
||||
#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
|
||||
#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
|
||||
|
||||
/* Capture/compare mode register 1 -- Input capture mode */
|
||||
|
||||
/* Bits 1-0:(same as output compare mode) */
|
||||
#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
|
||||
#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
|
||||
#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
/* Bits 9:8 (same as output compare mode) */
|
||||
#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */
|
||||
#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
|
||||
#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
|
||||
#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
|
||||
/* Capture/compare mode register 2 - Output Compare mode */
|
||||
|
||||
#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
|
||||
#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
|
||||
#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
|
||||
#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
|
||||
#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
|
||||
#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
|
||||
#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
|
||||
#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
|
||||
#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
|
||||
#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
|
||||
|
||||
/* Capture/compare mode register 2 - Input Capture Mode */
|
||||
|
||||
/* Bits 1-0:(same as output compare mode) */
|
||||
#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
|
||||
#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
|
||||
#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
/* Bits 9:8 (same as output compare mode) */
|
||||
#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */
|
||||
#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
|
||||
#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
|
||||
/* Capture/compare enable register */
|
||||
|
||||
#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
|
||||
#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
|
||||
#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */
|
||||
#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
|
||||
#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
|
||||
#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */
|
||||
#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
|
||||
#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
|
||||
#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
|
||||
#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
|
||||
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
|
||||
|
||||
/* Repetition counter register */
|
||||
|
||||
#define ATIM_RCR_REP_SHIFT (0) /* Bits 7-0: Repetition Counter Value */
|
||||
#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
|
||||
|
||||
/* Break and dead-time register */
|
||||
|
||||
#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
|
||||
#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT)
|
||||
#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
|
||||
#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT)
|
||||
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
|
||||
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
|
||||
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
|
||||
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
|
||||
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
|
||||
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
|
||||
#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
|
||||
#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
|
||||
#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
|
||||
#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
|
||||
|
||||
/* DMA control register */
|
||||
|
||||
#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
|
||||
#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT)
|
||||
#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
|
||||
#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
|
||||
#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
|
||||
#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */
|
||||
#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction */
|
||||
#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection */
|
||||
#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT)
|
||||
# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */
|
||||
# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
|
||||
# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
|
||||
# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
|
||||
#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
|
||||
#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */
|
||||
#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT)
|
||||
# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
|
||||
# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
|
||||
# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection. */
|
||||
#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT)
|
||||
# define GTIM_CR2_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
|
||||
# define GTIM_CR2_ENAB (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
|
||||
# define GTIM_CR2_UPDT (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
|
||||
# define GTIM_CR2_CMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
|
||||
# define GTIM_CR2_CMP1 (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP2 (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP3 (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP4 (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO) */
|
||||
#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
|
||||
|
||||
/* Slave mode control register */
|
||||
|
||||
#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */
|
||||
#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT)
|
||||
# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
|
||||
# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
|
||||
# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
|
||||
# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
|
||||
# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
|
||||
# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
|
||||
# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
|
||||
# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
|
||||
#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */
|
||||
#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT)
|
||||
# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
|
||||
# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
|
||||
# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
|
||||
# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
|
||||
# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
|
||||
# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
|
||||
# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
|
||||
# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
|
||||
#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */
|
||||
#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter */
|
||||
#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT)
|
||||
# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
|
||||
# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler */
|
||||
#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT)
|
||||
# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
|
||||
# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
|
||||
# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
|
||||
# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
|
||||
#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */
|
||||
#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
|
||||
#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
|
||||
#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
|
||||
#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
|
||||
#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
|
||||
#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
|
||||
#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
|
||||
#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
|
||||
#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
|
||||
#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
|
||||
#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt Flag */
|
||||
#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
|
||||
#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
|
||||
#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
|
||||
#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
|
||||
#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
|
||||
#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
|
||||
#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
|
||||
#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
|
||||
#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */
|
||||
#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation */
|
||||
#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation */
|
||||
#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation */
|
||||
#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation */
|
||||
|
||||
/* Capture/compare mode register 1 - Output compare mode */
|
||||
|
||||
#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
|
||||
#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions below) */
|
||||
#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
|
||||
#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
|
||||
#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
|
||||
#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions below) */
|
||||
#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
|
||||
#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */
|
||||
#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions below) */
|
||||
#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
|
||||
#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
|
||||
#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
|
||||
#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions below) */
|
||||
#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
|
||||
|
||||
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
|
||||
#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
|
||||
#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
|
||||
#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
|
||||
|
||||
/* Common CCMR (unshifted) Compare Mode bit field definitions */
|
||||
|
||||
#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
|
||||
#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
|
||||
#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
|
||||
#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
|
||||
#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
|
||||
#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
|
||||
#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
|
||||
#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
|
||||
|
||||
/* Capture/compare mode register 1 - Input capture mode */
|
||||
|
||||
/* Bits 1-0 (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
|
||||
#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
|
||||
#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
/* Bits 9-8: (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */
|
||||
#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
|
||||
#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
|
||||
#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
|
||||
/* Capture/compare mode register 2 - Output Compare mode */
|
||||
|
||||
#define GTIM_CCMR1_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
|
||||
#define GTIM_CCMR1_CC3S_MASK (3 << GTIM_CCMR1_CC3S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions above) */
|
||||
#define GTIM_CCMR1_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
|
||||
#define GTIM_CCMR1_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
|
||||
#define GTIM_CCMR1_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
|
||||
#define GTIM_CCMR1_OC3M_MASK (7 << GTIM_CCMR1_OC3M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions above) */
|
||||
#define GTIM_CCMR1_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
|
||||
#define GTIM_CCMR1_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
|
||||
#define GTIM_CCMR1_CC4S_MASK (3 << GTIM_CCMR1_CC4S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions above) */
|
||||
#define GTIM_CCMR1_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
|
||||
#define GTIM_CCMR1_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
|
||||
#define GTIM_CCMR1_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
|
||||
#define GTIM_CCMR1_OC4M_MASK (7 << GTIM_CCMR1_OC4M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions above) */
|
||||
#define GTIM_CCMR1_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
|
||||
|
||||
/* Capture/compare mode register 2 - Input capture mode */
|
||||
|
||||
/* Bits 1-0 (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
|
||||
#define GTIM_CCMR1_IC3PSC_MASK (3 << GTIM_CCMR1_IC3PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
|
||||
#define GTIM_CCMR1_IC3F_MASK (0x0f << GTIM_CCMR1_IC3F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
/* Bits 9-8: (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */
|
||||
#define GTIM_CCMR1_IC4PSC_MASK (3 << GTIM_CCMR1_IC4PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
|
||||
#define GTIM_CCMR1_IC4F_MASK (0x0f << GTIM_CCMR1_IC4F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
|
||||
/* Capture/compare enable register */
|
||||
|
||||
#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
|
||||
#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
|
||||
#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
|
||||
#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
|
||||
#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
|
||||
#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
|
||||
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
|
||||
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
|
||||
|
||||
/* DMA control register */
|
||||
|
||||
#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
|
||||
#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT)
|
||||
#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
|
||||
#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
|
||||
#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
|
||||
#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */
|
||||
#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT)
|
||||
# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
|
||||
# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
|
||||
# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H */
|
||||
|
||||
226
arch/arm/src/stm32/chip/stm32_usbdev.h
Normal file
226
arch/arm/src/stm32/chip/stm32_usbdev.h
Normal file
@ -0,0 +1,226 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32_usbdev.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
|
||||
#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
|
||||
#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n))
|
||||
#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET)
|
||||
#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET)
|
||||
#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET)
|
||||
#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET)
|
||||
#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET)
|
||||
#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET)
|
||||
#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET)
|
||||
#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET)
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET)
|
||||
#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET)
|
||||
#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET)
|
||||
#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET)
|
||||
#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET)
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBCANRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* USB endpoint register */
|
||||
|
||||
#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */
|
||||
#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT)
|
||||
#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */
|
||||
#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT)
|
||||
# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */
|
||||
# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */
|
||||
# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */
|
||||
# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */
|
||||
# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */
|
||||
# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */
|
||||
#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */
|
||||
#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */
|
||||
#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */
|
||||
#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */
|
||||
#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT)
|
||||
# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */
|
||||
# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */
|
||||
# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */
|
||||
# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */
|
||||
#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */
|
||||
#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */
|
||||
#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT)
|
||||
# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */
|
||||
# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */
|
||||
# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */
|
||||
# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */
|
||||
# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
|
||||
# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
|
||||
#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */
|
||||
|
||||
/* USB control register */
|
||||
|
||||
#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */
|
||||
#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */
|
||||
#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */
|
||||
#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
|
||||
#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
|
||||
#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */
|
||||
#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */
|
||||
#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
|
||||
#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
|
||||
#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
|
||||
#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
|
||||
#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
|
||||
#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
|
||||
|
||||
#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\
|
||||
USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM)
|
||||
|
||||
/* USB interrupt status register */
|
||||
|
||||
#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */
|
||||
#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
|
||||
#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
|
||||
#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
|
||||
#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
|
||||
#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
|
||||
#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
|
||||
#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
|
||||
#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
|
||||
#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
|
||||
#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
|
||||
|
||||
#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\
|
||||
USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR)
|
||||
|
||||
/* USB frame number register */
|
||||
|
||||
#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */
|
||||
#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT)
|
||||
#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */
|
||||
#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT)
|
||||
#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */
|
||||
#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */
|
||||
#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */
|
||||
|
||||
/* USB device address */
|
||||
|
||||
#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */
|
||||
#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT)
|
||||
#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */
|
||||
|
||||
/* Buffer table address */
|
||||
|
||||
#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */
|
||||
#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT)
|
||||
|
||||
/* Transmission buffer address */
|
||||
|
||||
#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */
|
||||
#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */
|
||||
#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT)
|
||||
|
||||
/* Transmission byte count */
|
||||
|
||||
#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */
|
||||
#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
|
||||
|
||||
/* Reception buffer address */
|
||||
|
||||
#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */
|
||||
#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
|
||||
#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT)
|
||||
|
||||
/* Reception byte count */
|
||||
|
||||
#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */
|
||||
#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */
|
||||
#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
|
||||
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
|
||||
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H */
|
||||
|
||||
334
arch/arm/src/stm32/chip/stm32f103re_pinmap.h
Normal file
334
arch/arm/src/stm32/chip/stm32f103re_pinmap.h
Normal file
@ -0,0 +1,334 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f103re_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Uros Platise <uros.platise@isotel.eu>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103RE_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103RE_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* TIMERS */
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM4_REMAP)
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#else
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#endif
|
||||
|
||||
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#define GPIO_TIM8_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_TIM8_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_TIM8_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_TIM8_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TIM8_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM8_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
/* USART */
|
||||
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART2_REMAP)
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
/* SPI */
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
/* CAN */
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
|
||||
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
|
||||
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
|
||||
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103RE_PINMAP_H */
|
||||
496
arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
Normal file
496
arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
Normal file
@ -0,0 +1,496 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103ZE_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103ZE_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions: */
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM4_REMAP)
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#else
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#endif
|
||||
|
||||
#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART2_REMAP)
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
|
||||
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
/* FSMC: CF */
|
||||
|
||||
#define GPIO_CF_A0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_CF_A1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_CF_A2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_CF_A3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_CF_A4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_CF_A5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_CF_A6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_CF_A7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_CF_A8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_CF_A9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_CF_A10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_CF_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_CF_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_CF_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_CF_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_CF_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_CF_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_CF_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_CF_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_CF_D8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_CF_D9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_CF_D10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_CF_D11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_CF_D12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_CF_D13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_CF_D14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_CF_D15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_CF_NIORD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_CF_NREG (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_CF_NIOWR (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_CF_CD (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_CF_INTR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_CF_NIOS16 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_CF_NOE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_CF_NWE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_CF_NWAIT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_CF_NCE41 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_CF_NCE42 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
|
||||
/* FSMC: CF/IDE */
|
||||
|
||||
#define GPIO_CFIDE_A0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_CFIDE_A1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_CFIDE_A2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_CFIDE_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_CFIDE_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_CFIDE_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_CFIDE_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_CFIDE_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_CFIDE_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_CFIDE_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_CFIDE_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_CFIDE_D8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_CFIDE_D9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_CFIDE_D10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_CFIDE_D11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_CFIDE_D12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_CFIDE_D13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_CFIDE_D14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_CFIDE_D15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_CFIDE_NIORD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN6)
|
||||
#define GPIO_CFIDE_NREG (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN7)
|
||||
#define GPIO_CFIDE_NIOWR (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN8)
|
||||
#define GPIO_CFIDE_CD (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
|
||||
#define GPIO_CFIDE_INTR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
|
||||
#define GPIO_CFIDE_NIOS16 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_CFIDE_NOE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_CFIDE_NWE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_CFIDE_NWAIT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_CFIDE_NCE41 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_CFIDE_NCE42 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN11)
|
||||
|
||||
/* SDIO */
|
||||
|
||||
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
|
||||
#ifndef CONFIG_SDIO_WIDTH_D1_ONLY
|
||||
# define GPIO_SDIO_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SDIO_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SDIO_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_SDIO_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_SDIO_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_SDIO_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
/* FSMC: NOR/PSRAM/SRAM (NPS) */
|
||||
|
||||
#define GPIO_NPS_A0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_NPS_A1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_NPS_A2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_NPS_A3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_NPS_A4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_NPS_A5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_NPS_A6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_NPS_A7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_NPS_A8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_NPS_A9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_NPS_A10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_NPS_A11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_NPS_A12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_NPS_A13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_NPS_A14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_NPS_A15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_NPS_A16 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_NPS_A17 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_NPS_A18 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_NPS_A19 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_NPS_A20 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_NPS_A21 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_NPS_A22 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_NPS_A23 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_NPS_A24 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_NPS_A25 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_NPS_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_NPS_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_NPS_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_NPS_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_NPS_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_NPS_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_NPS_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_NPS_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_NPS_D8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_NPS_D9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_NPS_D10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_NPS_D11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_NPS_D12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_NPS_D13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_NPS_D14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_NPS_D15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_NPS_CLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_NPS_NOE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_NPS_NWE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_NPS_NWAIT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_NPS_NE1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_NPS_NE2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_NPS_NE3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_NPS_NE4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_NPS_NBL0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_NPS_NBL1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
|
||||
/* FSMC: NOR/PSRAM Multiplex (NPM) */
|
||||
|
||||
#define GPIO_NPM_A16 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_NPM_A17 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_NPM_A18 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_NPM_A19 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_NPM_A20 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_NPM_A21 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_NPM_A22 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_NPM_A23 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_NPM_DA0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_NPM_DA1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_NPM_DA2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_NPM_DA3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_NPM_DA4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_NPM_DA5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_NPM_DA6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_NPM_DA7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_NPM_DA8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_NPM_DA9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_NPM_DA10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_NPM_DA11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_NPM_DA12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_NPM_DA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_NPM_DA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_NPM_DA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_NPM_CLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_NPM_NOE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_NPM_NWE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_NPM_NWAIT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_NPM_NE1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_NPM_NE2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_NPM_NE3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_NPM_NE4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_NPM_A24 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_NPM_A25 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_NPM_NBL0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_NPM_NBL1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
|
||||
/* FSMC: NAND */
|
||||
|
||||
#define GPIO_NAND_D4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_NAND_D5 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_NAND_D6 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_NAND_D7 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_NAND_D8 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_NAND_D9 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_NAND_D10 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_NAND_D11 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_NAND_D12 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_NAND_D13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_NAND_D14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_NAND_D15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_NAND_CLE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_NAND_ALE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_NAND_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_NAND_D1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_NAND_INT2 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_NAND_INT3 (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_NAND_D2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_NAND_D3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_NAND_NOE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_NAND_NWE (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_NAND_NWAIT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_NAND_NCE2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_NAND_NCE3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103ZE_PINMAP_H */
|
||||
|
||||
416
arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
Normal file
416
arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
Normal file
@ -0,0 +1,416 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F107VC_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F107VC_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions: */
|
||||
|
||||
#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
|
||||
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_ETH_REMAP)
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#else
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_OTG_FSDM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTG_FSDP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTG_FSID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTG_FSSOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTG_FSVBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#if defined(CONFIG_STM32_TIM4_REMAP)
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#else
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#endif
|
||||
#define GPIO_TIM4_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH4IN (GGPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TRACECK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#if defined(CONFIG_STM32_TRACESWO_REMAP)
|
||||
# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPU|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART2_REMAP)
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
|
||||
/* Some GPIOs are accessible only as remapped, alternate functions */
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F107VC_PINMAP_H */
|
||||
@ -36,6 +36,35 @@
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Additional Configuration *********************************************************/
|
||||
|
||||
#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE)
|
||||
# undef CONFIG_DEBUG_DMA
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
/* Peripherals **********************************************************************/
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_adc.h"
|
||||
#include "stm32_bkp.h"
|
||||
@ -56,10 +85,8 @@
|
||||
#include "stm32_uart.h"
|
||||
#include "stm32_usbdev.h"
|
||||
#include "stm32_wdg.h"
|
||||
|
||||
/* TODO: Inconsistency! Code uses GPIO macros from this file instead from gpio.h!
|
||||
* _internal also includes pinmap.h file.
|
||||
*/
|
||||
#include "stm32_internal.h"
|
||||
#include "stm32_lowputc.h"
|
||||
#include "stm32_eth.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_H */
|
||||
|
||||
|
||||
@ -50,281 +50,281 @@
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
|
||||
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
|
||||
#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */
|
||||
#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */
|
||||
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
|
||||
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
|
||||
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
|
||||
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
|
||||
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
|
||||
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
|
||||
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
|
||||
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
|
||||
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
|
||||
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
|
||||
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
|
||||
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
|
||||
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
|
||||
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NADC > 0
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC1_HTR (STM32_ADC1_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC1_LTR (STM32_ADC1_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NADC > 1
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
# define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET)
|
||||
# define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET)
|
||||
# define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET)
|
||||
# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET)
|
||||
# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE+STM32_ADC_JOFR1_OFFSET)
|
||||
# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE+STM32_ADC_JOFR2_OFFSET)
|
||||
# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE+STM32_ADC_JOFR3_OFFSET)
|
||||
# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE+STM32_ADC_JOFR4_OFFSET)
|
||||
# define STM32_ADC2_HTR (STM32_ADC2_BASE+STM32_ADC_HTR_OFFSET)
|
||||
# define STM32_ADC2_LTR (STM32_ADC2_BASE+STM32_ADC_LTR_OFFSET)
|
||||
# define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET)
|
||||
# define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET)
|
||||
# define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET)
|
||||
# define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET)
|
||||
# define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET)
|
||||
# define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET)
|
||||
# define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET)
|
||||
# define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET)
|
||||
# define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* ADC status register */
|
||||
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */
|
||||
#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */
|
||||
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
|
||||
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
|
||||
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
|
||||
|
||||
/* ADC control register 1 */
|
||||
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT)
|
||||
# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */
|
||||
# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */
|
||||
# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */
|
||||
# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */
|
||||
# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */
|
||||
# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */
|
||||
# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */
|
||||
# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */
|
||||
#define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */
|
||||
#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT)
|
||||
#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */
|
||||
#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */
|
||||
#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */
|
||||
#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */
|
||||
#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */
|
||||
#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */
|
||||
#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */
|
||||
#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */
|
||||
#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT)
|
||||
#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */
|
||||
#define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT)
|
||||
# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */
|
||||
# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */
|
||||
# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */
|
||||
# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */
|
||||
# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */
|
||||
# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */
|
||||
# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */
|
||||
# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */
|
||||
# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */
|
||||
# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */
|
||||
#define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */
|
||||
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
|
||||
|
||||
/* ADC control register 2 */
|
||||
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
|
||||
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 14-12: External event select for injected group */
|
||||
#define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_T1TRG0 (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
|
||||
# define ADC_CR2_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
|
||||
# define ADC_CR2_T2TRG0 (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
|
||||
# define ADC_CR2_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_T4TRG0 (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */
|
||||
# define ADC_CR2_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
|
||||
#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
|
||||
#define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */
|
||||
#define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
|
||||
# define ADC_CR2_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_T3TRG0 (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */
|
||||
# define ADC_CR2_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
|
||||
#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
|
||||
#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */
|
||||
#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */
|
||||
#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */
|
||||
#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */
|
||||
#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */
|
||||
#define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
|
||||
#define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */
|
||||
#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */
|
||||
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
|
||||
#define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 14-12: External event select for injected group */
|
||||
#define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
|
||||
# define ADC_CR2_JEXTSEL_T1TRG0 (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T2TRG0 (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */
|
||||
# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */
|
||||
# define ADC_CR2_JEXTSEL_T4TRG0 (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */
|
||||
# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line15 */
|
||||
# define ADC_CR2_JEXTSEL_SWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */
|
||||
#define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */
|
||||
#define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */
|
||||
#define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT)
|
||||
# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */
|
||||
# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */
|
||||
# define ADC_CR2_EXTSEL_T3TRG0 (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */
|
||||
# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */
|
||||
# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line11 */
|
||||
# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */
|
||||
#define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */
|
||||
#define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */
|
||||
#define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */
|
||||
#define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */
|
||||
|
||||
/* ADC sample time register 1 */
|
||||
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 2-0: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 5-3: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 8-6: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 11-9: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 14-12: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 17-15: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 20-18: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 23-21: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 2-0: Channel 10 Sample time selection */
|
||||
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
|
||||
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 5-3: Channel 11 Sample time selection */
|
||||
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
|
||||
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 8-6: Channel 12 Sample time selection */
|
||||
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
|
||||
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 11-9: Channel 13 Sample time selection */
|
||||
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
|
||||
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 14-12: Channel 14 Sample time selection */
|
||||
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
|
||||
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 17-15: Channel 15 Sample time selection */
|
||||
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
|
||||
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 20-18: Channel 16 Sample time selection */
|
||||
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
|
||||
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 23-21: Channel 17 Sample time selection */
|
||||
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
|
||||
|
||||
#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
|
||||
#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
|
||||
#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
|
||||
#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
|
||||
#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
|
||||
#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
|
||||
#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
|
||||
#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */
|
||||
#define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */
|
||||
#define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */
|
||||
#define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */
|
||||
#define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */
|
||||
#define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */
|
||||
#define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */
|
||||
#define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */
|
||||
|
||||
/* ADC sample time register 2 */
|
||||
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR1_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT)
|
||||
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
|
||||
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR1_SMP0_SHIFT)
|
||||
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
|
||||
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT)
|
||||
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
|
||||
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT)
|
||||
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
|
||||
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT)
|
||||
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
|
||||
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT)
|
||||
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
|
||||
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT)
|
||||
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
|
||||
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT)
|
||||
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
|
||||
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT)
|
||||
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
|
||||
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT)
|
||||
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
|
||||
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT)
|
||||
|
||||
/* ADC injected channel data offset register 1-4 */
|
||||
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */
|
||||
#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT)
|
||||
|
||||
/* ADC watchdog high threshold register */
|
||||
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */
|
||||
#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT)
|
||||
|
||||
/* ADC watchdog low threshold register */
|
||||
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11:0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
#define ADC_LTR_SHIFT (0) /* Bits 11:0: Analog watchdog low threshold */
|
||||
#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 1 */
|
||||
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 23:20 L[3:0]: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
|
||||
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
|
||||
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
|
||||
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
|
||||
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
|
||||
#define ADC_SQR1_L_SHIFT (20) /* Bits 23:20 L[3:0]: Regular channel sequence length */
|
||||
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 2 */
|
||||
|
||||
#define ADC_SQR1_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24:20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29:25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
#define ADC_SQR1_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
|
||||
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
|
||||
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
|
||||
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
|
||||
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24:20: 11th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
|
||||
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29:25: 12th conversion in regular sequence */
|
||||
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
|
||||
|
||||
/* ADC regular sequence register 3 */
|
||||
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24:20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29:25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
|
||||
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
|
||||
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
|
||||
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
|
||||
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24:20: 5th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
|
||||
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29:25: 6th conversion in regular sequence */
|
||||
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
|
||||
|
||||
/* ADC injected sequence register */
|
||||
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21:20 JL[1:0]: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
|
||||
#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
|
||||
#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
|
||||
#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence */
|
||||
#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT)
|
||||
#define ADC_JSQR_JL_SHIFT (20) /* Bits 21:20 JL[1:0]: Injected Sequence length */
|
||||
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
|
||||
|
||||
/* ADC injected data register 1-4 */
|
||||
|
||||
#define ADC_JDR_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_MASK (0xffff << ADC_JDR_SHIFT)
|
||||
#define ADC_JDR_SHIFT (0) /* Bits 15-0: Injected data */
|
||||
#define ADC_JDR_MASK (0xffff << ADC_JDR_SHIFT)
|
||||
|
||||
/* ADC regular data register */
|
||||
|
||||
#define ADC_DR_DATA_SHIFT (0) /* Bits 15:0 Regular data */
|
||||
#define ADC_DR_DATA_MASK (0xffff << yyyy)
|
||||
#define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31:16: ADC2 data */
|
||||
#define ADC_DR_ADC2DATA_MASK (0xffff << yyyy)
|
||||
#define ADC_DR_DATA_SHIFT (0) /* Bits 15:0 Regular data */
|
||||
#define ADC_DR_DATA_MASK (0xffff << yyyy)
|
||||
#define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31:16: ADC2 data */
|
||||
#define ADC_DR_ADC2DATA_MASK (0xffff << yyyy)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@ -358,8 +358,8 @@
|
||||
#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */
|
||||
#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */
|
||||
#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */
|
||||
#define CAN_TIR_EXID_MASK (3) /* Bit 20:3: Extended Identifier */
|
||||
#define CAN_TIR_EXID_MASK (0x0003ffff << CAN_TIR_EXID_MASK)
|
||||
#define CAN_TIR_EXID_SHIFT (3) /* Bit 20:3: Extended Identifier */
|
||||
#define CAN_TIR_EXID_MASK (0x0003ffff << CAN_TIR_EXID_SHIFT)
|
||||
#define CAN_TIR_STID_SHIFT (21) /* Bits 31:21: Standard Identifier */
|
||||
#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT)
|
||||
|
||||
@ -397,8 +397,8 @@
|
||||
|
||||
#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */
|
||||
#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */
|
||||
#define CAN_RIR_EXID_MASK (3) /* Bit 20:3: Extended Identifier */
|
||||
#define CAN_RIR_EXID_MASK (0x0003ffff << CAN_TIR_EXID_MASK)
|
||||
#define CAN_RIR_EXID_SHIFT (3) /* Bit 20:3: Extended Identifier */
|
||||
#define CAN_RIR_EXID_MASK (0x0003ffff << CAN_RIR_EXID_SHIFT)
|
||||
#define CAN_RIR_STID_SHIFT (21) /* Bits 31:21: Standard Identifier */
|
||||
#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT)
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_dma.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -42,329 +42,183 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* 7 DMA Channels */
|
||||
|
||||
#define DMA1 0
|
||||
#define DMA2 1
|
||||
#define DMA3 2
|
||||
#define DMA4 3
|
||||
#define DMA5 4
|
||||
#define DMA6 5
|
||||
#define DMA7 6
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
|
||||
#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
|
||||
|
||||
#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
|
||||
#define STM32_DMACHAN_CCR_OFFSET 0x0008
|
||||
#define STM32_DMACHAN_CNDTR_OFFSET 0x000c
|
||||
#define STM32_DMACHAN_CPAR_OFFSET 0x0010
|
||||
#define STM32_DMACHAN_CMAR_OFFSET 0x0014
|
||||
|
||||
#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
|
||||
|
||||
#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
|
||||
#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
|
||||
#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
|
||||
#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
|
||||
#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
|
||||
#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
|
||||
#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
|
||||
|
||||
#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
|
||||
#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
|
||||
#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
|
||||
#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
|
||||
#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
|
||||
#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
|
||||
#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
|
||||
|
||||
#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
|
||||
#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
|
||||
#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
|
||||
#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
|
||||
#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
|
||||
#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
|
||||
#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
|
||||
|
||||
#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
|
||||
#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
|
||||
#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
|
||||
#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
|
||||
#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
|
||||
#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
|
||||
#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
|
||||
#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
|
||||
#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
|
||||
#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
|
||||
#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
|
||||
|
||||
#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
|
||||
#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
|
||||
#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
|
||||
#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
|
||||
#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
|
||||
#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
|
||||
#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
|
||||
#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
|
||||
#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
|
||||
#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
|
||||
#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
|
||||
#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
|
||||
#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
|
||||
#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
|
||||
#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
|
||||
#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
|
||||
#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
|
||||
|
||||
#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
|
||||
#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
|
||||
#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
|
||||
#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
|
||||
#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
|
||||
#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define DMA_CHAN_SHIFT(n) ((n) << 2)
|
||||
#define DMA_CHAN_MASK 0x0f
|
||||
#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
|
||||
#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
|
||||
#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
|
||||
#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
|
||||
|
||||
/* DMA interrupt status register */
|
||||
|
||||
#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
|
||||
#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
|
||||
#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
|
||||
#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
|
||||
#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
|
||||
#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
|
||||
#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
|
||||
#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
|
||||
#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
|
||||
#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
|
||||
#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
|
||||
#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
|
||||
#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
|
||||
#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
|
||||
|
||||
#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
|
||||
#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
|
||||
#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
|
||||
#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
|
||||
#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
|
||||
#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
|
||||
#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
|
||||
#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
|
||||
#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
|
||||
#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
|
||||
|
||||
#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
|
||||
|
||||
/* DMA channel configuration register */
|
||||
|
||||
#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
|
||||
#define DMA_CCR_PL_SHIFT (12) /* Bits 13-12: Channel Priority level */
|
||||
#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
|
||||
# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
|
||||
# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
|
||||
# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
|
||||
# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
|
||||
#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 11-10: Memory size */
|
||||
#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
|
||||
# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 9-8: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
|
||||
# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
|
||||
# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
|
||||
# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
|
||||
#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
|
||||
#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
|
||||
#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
|
||||
#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
|
||||
#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
|
||||
#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
|
||||
#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
|
||||
#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
|
||||
|
||||
#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
|
||||
|
||||
/* DMA channel number of data register */
|
||||
|
||||
#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
|
||||
#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given channel can be enabled at once.
|
||||
*/
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (1)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||
#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
|
||||
#define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
|
||||
#define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
|
||||
#define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
|
||||
#define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
|
||||
#define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
|
||||
#define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
|
||||
#define DMACHAN_UART4_RX STM32_DMA2_CHAN3
|
||||
#define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
|
||||
#define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
|
||||
#define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
|
||||
#define DMACHAN_SDIO STM32_DMA2_CHAN4
|
||||
#define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
|
||||
#define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
|
||||
#define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
|
||||
#define DMACHAN_ADC3 STM32_DMA2_CHAN5
|
||||
#define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
||||
#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
|
||||
#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
||||
#include "chip/stm32_dma.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg);
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t isr;
|
||||
uint32_t ccr;
|
||||
uint32_t cndtr;
|
||||
uint32_t cpar;
|
||||
uint32_t cmar;
|
||||
};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chan' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chan' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN DMA_HANDLE stm32_dmachannel(int chan);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
|
||||
void *arg, bool half);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
EXTERN void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
|
||||
#else
|
||||
# define stm32_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
EXTERN void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define stm32_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */
|
||||
|
||||
|
||||
91
arch/arm/src/stm32/stm32_eth.h
Normal file
91
arch/arm/src/stm32/stm32_eth.h
Normal file
@ -0,0 +1,91 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_eth.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_ETH_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_ETH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: stm32_ethinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Ethernet driver for one interface. If the STM32 chip
|
||||
* supports multiple Ethernet controllers, then bould specific logic
|
||||
* must implement up_netinitialize() and call this function to initialize
|
||||
* the desiresed interfaces.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if STM32_NTHERNET > 1
|
||||
EXTERN int stm32_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */
|
||||
|
||||
@ -43,7 +43,6 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -97,3 +96,4 @@
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_i2c.h
|
||||
* arch/arm/src/stm32/stm32_i2c.c
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Uros Platise <uros.platise@isotel.eu>
|
||||
@ -64,7 +64,6 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/i2c.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
@ -80,6 +79,7 @@
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_i2c.h"
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C1)
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
@ -159,7 +159,7 @@ void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
|
||||
}
|
||||
|
||||
|
||||
static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst, bool fast)
|
||||
static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst)
|
||||
{
|
||||
/* Disable Peripheral if rising time is to be changed,
|
||||
* and restore state on return. */
|
||||
@ -171,7 +171,7 @@ static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst, bool fast)
|
||||
|
||||
/* Update timing and control registers */
|
||||
|
||||
if (!fast) {
|
||||
if (((struct stm32_i2c_inst_s *)inst)->frequency < 400e3) {
|
||||
|
||||
/* Speed: 100 kHz
|
||||
* Risetime: 1000 ns
|
||||
@ -231,7 +231,7 @@ static int stm32_i2c_init(FAR struct i2c_dev_s *inst)
|
||||
(STM32_BOARD_HCLK / 1000000)
|
||||
);
|
||||
|
||||
stm32_i2c_setclock(inst, false);
|
||||
stm32_i2c_setclock(inst);
|
||||
|
||||
/* Enable I2C */
|
||||
|
||||
@ -293,8 +293,8 @@ static int stm32_i2c2_isr(int irq, void *context)
|
||||
uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *inst, uint32_t frequency)
|
||||
{
|
||||
stm32_i2c_sem_wait(inst);
|
||||
((struct stm32_i2c_inst_s *)inst)->frequency = frequency;
|
||||
|
||||
((struct stm32_i2c_inst_s *)inst)->frequency = frequency;
|
||||
|
||||
stm32_i2c_sem_post(inst);
|
||||
return ((struct stm32_i2c_inst_s *)inst)->frequency;
|
||||
@ -307,7 +307,6 @@ int stm32_i2c_setaddress(FAR struct i2c_dev_s *inst, int addr, int nbits)
|
||||
|
||||
((struct stm32_i2c_inst_s *)inst)->address = addr;
|
||||
|
||||
|
||||
stm32_i2c_sem_post(inst);
|
||||
return OK;
|
||||
}
|
||||
@ -316,8 +315,10 @@ int stm32_i2c_setaddress(FAR struct i2c_dev_s *inst, int addr, int nbits)
|
||||
int stm32_i2c_write(FAR struct i2c_dev_s *inst, const uint8_t *buffer, int buflen)
|
||||
{
|
||||
stm32_i2c_sem_wait(inst);
|
||||
stm32_i2c_sem_post(inst);
|
||||
|
||||
stm32_i2c_setclock(inst);
|
||||
|
||||
stm32_i2c_sem_post(inst);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -325,8 +326,10 @@ int stm32_i2c_write(FAR struct i2c_dev_s *inst, const uint8_t *buffer, int bufle
|
||||
int stm32_i2c_read(FAR struct i2c_dev_s *inst, uint8_t *buffer, int buflen)
|
||||
{
|
||||
stm32_i2c_sem_wait(inst);
|
||||
stm32_i2c_sem_post(inst);
|
||||
|
||||
stm32_i2c_setclock(inst);
|
||||
|
||||
stm32_i2c_sem_post(inst);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -335,8 +338,9 @@ int stm32_i2c_read(FAR struct i2c_dev_s *inst, uint8_t *buffer, int buflen)
|
||||
int stm32_i2c_transfer(FAR struct i2c_dev_s *inst, FAR struct i2c_msg_s *msgs, int count)
|
||||
{
|
||||
stm32_i2c_sem_wait(inst);
|
||||
stm32_i2c_sem_post(inst);
|
||||
|
||||
|
||||
stm32_i2c_sem_post(inst);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
@ -449,3 +453,5 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * inst)
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C1 */
|
||||
|
||||
|
||||
@ -41,152 +41,10 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */
|
||||
#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */
|
||||
#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */
|
||||
#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */
|
||||
#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
|
||||
#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
|
||||
#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NI2C > 0
|
||||
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NI2C > 1
|
||||
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
|
||||
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
|
||||
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
|
||||
# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET)
|
||||
# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET)
|
||||
# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET)
|
||||
# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET)
|
||||
# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
|
||||
# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable*/
|
||||
#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */
|
||||
#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */
|
||||
#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */
|
||||
#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */
|
||||
#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */
|
||||
#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */
|
||||
#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */
|
||||
#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */
|
||||
#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */
|
||||
#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */
|
||||
#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */
|
||||
#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */
|
||||
#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
|
||||
#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
|
||||
#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */
|
||||
#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
|
||||
#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
|
||||
#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
|
||||
|
||||
/* Own address register 1 */
|
||||
|
||||
#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */
|
||||
#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */
|
||||
#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT)
|
||||
#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/
|
||||
#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT)
|
||||
#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */
|
||||
#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */
|
||||
|
||||
/* Own address register 2 */
|
||||
|
||||
#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */
|
||||
#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */
|
||||
#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT)
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */
|
||||
#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT)
|
||||
|
||||
/* Status register 1 */
|
||||
|
||||
#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */
|
||||
#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */
|
||||
#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */
|
||||
#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */
|
||||
#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */
|
||||
#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */
|
||||
#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */
|
||||
#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */
|
||||
#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */
|
||||
#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */
|
||||
#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */
|
||||
#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */
|
||||
#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */
|
||||
|
||||
/* Status register 2 */
|
||||
|
||||
#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */
|
||||
#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */
|
||||
#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */
|
||||
#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */
|
||||
#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */
|
||||
#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */
|
||||
#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */
|
||||
#define I2C_SR2_PEC_SHIFT (1) /* Bits 15-8: Packet Error Checking Register */
|
||||
#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT)
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */
|
||||
#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT)
|
||||
#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */
|
||||
#define I2C_CCR_FS (1 << 15) /* Bit 15: I2C Master Mode Selection */
|
||||
|
||||
/* TRISE Register */
|
||||
|
||||
#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */
|
||||
#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_i2c.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */
|
||||
|
||||
|
||||
@ -1,104 +1,104 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_idle.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() up_ledon(LED_IDLE)
|
||||
# define END_IDLE() up_ledoff(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
sched_process_timer();
|
||||
#else
|
||||
|
||||
/* Sleep until an interrupt occurs to save power */
|
||||
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_idle.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() up_ledon(LED_IDLE)
|
||||
# define END_IDLE() up_ledoff(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
sched_process_timer();
|
||||
#else
|
||||
|
||||
/* Sleep until an interrupt occurs to save power */
|
||||
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@ -40,387 +40,6 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "stm32.h"
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE)
|
||||
# undef CONFIG_DEBUG_DMA
|
||||
#endif
|
||||
|
||||
/* NVIC priority levels *************************************************************/
|
||||
|
||||
#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */
|
||||
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
|
||||
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t isr, void *arg);
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
struct stm32_dmaregs_s
|
||||
{
|
||||
uint32_t isr;
|
||||
uint32_t ccr;
|
||||
uint32_t cndtr;
|
||||
uint32_t cpar;
|
||||
uint32_t cmar;
|
||||
};
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* This symbol references the Cortex-M3 vector table (as positioned by the the linker
|
||||
* script, ld.script or ld.script.dfu. The standard location for the vector table is
|
||||
* at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU
|
||||
* bootloader, then the vector table will be offset to a different location in FLASH
|
||||
* and we will need to set the NVIC vector location to this alternative location.
|
||||
*/
|
||||
|
||||
extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level initialization.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_lowsetup(void);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_clockconfig(void);
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chan' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chan' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN DMA_HANDLE stm32_dmachannel(int chan);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
|
||||
void *arg, bool half);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void stm32_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
EXTERN void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs);
|
||||
#else
|
||||
# define stm32_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
EXTERN void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define stm32_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: stm32_ethinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Ethernet driver for one interface. If the STM32 chip
|
||||
* supports multiple Ethernet controllers, then bould specific logic
|
||||
* must implement up_netinitialize() and call this function to initialize
|
||||
* the desiresed interfaces.
|
||||
*
|
||||
* Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if STM32_NTHERNET > 1
|
||||
EXTERN int stm32_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_spi1/2/3select and stm32_spi1/2/3status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/3select, stm32_spi1/2/3status, and
|
||||
* stm32_spi1/2/3cmddata must be provided by board-specific logic. These are
|
||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
|
||||
* (including up_spiinitialize()) are provided by common STM32 logic. To use this
|
||||
* common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
|
||||
* board-specific logic. These functions will perform chip selection and
|
||||
* status operations using GPIOs in the way your board is configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
|
||||
* provide stm32_spi1/2/3cmddata() functions in your board-specific logic.
|
||||
* These functions will perform cmd/data selection operations using GPIOs in the
|
||||
* way your board is configured.
|
||||
* 4. Add a calls to up_spiinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 5. The handle returned by up_spiinitialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
struct spi_dev_s;
|
||||
enum spi_dev_e;
|
||||
EXTERN void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
EXTERN void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
EXTERN void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbpullup
|
||||
*
|
||||
* Description:
|
||||
* If USB is supported and the board supports a pullup via GPIO (for USB software
|
||||
* connect and disconnect), then the board software must provide stm32_pullup.
|
||||
* See include/nuttx/usb/usbdev.h for additional description of this method.
|
||||
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
|
||||
* NULL.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
struct usbdev_s;
|
||||
EXTERN int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
|
||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
struct usbdev_s;
|
||||
EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||
EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- posssible from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_INTERNAL_H */
|
||||
|
||||
79
arch/arm/src/stm32/stm32_lowputc.h
Normal file
79
arch/arm/src/stm32/stm32_lowputc.h
Normal file
@ -0,0 +1,79 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_lowputc.h
|
||||
*
|
||||
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level initialization
|
||||
* of serial console.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_lowsetup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */
|
||||
|
||||
@ -1,155 +1,155 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* FLASH and SRAM *******************************************************************/
|
||||
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000 - Up to 512Kb */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 64Kb SRAM */
|
||||
#define STM32_SRAMBB_BASE 0x22000000
|
||||
#define STM32_PERIPH_BASE 0x40000000
|
||||
|
||||
/* Register Base Address ************************************************************/
|
||||
|
||||
/* APB1 bus */
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000 - 0x400003ff: TIM2 timer */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400 - 0x400007ff: TIM3 timer */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800 - 0x40000bff: TIM4 timer */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00 - 0x40000fff: TIM5 timer */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000 - 0x400013ff: TIM6 timer */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400 - 0x400007ff: TIM7 timer */
|
||||
/* 0x40001800 - 0x40000fff: Reserved */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800 - 0x40002bff: RTC */
|
||||
#define STM32_WWDG_BASE 0x40002C00 /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
|
||||
/* 0x40003400 - 0x400037ff: Reserved */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800 - 0x40003bff: SPI2/I22 */
|
||||
#define STM32_I2S2_BASE 0x40003800
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00 - 0x40003fff: SPI3/I23 */
|
||||
#define STM32_I2S3_BASE 0x40003c00
|
||||
/* 0x40004000 - 0x400043ff: Reserved */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400 - 0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800 - 0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00 - 0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000 - 0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400 - 0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800 - 0x40005Bff: I2C2 */
|
||||
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00 - 0x40005fff: USB device FS registers */
|
||||
#define STM32_USBCANRAM_BASE 0x40006000 /* 0x40006000 - 0x400063ff: Shared USB/CAN SRAM 512 bytes */
|
||||
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400 - 0x400067ff: bxCAN1 */
|
||||
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800 - 0x40006bff: bxCAN2 */
|
||||
#define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */
|
||||
/* 0x40007800 - 0x4000ffff: Reserved */
|
||||
|
||||
/* APB2 bus */
|
||||
|
||||
#define STM32_AFIO_BASE 0x40010000 /* 0x40010000 - 0x400103ff: AFIO */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400 - 0x400107ff: EXTI */
|
||||
#define STM32_GPIOA_BASE 0x40010800 /* 0x40010800 - 0x40010bff: GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0X40010c00 /* 0X40010c00 - 0x40010fff: GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x40011000 /* 0x40011000 - 0x400113ff: GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0x40011400 /* 0x40011400 - 0x400117ff: GPIO Port D */
|
||||
#define STM32_GPIOE_BASE 0x40011800 /* 0x40011800 - 0x40011bff: GPIO Port E */
|
||||
#define STM32_GPIOF_BASE 0x40011c00 /* 0x4001c000 - 0x400111ff: GPIO Port F */
|
||||
#define STM32_GPIOG_BASE 0x40012000 /* 0x40012000 - 0x400123ff: GPIO Port G */
|
||||
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400 - 0x400127ff: ADC1 */
|
||||
#define STM32_ADC2_BASE 0x40012800 /* 0x40012800 - 0x40012bff: ADC2 */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00 - 0x40012fff: TIM1 timer */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000 - 0x400133ff: SPI1 */
|
||||
#define STM32_TIM8_BASE 0x40013400 /* 0x40013400 - 0x400137ff: TIM8 timer */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800 - 0x40013bff: USART1 */
|
||||
#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013fff: ADC3 */
|
||||
/* 0x40014000 - 0x40017fff: Reserved */
|
||||
/* AHB bus */
|
||||
|
||||
#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */
|
||||
/* 0x40018400 - 0x40017fff: Reserved */
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */
|
||||
/* 0x40020800 - 0x40020fff: Reserved */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
|
||||
/* 0x40021400 - 0x40021fff: Reserved */
|
||||
#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */
|
||||
#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: RC */
|
||||
/* 0x40023400 - 0x40027fff: Reserved */
|
||||
#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
|
||||
/* 0x40030000 - 0x4fffffff: Reserved */
|
||||
|
||||
/* Peripheral BB base */
|
||||
|
||||
#define STM32_PERIPHBB_BASE 0x42000000
|
||||
|
||||
/* Flexible SRAM controller (FSMC) */
|
||||
|
||||
#define STM32_FSMC_BASE 0xa0000000
|
||||
|
||||
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
|
||||
* address range
|
||||
*/
|
||||
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* FLASH and SRAM *******************************************************************/
|
||||
|
||||
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000 - Up to 512Kb */
|
||||
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000 - 64Kb SRAM */
|
||||
#define STM32_SRAMBB_BASE 0x22000000
|
||||
#define STM32_PERIPH_BASE 0x40000000
|
||||
|
||||
/* Register Base Address ************************************************************/
|
||||
|
||||
/* APB1 bus */
|
||||
|
||||
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000 - 0x400003ff: TIM2 timer */
|
||||
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400 - 0x400007ff: TIM3 timer */
|
||||
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800 - 0x40000bff: TIM4 timer */
|
||||
#define STM32_TIM5_BASE 0x40000c00 /* 0x40000c00 - 0x40000fff: TIM5 timer */
|
||||
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000 - 0x400013ff: TIM6 timer */
|
||||
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400 - 0x400007ff: TIM7 timer */
|
||||
/* 0x40001800 - 0x40000fff: Reserved */
|
||||
#define STM32_RTC_BASE 0x40002800 /* 0x40002800 - 0x40002bff: RTC */
|
||||
#define STM32_WWDG_BASE 0x40002C00 /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
|
||||
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
|
||||
/* 0x40003400 - 0x400037ff: Reserved */
|
||||
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800 - 0x40003bff: SPI2/I22 */
|
||||
#define STM32_I2S2_BASE 0x40003800
|
||||
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00 - 0x40003fff: SPI3/I23 */
|
||||
#define STM32_I2S3_BASE 0x40003c00
|
||||
/* 0x40004000 - 0x400043ff: Reserved */
|
||||
#define STM32_USART2_BASE 0x40004400 /* 0x40004400 - 0x400047ff: USART2 */
|
||||
#define STM32_USART3_BASE 0x40004800 /* 0x40004800 - 0x40004bff: USART3 */
|
||||
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00 - 0x40004fff: UART4 */
|
||||
#define STM32_UART5_BASE 0x40005000 /* 0x40005000 - 0x400053ff: UART5 */
|
||||
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400 - 0x400057ff: I2C1 */
|
||||
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800 - 0x40005Bff: I2C2 */
|
||||
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00 - 0x40005fff: USB device FS registers */
|
||||
#define STM32_USBCANRAM_BASE 0x40006000 /* 0x40006000 - 0x400063ff: Shared USB/CAN SRAM 512 bytes */
|
||||
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400 - 0x400067ff: bxCAN1 */
|
||||
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800 - 0x40006bff: bxCAN2 */
|
||||
#define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
|
||||
#define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */
|
||||
#define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */
|
||||
/* 0x40007800 - 0x4000ffff: Reserved */
|
||||
|
||||
/* APB2 bus */
|
||||
|
||||
#define STM32_AFIO_BASE 0x40010000 /* 0x40010000 - 0x400103ff: AFIO */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400 - 0x400107ff: EXTI */
|
||||
#define STM32_GPIOA_BASE 0x40010800 /* 0x40010800 - 0x40010bff: GPIO Port A */
|
||||
#define STM32_GPIOB_BASE 0X40010c00 /* 0X40010c00 - 0x40010fff: GPIO Port B */
|
||||
#define STM32_GPIOC_BASE 0x40011000 /* 0x40011000 - 0x400113ff: GPIO Port C */
|
||||
#define STM32_GPIOD_BASE 0x40011400 /* 0x40011400 - 0x400117ff: GPIO Port D */
|
||||
#define STM32_GPIOE_BASE 0x40011800 /* 0x40011800 - 0x40011bff: GPIO Port E */
|
||||
#define STM32_GPIOF_BASE 0x40011c00 /* 0x4001c000 - 0x400111ff: GPIO Port F */
|
||||
#define STM32_GPIOG_BASE 0x40012000 /* 0x40012000 - 0x400123ff: GPIO Port G */
|
||||
#define STM32_ADC1_BASE 0x40012400 /* 0x40012400 - 0x400127ff: ADC1 */
|
||||
#define STM32_ADC2_BASE 0x40012800 /* 0x40012800 - 0x40012bff: ADC2 */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00 - 0x40012fff: TIM1 timer */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000 - 0x400133ff: SPI1 */
|
||||
#define STM32_TIM8_BASE 0x40013400 /* 0x40013400 - 0x400137ff: TIM8 timer */
|
||||
#define STM32_USART1_BASE 0x40013800 /* 0x40013800 - 0x40013bff: USART1 */
|
||||
#define STM32_ADC3_BASE 0x40012800 /* 0x40012800 - 0x40013fff: ADC3 */
|
||||
/* 0x40014000 - 0x40017fff: Reserved */
|
||||
/* AHB bus */
|
||||
|
||||
#define STM32_SDIO_BASE 0x40018000 /* 0x40018000 - 0x400183ff: SDIO */
|
||||
/* 0x40018400 - 0x40017fff: Reserved */
|
||||
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000 - 0x400203ff: DMA1 */
|
||||
#define STM32_DMA2_BASE 0x40020400 /* 0x40020000 - 0x400207ff: DMA2 */
|
||||
/* 0x40020800 - 0x40020fff: Reserved */
|
||||
#define STM32_RCC_BASE 0x40021000 /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
|
||||
/* 0x40021400 - 0x40021fff: Reserved */
|
||||
#define STM32_OTGFS_BASE 0x50000000 /* 0x50000000 - 0x500003ff: USB OTG FS */
|
||||
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000 - 0x400223ff: Flash memory interface */
|
||||
#define STM32_CRC_BASE 0x40028000 /* 0x40023000 - 0x400233ff: RC */
|
||||
/* 0x40023400 - 0x40027fff: Reserved */
|
||||
#define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */
|
||||
/* 0x40030000 - 0x4fffffff: Reserved */
|
||||
|
||||
/* Peripheral BB base */
|
||||
|
||||
#define STM32_PERIPHBB_BASE 0x42000000
|
||||
|
||||
/* Flexible SRAM controller (FSMC) */
|
||||
|
||||
#define STM32_FSMC_BASE 0xa0000000
|
||||
|
||||
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
|
||||
* address range
|
||||
*/
|
||||
|
||||
#define STM32_SCS_BASE 0xe000e000
|
||||
#define STM32_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_rcc.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -43,274 +43,50 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */
|
||||
#define STM32_RCC_CFGR_OFFSET 0x0004 /* Clock configuration register */
|
||||
#define STM32_RCC_CIR_OFFSET 0x0008 /* Clock interrupt register */
|
||||
#define STM32_RCC_APB2RSTR_OFFSET 0x000c /* APB2 Peripheral reset register */
|
||||
#define STM32_RCC_APB1RSTR_OFFSET 0x0010 /* APB1 Peripheral reset register */
|
||||
#define STM32_RCC_AHBENR_OFFSET 0x0014 /* AHB Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB2ENR_OFFSET 0x0018 /* APB2 Peripheral Clock enable register */
|
||||
#define STM32_RCC_APB1ENR_OFFSET 0x001c /* APB1 Peripheral Clock enable register */
|
||||
#define STM32_RCC_BDCR_OFFSET 0x0020 /* Backup domain control register */
|
||||
#define STM32_RCC_CSR_OFFSET 0x0024 /* Control/status register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
|
||||
#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
|
||||
#define STM32_RCC_CIR (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
|
||||
#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
|
||||
#define STM32_RCC_APB1RSTR (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
|
||||
#define STM32_RCC_AHBENR (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
|
||||
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
|
||||
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
|
||||
#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
|
||||
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */
|
||||
#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */
|
||||
#define RCC_CR_HSITRIM_SHIFT (3) /* Bits 7-3: Internal High Speed clock trimming */
|
||||
#define RCC_CR_HSITRIM_MASK (0x1f << RCC_CR_HSITRIM_SHIFT)
|
||||
#define RCC_CR_HSICAL_SHIFT (8) /* Bits 15-8: Internal High Speed clock Calibration */
|
||||
#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
|
||||
#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */
|
||||
#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready flag */
|
||||
#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
|
||||
#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
|
||||
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_SW_SHIFT (0) /* Bits 1-0: System clock Switch */
|
||||
#define RCC_CFGR_SW_MASK (3 << RCC_CFGR_SW_SHIFT)
|
||||
# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
|
||||
# define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
|
||||
# define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
|
||||
#define RCC_CFGR_SWS_SHIFT (2) /* Bits 3-2: System Clock Switch Status */
|
||||
#define RCC_CFGR_SWS_MASK (3 << RCC_CFGR_SWS_SHIFT)
|
||||
# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
|
||||
# define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
|
||||
#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 7-4: AHB prescaler */
|
||||
#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
|
||||
# define RCC_CFGR_HPRE_SYSCLK (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd2 (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd4 (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd8 (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd16 (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd64 (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd128 (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd256 (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
|
||||
# define RCC_CFGR_HPRE_SYSCLKd512 (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
|
||||
#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 10-8: APB Low speed prescaler (APB1) */
|
||||
#define RCC_CFGR_PPRE1_MASK (7 << RCC_CFGR_PPRE1_SHIFT)
|
||||
# define RCC_CFGR_PPRE1_HCLK (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE1_HCLKd2 (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd4 (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd8 (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE1_HCLKd16 (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 13-11: APB High speed prescaler (APB2) */
|
||||
#define RCC_CFGR_PPRE2_MASK (7 << RCC_CFGR_PPRE2_SHIFT)
|
||||
# define RCC_CFGR_PPRE2_HCLK (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
|
||||
# define RCC_CFGR_PPRE2_HCLKd2 (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd4 (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd8 (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
|
||||
# define RCC_CFGR_PPRE2_HCLKd16 (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
|
||||
#define RCC_CFGR_ADCPRE_SHIFT (14) /* Bits 15-14: ADC prescaler */
|
||||
#define RCC_CFGR_ADCPRE_MASK (3 << RCC_CFGR_ADCPRE_SHIFT)
|
||||
# define RCC_CFGR_PLCK2d2 (0 << RCC_CFGR_ADCPRE_SHIFT) /* 00: PLCK2 divided by 2 */
|
||||
# define RCC_CFGR_PLCK2d4 (1 << RCC_CFGR_ADCPRE_SHIFT) /* 01: PLCK2 divided by 4 */
|
||||
# define RCC_CFGR_PLCK2d6 (2 << RCC_CFGR_ADCPRE_SHIFT) /* 10: PLCK2 divided by 6 */
|
||||
# define RCC_CFGR_PLCK2d8 (3 << RCC_CFGR_ADCPRE_SHIFT) /* 11: PLCK2 divided by 8 */
|
||||
#define RCC_CFGR_PLLSRC (1 << 16) /* Bit 16: PLL entry clock source */
|
||||
#define RCC_CFGR_PLLXTPRE (1 << 17) /* Bit 17: HSE divider for PLL entry */
|
||||
#define RCC_CFGR_PLLMUL_SHIFT (18) /* Bits 21-18: PLL Multiplication Factor */
|
||||
#define RCC_CFGR_PLLMUL_MASK (0x0f << RCC_CFGR_PLLMUL_SHIFT)
|
||||
# define RCC_CFGR_PLLMUL_CLKx2 (0 << RCC_CFGR_PLLMUL_SHIFT) /* 0000: PLL input clock x 2 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx3 (1 << RCC_CFGR_PLLMUL_SHIFT) /* 0001: PLL input clock x 3 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx4 (2 << RCC_CFGR_PLLMUL_SHIFT) /* 0010: PLL input clock x 4 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx5 (3 << RCC_CFGR_PLLMUL_SHIFT) /* 0011: PLL input clock x 5 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx6 (4 << RCC_CFGR_PLLMUL_SHIFT) /* 0100: PLL input clock x 6 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx7 (5 << RCC_CFGR_PLLMUL_SHIFT) /* 0101: PLL input clock x 7 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx8 (6 << RCC_CFGR_PLLMUL_SHIFT) /* 0110: PLL input clock x 8 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx9 (7 << RCC_CFGR_PLLMUL_SHIFT) /* 0111: PLL input clock x 9 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx10 (8 << RCC_CFGR_PLLMUL_SHIFT) /* 1000: PLL input clock x 10 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx11 (9 << RCC_CFGR_PLLMUL_SHIFT) /* 1001: PLL input clock x 11 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx12 (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx13 (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx14 (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
|
||||
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
|
||||
#define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB prescaler */
|
||||
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 26-24: Microcontroller Clock Output */
|
||||
#define RCC_CFGR_MCO_MASK (7 << RCC_CFGR_MCO_SHIFT)
|
||||
# define RCC_CFGR_NOCLK (0 << RCC_CFGR_MCO_SHIFT) /* 0xx: No clock */
|
||||
# define RCC_CFGR_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock selected */
|
||||
# define RCC_CFGR_INTCLK (5 << RCC_CFGR_MCO_SHIFT) /* 101: Internal 8 MHz RC oscillator clock selected */
|
||||
# define RCC_CFGR_EXTCLK (6 << RCC_CFGR_MCO_SHIFT) /* 110: External 1-25 MHz oscillator clock selected */
|
||||
# define RCC_CFGR_PLLCLKd2 (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
|
||||
|
||||
/* Clock interrupt register */
|
||||
|
||||
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt flag */
|
||||
#define RCC_CIR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt flag */
|
||||
#define RCC_CIR_HSIRDYF (1 << 2) /* Bit 2: HSI Ready Interrupt flag */
|
||||
#define RCC_CIR_HSERDYF (1 << 3) /* Bit 3: HSE Ready Interrupt flag */
|
||||
#define RCC_CIR_PLLRDYF (1 << 4) /* Bit 4: PLL Ready Interrupt flag */
|
||||
#define RCC_CIR_CSSF (1 << 7) /* Bit 7: Clock Security System Interrupt flag */
|
||||
#define RCC_CIR_LSIRDYIE (1 << 8) /* Bit 8: LSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSERDYIE (1 << 9) /* Bit 9: LSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSIRDYIE (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
|
||||
#define RCC_CIR_HSERDYIE (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
|
||||
#define RCC_CIR_PLLRDYIE (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
|
||||
#define RCC_CIR_LSIRDYC (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_LSERDYC (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSIRDYC (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
|
||||
#define RCC_CIR_HSERDYC (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
|
||||
#define RCC_CIR_PLLRDYC (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
|
||||
#define RCC_CIR_CSSC (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
|
||||
|
||||
/* APB2 Peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_AFIORST (1 << 0) /* Bit 0: Alternate Function I/O reset */
|
||||
#define RCC_APB2RSTR_IOPARST (1 << 2) /* Bit 2: I/O port A reset */
|
||||
#define RCC_APB2RSTR_IOPBRST (1 << 3) /* Bit 3: IO port B reset */
|
||||
#define RCC_APB2RSTR_IOPCRST (1 << 4) /* Bit 4: IO port C reset */
|
||||
#define RCC_APB2RSTR_IOPDRST (1 << 5) /* Bit 5: IO port D reset */
|
||||
#define RCC_APB2RSTR_IOPERST (1 << 6) /* Bit 6: IO port E reset */
|
||||
#define TCC_APB2RSTR_IOPFRST (1 << 7) /* Bit 7: IO port F reset */
|
||||
#define TCC_APB2RSTR_IOPGRST (1 << 8) /* Bit 8: IO port G reset */
|
||||
#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC 1 interface reset */
|
||||
#define RCC_APB2RSTR_ADC2RST (1 << 10) /* Bit 10: ADC 2 interface reset */
|
||||
#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 Timer reset */
|
||||
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */
|
||||
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 Timer reset */
|
||||
#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
|
||||
#define RCC_APB2RTST_ADC2RST (1 << 15) /* Bit 15: ADC3 interface reset */
|
||||
|
||||
/* APB1 Peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_TIM2RST (1 << 0) /* Bit 0: Timer 2 reset */
|
||||
#define RCC_APB1RSTR_TIM3RST (1 << 1) /* Bit 1: Timer 3 reset */
|
||||
#define RCC_APB1RSTR_TIM4RST (1 << 2) /* Bit 2: Timer 4 reset */
|
||||
#define RCC_APB1RSTR_TIM5RST (1 << 3) /* Bit 3: Timer 5 reset */
|
||||
#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */
|
||||
#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */
|
||||
#define RCC_APB1RSTR_WWDGRST (1 << 11) /* Bit 11: Window Watchdog reset */
|
||||
#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
|
||||
#define RCC_APB1RSTR_SPI3RST (1 << 15) /* Bit 15: SPI 3 reset */
|
||||
#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
|
||||
#define RCC_APB1RSTR_USART3RST (1 << 18) /* Bit 18: USART 3 reset */
|
||||
#define RCC_APB1RSTR_UART4RST (1 << 19) /* Bit 19: UART 4 reset */
|
||||
#define RCC_APB1RSTR_UART5RST (1 << 20) /* Bit 18: UART 5 reset */
|
||||
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
|
||||
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
|
||||
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
|
||||
#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */
|
||||
#define RCC_APB1RSTR_BKPRST (1 << 27) /* Bit 27: Backup interface reset */
|
||||
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
|
||||
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
|
||||
|
||||
/* AHB Peripheral Clock enable register */
|
||||
|
||||
#define RCC_AHBENR_DMA1EN (1 << 0) /* Bit 0: DMA1 clock enable */
|
||||
#define RCC_AHBENR_DMA2EN (1 << 1) /* Bit 1: DMA2 clock enable */
|
||||
#define RCC_AHBENR_SRAMEN (1 << 2) /* Bit 2: SRAM interface clock enable */
|
||||
#define RCC_AHBENR_FLITFEN (1 << 4) /* Bit 4: FLITF clock enable */
|
||||
#define RCC_AHBENR_CRCEN (1 << 6) /* Bit 6: CRC clock enable */
|
||||
#define RCC_AHBENR_FSMCEN (1 << 8) /* Bit 8: FSMC clock enable */
|
||||
#define RCC_AHBENR_SDIOEN (1 << 10) /* Bit 10: SDIO clock enable */
|
||||
|
||||
/* APB2 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_AFIOEN (1 << 0) /* Bit 0: Alternate Function I/O clock enable */
|
||||
#define RCC_APB2ENR_IOPEN(n) (1 << ((n)+2))
|
||||
#define RCC_APB2ENR_IOPAEN (1 << 2) /* Bit 2: I/O port A clock enable */
|
||||
#define RCC_APB2ENR_IOPBEN (1 << 3) /* Bit 3: I/O port B clock enable */
|
||||
#define RCC_APB2ENR_IOPCEN (1 << 4) /* Bit 4: I/O port C clock enable */
|
||||
#define RCC_APB2ENR_IOPDEN (1 << 5) /* Bit 5: I/O port D clock enable */
|
||||
#define RCC_APB2ENR_IOPEEN (1 << 6) /* Bit 6: I/O port E clock enable */
|
||||
#define RCC_APB2ENR_IOPFEN (1 << 7) /* Bit 7: I/O port F clock enable */
|
||||
#define RCC_APB2ENR_IOPGEN (1 << 8) /* Bit 8: I/O port G clock enable */
|
||||
#define RCC_APB2ENR_ADC1EN (1 << 9) /* Bit 9: ADC 1 interface clock enable */
|
||||
#define RCC_APB2ENR_ADC2EN (1 << 10) /* Bit 10: ADC 2 interface clock enable */
|
||||
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 Timer clock enable */
|
||||
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */
|
||||
#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 Timer clock enable */
|
||||
#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */
|
||||
#define RCC_APB2ENR_ADC3EN (1 << 15) /* Bit 14: ADC3 interface clock enable */
|
||||
|
||||
/* APB1 Peripheral Clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_TIM2EN (1 << 0) /* Bit 0: Timer 2 clock enable */
|
||||
#define RCC_APB1ENR_TIM3EN (1 << 1) /* Bit 1: Timer 3 clock enable */
|
||||
#define RCC_APB1ENR_TIM4EN (1 << 2) /* Bit 2: Timer 4 clock enable */
|
||||
#define RCC_APB1ENR_TIM5EN (1 << 3) /* Bit 3: Timer 5 clock enable */
|
||||
#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 clock enable */
|
||||
#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 clock enable */
|
||||
#define RCC_APB1ENR_WWDGEN (1 << 11) /* Bit 11: Window Watchdog clock enable */
|
||||
#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 clock enable */
|
||||
#define RCC_APB1ENR_SPI3EN (1 << 15) /* Bit 15: SPI 3 clock enable */
|
||||
#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 clock enable */
|
||||
#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 clock enable */
|
||||
#define RCC_APB1ENR_UART4EN (1 << 19) /* Bit 19: UART 4 clock enable */
|
||||
#define RCC_APB1ENR_UART5EN (1 << 20) /* Bit 20: UART 5 clock enable */
|
||||
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
|
||||
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
|
||||
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
|
||||
#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */
|
||||
#define RCC_APB1ENR_BKPEN (1 << 27) /* Bit 27: Backup interface clock enable */
|
||||
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
|
||||
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
|
||||
#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
|
||||
#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */
|
||||
#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT)
|
||||
# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
|
||||
# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
|
||||
# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
|
||||
#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
|
||||
#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
|
||||
#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LSION (1 << 0) /* Bit 0: Internal Low Speed oscillator enable */
|
||||
#define RCC_CSR_LSIRDY (1 << 1) /* Bit 1: Internal Low Speed oscillator Ready */
|
||||
#define RCC_CSR_RMVF (1 << 24) /* Bit 24: Remove reset flag */
|
||||
#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
|
||||
#define RCC_CSR_PORRSTF (1 << 27) /* Bit 27: POR/PDR reset flag */
|
||||
#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
|
||||
#define RCC_CSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */
|
||||
#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
|
||||
#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_rcc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* This symbol references the Cortex-M3 vector table (as positioned by the the linker
|
||||
* script, ld.script or ld.script.dfu. The standard location for the vector table is
|
||||
* at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU
|
||||
* bootloader, then the vector table will be offset to a different location in FLASH
|
||||
* and we will need to set the NVIC vector location to this alternative location.
|
||||
*/
|
||||
|
||||
extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_clockconfig(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_sdio.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -42,270 +42,86 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */
|
||||
#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */
|
||||
#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */
|
||||
#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */
|
||||
#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */
|
||||
#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n))
|
||||
#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */
|
||||
#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */
|
||||
#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */
|
||||
#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */
|
||||
#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */
|
||||
#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */
|
||||
#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */
|
||||
#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */
|
||||
#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */
|
||||
#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */
|
||||
#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */
|
||||
#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */
|
||||
#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET)
|
||||
#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET)
|
||||
#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET)
|
||||
#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET)
|
||||
#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET)
|
||||
#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n))
|
||||
#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET)
|
||||
#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET)
|
||||
#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET)
|
||||
#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET)
|
||||
#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET)
|
||||
#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET)
|
||||
#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET)
|
||||
#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET)
|
||||
#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET)
|
||||
#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET)
|
||||
#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET)
|
||||
#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET)
|
||||
#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET)
|
||||
|
||||
/* Bit-band (BB) base addresses ****************************************************/
|
||||
|
||||
#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE)
|
||||
|
||||
#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5))
|
||||
#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5))
|
||||
#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5))
|
||||
#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5))
|
||||
#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5))
|
||||
#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5))
|
||||
#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5))
|
||||
#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5))
|
||||
#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5))
|
||||
#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5))
|
||||
#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5))
|
||||
#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5))
|
||||
#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5))
|
||||
#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5))
|
||||
#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5))
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
|
||||
#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT)
|
||||
# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
|
||||
# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
|
||||
# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
|
||||
|
||||
#define SDIO_POWER_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */
|
||||
#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */
|
||||
#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */
|
||||
#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */
|
||||
#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */
|
||||
#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT)
|
||||
# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */
|
||||
# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */
|
||||
# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */
|
||||
#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */
|
||||
#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */
|
||||
|
||||
#define SDIO_CLKCR_RESET (0) /* Reset value */
|
||||
#define SDIO_ARG_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4))
|
||||
#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4))
|
||||
#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4))
|
||||
#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4))
|
||||
#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4))
|
||||
|
||||
#define SDIO_CMD_CMDINDEX_SHIFT (0)
|
||||
#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT)
|
||||
#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */
|
||||
#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT)
|
||||
# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */
|
||||
# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */
|
||||
# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */
|
||||
#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */
|
||||
#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */
|
||||
#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */
|
||||
#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */
|
||||
#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */
|
||||
#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */
|
||||
#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */
|
||||
|
||||
#define SDIO_CMD_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4))
|
||||
#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4))
|
||||
#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4))
|
||||
#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4))
|
||||
#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4))
|
||||
#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4))
|
||||
#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4))
|
||||
|
||||
#define SDIO_RESPCMD_SHIFT (0)
|
||||
#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT)
|
||||
|
||||
#define SDIO_DTIMER_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DLEN_SHIFT (0)
|
||||
#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT)
|
||||
|
||||
#define SDIO_DLEN_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
|
||||
#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
|
||||
#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */
|
||||
#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */
|
||||
#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
|
||||
#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
|
||||
#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
|
||||
#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
|
||||
#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
|
||||
#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
|
||||
|
||||
#define SDIO_DCTRL_RESET (0) /* Reset value */
|
||||
|
||||
#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4))
|
||||
#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4))
|
||||
#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4))
|
||||
#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4))
|
||||
#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4))
|
||||
#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4))
|
||||
#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4))
|
||||
#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4))
|
||||
|
||||
#define SDIO_DATACOUNT_SHIFT (0)
|
||||
#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT)
|
||||
|
||||
#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
|
||||
#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
|
||||
#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
|
||||
#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */
|
||||
#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */
|
||||
#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */
|
||||
#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */
|
||||
#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */
|
||||
#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */
|
||||
#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
|
||||
#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
|
||||
|
||||
#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */
|
||||
#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
|
||||
#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */
|
||||
|
||||
#define SDIO_ICR_RESET 0x00c007ff
|
||||
#define SDIO_ICR_STATICFLAGS 0x000005ff
|
||||
|
||||
#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */
|
||||
#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */
|
||||
#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
|
||||
#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
|
||||
#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
|
||||
#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
|
||||
#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
|
||||
#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
|
||||
|
||||
#define SDIO_MASK_RESET (0)
|
||||
|
||||
#define SDIO_FIFOCNT_SHIFT (0)
|
||||
#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_sdio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||
EXTERN FAR struct sdio_dev_s *sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- posssible from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */
|
||||
|
||||
|
||||
@ -43,104 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define STM32_SPI_CLK_MAX 18000000UL /* Maximum allowed speed as per specifications for all SPIs */
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
|
||||
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
|
||||
#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
|
||||
#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
|
||||
#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
|
||||
#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
|
||||
#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NSPI > 0
|
||||
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NSPI > 1
|
||||
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NSPI > 2
|
||||
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
|
||||
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
|
||||
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
|
||||
# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
|
||||
# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
|
||||
# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
|
||||
# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* SPI Control Register 1 */
|
||||
|
||||
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
|
||||
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
|
||||
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
|
||||
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
|
||||
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
|
||||
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
|
||||
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
|
||||
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
|
||||
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
|
||||
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
|
||||
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
|
||||
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
|
||||
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
|
||||
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
|
||||
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
|
||||
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
|
||||
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
|
||||
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
|
||||
#define SPI_CR1_DFF (1 << 11) /* Bit 11: Data Frame Format */
|
||||
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
|
||||
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
|
||||
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
|
||||
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
|
||||
|
||||
/* SPI Control Register 2 */
|
||||
|
||||
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
|
||||
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
|
||||
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
|
||||
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
|
||||
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
|
||||
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
|
||||
|
||||
/* SPI status register */
|
||||
|
||||
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
|
||||
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
|
||||
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
|
||||
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
|
||||
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
|
||||
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_spi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
@ -156,15 +59,59 @@ extern "C" {
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
struct spi_dev_s;
|
||||
enum spi_dev_e;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_spi1/2/3select and stm32_spi1/2/3status
|
||||
*
|
||||
* Description:
|
||||
* The external functions, stm32_spi1/2/3select, stm32_spi1/2/3status, and
|
||||
* stm32_spi1/2/3cmddata must be provided by board-specific logic. These are
|
||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
|
||||
* (including up_spiinitialize()) are provided by common STM32 logic. To use this
|
||||
* common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
|
||||
* board-specific logic. These functions will perform chip selection and
|
||||
* status operations using GPIOs in the way your board is configured.
|
||||
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, then
|
||||
* provide stm32_spi1/2/3cmddata() functions in your board-specific logic.
|
||||
* These functions will perform cmd/data selection operations using GPIOs in the
|
||||
* way your board is configured.
|
||||
* 4. Add a calls to up_spiinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 5. The handle returned by up_spiinitialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
|
||||
EXTERN void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
|
||||
EXTERN void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
EXTERN uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
EXTERN int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_STM32_SPI_H */
|
||||
|
||||
|
||||
@ -63,6 +63,7 @@
|
||||
#define getreg16(a) (*(volatile uint16_t *)(a))
|
||||
#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v))
|
||||
|
||||
#if defined(CONFIG_STM32_TIM5) && defined(CONFIG_STM32_TIM8)
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
@ -381,15 +382,6 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
|
||||
switch( ((struct stm32_tim_priv_s *)dev)->base ) {
|
||||
|
||||
case STM32_TIM1_BASE:
|
||||
switch(channel) {
|
||||
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
|
||||
case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
|
||||
case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
|
||||
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
|
||||
}
|
||||
break;
|
||||
|
||||
case STM32_TIM2_BASE:
|
||||
switch(channel) {
|
||||
case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break;
|
||||
@ -426,6 +418,16 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
}
|
||||
break;
|
||||
|
||||
#if STM32_NATIM > 0
|
||||
case STM32_TIM1_BASE:
|
||||
switch(channel) {
|
||||
case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
|
||||
case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
|
||||
case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
|
||||
case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
|
||||
}
|
||||
break;
|
||||
|
||||
case STM32_TIM8_BASE:
|
||||
switch(channel) {
|
||||
case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
|
||||
@ -434,7 +436,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
|
||||
case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
|
||||
}
|
||||
break;
|
||||
|
||||
#endif
|
||||
default: return ERROR;
|
||||
}
|
||||
|
||||
@ -582,3 +584,6 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_TIM5 && CONFIG_STM32_TIM8 */
|
||||
|
||||
|
||||
@ -1,10 +1,8 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_tim.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Uros Platise <uros.platise@isotel.eu>
|
||||
* Author: Uros Platise <uros.platise@isotel.eu>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -36,831 +34,17 @@
|
||||
************************************************************************************/
|
||||
|
||||
/** \file
|
||||
* \author Gregory Nutt, Uros Platise
|
||||
* \brief STM32 Timers
|
||||
* \author Uros Platise
|
||||
* \brief STM32 Timer Device Driver
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
|
||||
/* General Timers - TIM2, TIM3, TIM4, and TIM5 */
|
||||
|
||||
#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */
|
||||
#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
|
||||
#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit) */
|
||||
#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */
|
||||
#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 *(16-bit) */
|
||||
#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */
|
||||
#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */
|
||||
#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit) */
|
||||
#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */
|
||||
#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */
|
||||
#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */
|
||||
#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */
|
||||
#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */
|
||||
#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */
|
||||
#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */
|
||||
#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */
|
||||
#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */
|
||||
#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */
|
||||
#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit) */
|
||||
#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */
|
||||
#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
/* Advanced Timers - TIM1 and TIM8 */
|
||||
|
||||
#if STM32_NATIM > 0
|
||||
# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
|
||||
# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NATIM > 1
|
||||
# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
|
||||
# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
|
||||
# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
|
||||
# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
|
||||
# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
|
||||
# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
|
||||
# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
|
||||
# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
|
||||
# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
|
||||
# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
|
||||
# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
|
||||
# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
|
||||
# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
|
||||
# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
|
||||
# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
|
||||
# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
|
||||
# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
|
||||
# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* General Timers - TIM2, TIM3, TIM4, and TIM5 */
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NGTIM > 0
|
||||
# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
|
||||
# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
|
||||
# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
|
||||
# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
|
||||
# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
|
||||
# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
|
||||
# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
|
||||
# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
|
||||
# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
|
||||
# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
|
||||
# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
|
||||
# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
|
||||
# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
|
||||
# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
|
||||
# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
|
||||
# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
|
||||
# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
|
||||
# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Basic Timers - TIM6 and TIM7 */
|
||||
|
||||
#if STM32_NBTIM > 0
|
||||
# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
|
||||
# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NBTIM > 1
|
||||
# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
|
||||
# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
|
||||
# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
|
||||
# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
|
||||
# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
|
||||
# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
|
||||
# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
|
||||
# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
|
||||
#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */
|
||||
#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
|
||||
#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */
|
||||
#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */
|
||||
#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT)
|
||||
# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
|
||||
# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
|
||||
# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
|
||||
# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
|
||||
#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
|
||||
#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */
|
||||
#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT)
|
||||
# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
|
||||
# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
|
||||
# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */
|
||||
#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */
|
||||
#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */
|
||||
#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT)
|
||||
# define ATIM_CR2_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
|
||||
# define ATIM_CR2_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
|
||||
# define ATIM_CR2_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
|
||||
# define ATIM_CR2_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
|
||||
#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
|
||||
#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
|
||||
#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
|
||||
#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
|
||||
#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
|
||||
#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
|
||||
#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
|
||||
#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
|
||||
|
||||
/* Slave mode control register */
|
||||
|
||||
#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
|
||||
#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
|
||||
#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External trigger prescaler */
|
||||
#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT)
|
||||
# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
|
||||
# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
|
||||
# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
|
||||
# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
|
||||
#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External trigger filter */
|
||||
#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT)
|
||||
# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
|
||||
# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
|
||||
#define ATIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger selection */
|
||||
#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT)
|
||||
# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
|
||||
# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
|
||||
# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
|
||||
# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
|
||||
# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
|
||||
# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
|
||||
# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
|
||||
# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
|
||||
#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 2:0: Slave mode selection */
|
||||
#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT)
|
||||
# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
|
||||
# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
|
||||
# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
|
||||
# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
|
||||
# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
|
||||
# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
|
||||
# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
|
||||
# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
|
||||
#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
|
||||
#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
|
||||
#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
|
||||
#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */
|
||||
#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
|
||||
#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */
|
||||
#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
|
||||
#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
|
||||
#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
|
||||
#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
|
||||
#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */
|
||||
#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
|
||||
#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
|
||||
#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
|
||||
#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
|
||||
#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
|
||||
#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
|
||||
#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
|
||||
#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */
|
||||
#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
|
||||
#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
|
||||
#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
|
||||
#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */
|
||||
#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
|
||||
#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */
|
||||
#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */
|
||||
#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */
|
||||
#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */
|
||||
#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */
|
||||
#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */
|
||||
|
||||
/* Capture/compare mode register 1 -- Output compare mode */
|
||||
|
||||
#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
|
||||
#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
|
||||
#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
|
||||
#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
|
||||
#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
|
||||
#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */
|
||||
#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
|
||||
#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
|
||||
#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
|
||||
#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
|
||||
|
||||
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
|
||||
#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
|
||||
#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
|
||||
#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
|
||||
|
||||
/* Common CCMR (unshifted) Compare Mode bit field definitions */
|
||||
|
||||
#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
|
||||
#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
|
||||
#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
|
||||
#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
|
||||
#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
|
||||
#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
|
||||
#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
|
||||
#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
|
||||
|
||||
/* Capture/compare mode register 1 -- Input capture mode */
|
||||
|
||||
/* Bits 1-0:(same as output compare mode) */
|
||||
#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
|
||||
#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
|
||||
#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
/* Bits 9:8 (same as output compare mode) */
|
||||
#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */
|
||||
#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
|
||||
#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions below) */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
|
||||
#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
|
||||
|
||||
#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
|
||||
#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
|
||||
/* Capture/compare mode register 2 - Output Compare mode */
|
||||
|
||||
#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
|
||||
#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
|
||||
#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
|
||||
#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
|
||||
#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
|
||||
#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
|
||||
#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
|
||||
#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
|
||||
#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
|
||||
#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
|
||||
|
||||
/* Capture/compare mode register 2 - Input Capture Mode */
|
||||
|
||||
/* Bits 1-0:(same as output compare mode) */
|
||||
#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
|
||||
#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
|
||||
#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
/* Bits 9:8 (same as output compare mode) */
|
||||
#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */
|
||||
#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
|
||||
#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT)
|
||||
/* (See common (unshifted) bit field definitions above) */
|
||||
|
||||
/* Capture/compare enable register */
|
||||
|
||||
#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
|
||||
#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
|
||||
#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */
|
||||
#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
|
||||
#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
|
||||
#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */
|
||||
#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
|
||||
#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
|
||||
#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
|
||||
#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output Polarity */
|
||||
#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
|
||||
#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
|
||||
|
||||
/* Repetition counter register */
|
||||
|
||||
#define ATIM_RCR_REP_SHIFT (0) /* Bits 7-0: Repetition Counter Value */
|
||||
#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
|
||||
|
||||
/* Break and dead-time register */
|
||||
|
||||
#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
|
||||
#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT)
|
||||
#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
|
||||
#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT)
|
||||
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
|
||||
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
|
||||
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
|
||||
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
|
||||
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
|
||||
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
|
||||
#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
|
||||
#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
|
||||
#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
|
||||
#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
|
||||
|
||||
/* DMA control register */
|
||||
|
||||
#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
|
||||
#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT)
|
||||
#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
|
||||
#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
|
||||
#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
|
||||
#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */
|
||||
#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction */
|
||||
#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection */
|
||||
#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT)
|
||||
# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */
|
||||
# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
|
||||
# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
|
||||
# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
|
||||
#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
|
||||
#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */
|
||||
#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT)
|
||||
# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
|
||||
# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
|
||||
# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection. */
|
||||
#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT)
|
||||
# define GTIM_CR2_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
|
||||
# define GTIM_CR2_ENAB (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
|
||||
# define GTIM_CR2_UPDT (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
|
||||
# define GTIM_CR2_CMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
|
||||
# define GTIM_CR2_CMP1 (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP2 (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP3 (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO) */
|
||||
# define GTIM_CR2_CMP4 (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO) */
|
||||
#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
|
||||
|
||||
/* Slave mode control register */
|
||||
|
||||
#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */
|
||||
#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT)
|
||||
# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
|
||||
# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
|
||||
# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
|
||||
# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
|
||||
# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
|
||||
# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
|
||||
# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
|
||||
# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
|
||||
#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */
|
||||
#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT)
|
||||
# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
|
||||
# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
|
||||
# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
|
||||
# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
|
||||
# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
|
||||
# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
|
||||
# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
|
||||
# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
|
||||
#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */
|
||||
#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter */
|
||||
#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT)
|
||||
# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
|
||||
# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler */
|
||||
#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT)
|
||||
# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
|
||||
# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
|
||||
# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
|
||||
# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
|
||||
#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */
|
||||
#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
|
||||
#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
|
||||
#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
|
||||
#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
|
||||
#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
|
||||
#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
|
||||
#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
|
||||
#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
|
||||
#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
|
||||
#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
|
||||
#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt Flag */
|
||||
#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
|
||||
#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
|
||||
#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
|
||||
#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
|
||||
#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
|
||||
#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
|
||||
#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
|
||||
#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
|
||||
#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */
|
||||
#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation */
|
||||
#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation */
|
||||
#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation */
|
||||
#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation */
|
||||
|
||||
/* Capture/compare mode register 1 - Output compare mode */
|
||||
|
||||
#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */
|
||||
#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions below) */
|
||||
#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
|
||||
#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
|
||||
#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */
|
||||
#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions below) */
|
||||
#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */
|
||||
#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */
|
||||
#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions below) */
|
||||
#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
|
||||
#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
|
||||
#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */
|
||||
#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions below) */
|
||||
#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
|
||||
|
||||
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */
|
||||
#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */
|
||||
#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */
|
||||
#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */
|
||||
|
||||
/* Common CCMR (unshifted) Compare Mode bit field definitions */
|
||||
|
||||
#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */
|
||||
#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */
|
||||
#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */
|
||||
#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
|
||||
#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */
|
||||
#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
|
||||
#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
|
||||
#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
|
||||
|
||||
/* Capture/compare mode register 1 - Input capture mode */
|
||||
|
||||
/* Bits 1-0 (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */
|
||||
#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */
|
||||
#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
/* Bits 9-8: (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */
|
||||
#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */
|
||||
#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */
|
||||
#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */
|
||||
|
||||
/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
|
||||
|
||||
#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */
|
||||
#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */
|
||||
#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */
|
||||
#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */
|
||||
#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */
|
||||
#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */
|
||||
#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */
|
||||
#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */
|
||||
|
||||
/* Capture/compare mode register 2 - Output Compare mode */
|
||||
|
||||
#define GTIM_CCMR1_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */
|
||||
#define GTIM_CCMR1_CC3S_MASK (3 << GTIM_CCMR1_CC3S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions above) */
|
||||
#define GTIM_CCMR1_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
|
||||
#define GTIM_CCMR1_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
|
||||
#define GTIM_CCMR1_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */
|
||||
#define GTIM_CCMR1_OC3M_MASK (7 << GTIM_CCMR1_OC3M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions above) */
|
||||
#define GTIM_CCMR1_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
|
||||
#define GTIM_CCMR1_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */
|
||||
#define GTIM_CCMR1_CC4S_MASK (3 << GTIM_CCMR1_CC4S_SHIFT)
|
||||
/* (See common CCMR Capture/Compare Selection definitions above) */
|
||||
#define GTIM_CCMR1_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
|
||||
#define GTIM_CCMR1_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
|
||||
#define GTIM_CCMR1_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */
|
||||
#define GTIM_CCMR1_OC4M_MASK (7 << GTIM_CCMR1_OC4M_SHIFT)
|
||||
/* (See common CCMR Output Compare Mode definitions above) */
|
||||
#define GTIM_CCMR1_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
|
||||
|
||||
/* Capture/compare mode register 2 - Input capture mode */
|
||||
|
||||
/* Bits 1-0 (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */
|
||||
#define GTIM_CCMR1_IC3PSC_MASK (3 << GTIM_CCMR1_IC3PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */
|
||||
#define GTIM_CCMR1_IC3F_MASK (0x0f << GTIM_CCMR1_IC3F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
/* Bits 9-8: (Same as Output Compare Mode) */
|
||||
#define GTIM_CCMR1_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */
|
||||
#define GTIM_CCMR1_IC4PSC_MASK (3 << GTIM_CCMR1_IC4PSC_SHIFT)
|
||||
/* (See common CCMR Input Capture Prescaler definitions below) */
|
||||
#define GTIM_CCMR1_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */
|
||||
#define GTIM_CCMR1_IC4F_MASK (0x0f << GTIM_CCMR1_IC4F_SHIFT)
|
||||
/* (See common CCMR Input Capture Filter definitions below) */
|
||||
|
||||
/* Capture/compare enable register */
|
||||
|
||||
#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
|
||||
#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */
|
||||
#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
|
||||
#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */
|
||||
#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
|
||||
#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */
|
||||
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
|
||||
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
|
||||
|
||||
/* DMA control register */
|
||||
|
||||
#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */
|
||||
#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT)
|
||||
#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */
|
||||
#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
|
||||
#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */
|
||||
#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */
|
||||
#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */
|
||||
#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */
|
||||
#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT)
|
||||
# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
|
||||
# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
|
||||
# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
|
||||
|
||||
/* DMA/Interrupt enable register */
|
||||
|
||||
#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
|
||||
#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */
|
||||
|
||||
/* Event generation register */
|
||||
|
||||
#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */
|
||||
#include "chip/stm32_tim.h"
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
@ -965,6 +149,7 @@ struct stm32_tim_ops_s {
|
||||
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
@ -976,4 +161,3 @@ FAR struct stm32_tim_dev_s * stm32_tim_init(int timer);
|
||||
int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */
|
||||
|
||||
|
||||
@ -1,211 +1,211 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H
|
||||
#define __ARCH_ARM_STC_STM32_STM32_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
|
||||
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
|
||||
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
|
||||
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
|
||||
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS (0x03ff)
|
||||
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
|
||||
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
|
||||
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
|
||||
#define USART_CR2_LBDL (1 << 6) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 7) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 15-8: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 7:0 [7:0]: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_uart.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H
|
||||
#define __ARCH_ARM_STC_STM32_STM32_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */
|
||||
#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */
|
||||
#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */
|
||||
#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */
|
||||
#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */
|
||||
#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */
|
||||
#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 1
|
||||
# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 0
|
||||
# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
|
||||
# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 3
|
||||
# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
#if STM32_NUSART > 4
|
||||
# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET)
|
||||
# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET)
|
||||
# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
|
||||
# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
|
||||
# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
|
||||
# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* Status register */
|
||||
|
||||
#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */
|
||||
#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */
|
||||
#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */
|
||||
#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */
|
||||
#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
|
||||
#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
|
||||
#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */
|
||||
#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
|
||||
#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */
|
||||
#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */
|
||||
|
||||
#define USART_SR_ALLBITS (0x03ff)
|
||||
#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
|
||||
|
||||
/* Data register */
|
||||
|
||||
#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */
|
||||
#define USART_DR_MASK (0xff << USART_DR_SHIFT)
|
||||
|
||||
/* Baud Rate Register */
|
||||
|
||||
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
|
||||
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
|
||||
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
|
||||
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
|
||||
|
||||
/* Control register 1 */
|
||||
|
||||
#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */
|
||||
#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */
|
||||
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
|
||||
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
|
||||
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
|
||||
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
|
||||
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
|
||||
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
|
||||
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
|
||||
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
|
||||
#define USART_CR1_M (1 << 12) /* Bit 12: word length */
|
||||
#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */
|
||||
|
||||
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
|
||||
|
||||
/* Control register 2 */
|
||||
|
||||
#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */
|
||||
#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT)
|
||||
#define USART_CR2_LBDL (1 << 6) /* Bit 5: LIN Break Detection Length */
|
||||
#define USART_CR2_LBDIE (1 << 7) /* Bit 6: LIN Break Detection Interrupt Enable */
|
||||
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
|
||||
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
|
||||
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
|
||||
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
|
||||
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
|
||||
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
|
||||
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
|
||||
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
|
||||
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
|
||||
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
|
||||
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
|
||||
|
||||
/* Control register 3 */
|
||||
|
||||
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
|
||||
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
|
||||
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
|
||||
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
|
||||
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
|
||||
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
|
||||
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
|
||||
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
|
||||
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
|
||||
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
|
||||
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
|
||||
|
||||
/* Guard time and prescaler register */
|
||||
|
||||
#define USART_GTPR_GT_SHIFT (8) /* Bits 15-8: Guard time value */
|
||||
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
|
||||
#define USART_GTPR_PSC_SHIFT (0) /* Bits 7:0 [7:0]: Prescaler value */
|
||||
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_usbdev.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -41,205 +41,58 @@
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
|
||||
#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
|
||||
#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
|
||||
#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
|
||||
#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
|
||||
#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
|
||||
#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
|
||||
#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
|
||||
#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
|
||||
#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
|
||||
#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
|
||||
#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
|
||||
#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
|
||||
#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
|
||||
#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
|
||||
|
||||
#define STM32_USB_BTABLE_RADDR(ep,o) ((((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) << 1)
|
||||
#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
/* Endpoint Registers */
|
||||
|
||||
#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n))
|
||||
#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET)
|
||||
#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET)
|
||||
#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET)
|
||||
#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET)
|
||||
#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET)
|
||||
#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET)
|
||||
#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET)
|
||||
#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET)
|
||||
|
||||
/* Common Registers */
|
||||
|
||||
#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET)
|
||||
#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET)
|
||||
#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET)
|
||||
#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET)
|
||||
#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET)
|
||||
|
||||
/* Buffer Descriptor Table (Relatative to BTABLE address) */
|
||||
|
||||
#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBCANRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o))
|
||||
#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
|
||||
#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
|
||||
#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
|
||||
#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* USB endpoint register */
|
||||
|
||||
#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */
|
||||
#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT)
|
||||
#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */
|
||||
#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT)
|
||||
# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */
|
||||
# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */
|
||||
# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */
|
||||
# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */
|
||||
# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */
|
||||
# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */
|
||||
#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */
|
||||
#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */
|
||||
#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */
|
||||
#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */
|
||||
#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT)
|
||||
# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */
|
||||
# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */
|
||||
# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */
|
||||
# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */
|
||||
#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */
|
||||
#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */
|
||||
#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT)
|
||||
# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */
|
||||
# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */
|
||||
# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */
|
||||
# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */
|
||||
# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
|
||||
# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
|
||||
#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */
|
||||
|
||||
/* USB control register */
|
||||
|
||||
#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */
|
||||
#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */
|
||||
#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */
|
||||
#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */
|
||||
#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */
|
||||
#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */
|
||||
#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */
|
||||
#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
|
||||
#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
|
||||
#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
|
||||
#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
|
||||
#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
|
||||
#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
|
||||
|
||||
#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\
|
||||
USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM)
|
||||
|
||||
/* USB interrupt status register */
|
||||
|
||||
#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */
|
||||
#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT)
|
||||
#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */
|
||||
#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
|
||||
#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
|
||||
#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
|
||||
#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
|
||||
#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
|
||||
#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
|
||||
#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
|
||||
#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
|
||||
|
||||
#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\
|
||||
USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR)
|
||||
|
||||
/* USB frame number register */
|
||||
|
||||
#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */
|
||||
#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT)
|
||||
#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */
|
||||
#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT)
|
||||
#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */
|
||||
#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */
|
||||
#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */
|
||||
|
||||
/* USB device address */
|
||||
|
||||
#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */
|
||||
#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT)
|
||||
#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */
|
||||
|
||||
/* Buffer table address */
|
||||
|
||||
#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */
|
||||
#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT)
|
||||
|
||||
/* Transmission buffer address */
|
||||
|
||||
#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */
|
||||
#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */
|
||||
#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT)
|
||||
|
||||
/* Transmission byte count */
|
||||
|
||||
#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */
|
||||
#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
|
||||
|
||||
/* Reception buffer address */
|
||||
|
||||
#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */
|
||||
#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
|
||||
#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT)
|
||||
|
||||
/* Reception byte count */
|
||||
|
||||
#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */
|
||||
#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */
|
||||
#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
|
||||
#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
|
||||
#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
#include "chip/stm32_usbdev.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbpullup
|
||||
*
|
||||
* Description:
|
||||
* If USB is supported and the board supports a pullup via GPIO (for USB software
|
||||
* connect and disconnect), then the board software must provide stm32_pullup.
|
||||
* See include/nuttx/usb/usbdev.h for additional description of this method.
|
||||
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
|
||||
* NULL.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
|
||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */
|
||||
|
||||
|
||||
@ -1,448 +1,448 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32f107vc_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions: */
|
||||
|
||||
#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
|
||||
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_ETH_REMAP)
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#else
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_OTG_FSDM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTG_FSDP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTG_FSID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTG_FSSOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTG_FSVBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#if defined(CONFIG_STM32_TIM4_REMAP)
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#else
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#endif
|
||||
#define GPIO_TIM4_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH4IN (GGPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TRACECK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#if defined(CONFIG_STM32_TRACESWO_REMAP)
|
||||
# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPU|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART2_REMAP)
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
|
||||
/* Some GPIOs are accessible only as remapped, alternate functions */
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H */
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32f107vc_pinmap.h
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Alternate Pin Functions: */
|
||||
|
||||
#define GPIO_ADC12_IN0 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN10 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN11 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ADC12_IN12 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN13 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN14 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN15 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ADC12_IN3 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ADC12_IN4 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_ADC12_IN5 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#define GPIO_ADC12_IN6 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
#define GPIO_ADC12_IN7 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ADC12_IN8 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_ADC12_IN9 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
|
||||
#elif defined(CONFIG_STM32_CAN1_PARTIAL_REMAP)
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_CAN2_REMAP)
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
#else
|
||||
# define GPIO_CAN2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_ETH_MDC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIICOL (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIICRSWKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_ETH_MIIRXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
|
||||
#if defined(CONFIG_STM32_ETH_REMAP)
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#else
|
||||
# define GPIO_ETH_MIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
# define GPIO_ETH_MIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
# define GPIO_ETH_MIIRXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_ETH_MIIRXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_ETH_MIIRXDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_ETH_MIIRXER (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_ETH_MIITXCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_ETH_MIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_MIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_MIITXD2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_ETH_MIITXD3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_ETH_MIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_ETH_PPSOUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIICRSDV (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_ETH_RMIIREFCLK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_ETH_RMIIRXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_ETH_RMIIRXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_ETH_RMIITXD0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_ETH_RMIITXD1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_ETH_RMIITXEN (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_I2C1_REMAP)
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#else
|
||||
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#endif
|
||||
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
|
||||
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_I2S2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_I2S2_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
|
||||
#define GPIO_I2S3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_I2S3_SD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_I2S3_WS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_MCO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_OTG_FSDM (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_OTG_FSDP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_OTG_FSID (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
#define GPIO_OTG_FSSOF (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_OTG_FSVBUS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_SPI1_REMAP)
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#else
|
||||
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
|
||||
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#endif
|
||||
|
||||
#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
|
||||
#if defined(CONFIG_STM32_SPI3_REMAP)
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
#else
|
||||
# define GPIO_SPI3_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_SPI3_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_SPI3_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TAMPER_RTC (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN13)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
|
||||
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
|
||||
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
|
||||
#else
|
||||
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
|
||||
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#else
|
||||
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
|
||||
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
|
||||
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
|
||||
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
|
||||
#endif
|
||||
#define GPIO_TIM3_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
|
||||
#if defined(CONFIG_STM32_TIM4_REMAP)
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#else
|
||||
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
|
||||
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
|
||||
#endif
|
||||
#define GPIO_TIM4_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN0)
|
||||
|
||||
#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TIM5_CH4IN (GGPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_TRACECK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_TRACED0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_TRACED1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_TRACED2 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_TRACED3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#if defined(CONFIG_STM32_TRACESWO_REMAP)
|
||||
# define GPIO_TRACESWO (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define GPIO_USART1_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPU|GPIO_PORTA|GPIO_PIN11)
|
||||
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
|
||||
#define GPIO_USART1_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
|
||||
#if defined(CONFIG_STM32_USART1_REMAP)
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#else
|
||||
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART2_REMAP)
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#else
|
||||
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
|
||||
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
|
||||
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
|
||||
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#else
|
||||
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
|
||||
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
|
||||
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
|
||||
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
|
||||
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
|
||||
#endif
|
||||
|
||||
#define GPIO_UART4_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_UART4_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
|
||||
|
||||
#define GPIO_UART5_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_UART5_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
|
||||
|
||||
#define GPIO_WKUP (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
|
||||
|
||||
/* Some GPIOs are accessible only as remapped, alternate functions */
|
||||
|
||||
#if 0 /* Needs further investigation */
|
||||
#define GPIO_PA13 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN13)
|
||||
#define GPIO_PA14 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN14)
|
||||
#define GPIO_PA15 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_PB3 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_PB4 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32F107VC_PINMAP_H */
|
||||
|
||||
@ -43,6 +43,7 @@ AOBJS = $(ASRCS:.S=$(OBJEXT))
|
||||
CSRCS = up_boot.c up_leds.c up_buttons.c up_spi.c up_usbdev.c \
|
||||
up_extcontext.c up_selectnor.c up_deselectnor.c \
|
||||
up_selectsram.c up_deselectsram.c
|
||||
|
||||
ifeq ($(CONFIG_NSH_ARCHINIT),y)
|
||||
CSRCS += up_nsh.c
|
||||
endif
|
||||
|
||||
@ -45,7 +45,7 @@
|
||||
#include <debug.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32.h"
|
||||
#include "stm3210e-internal.h"
|
||||
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* configs/stm3210e-eval/src/up_selectnor.c
|
||||
* arch/arm/src/board/up_selectnor.c
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -46,9 +46,7 @@
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_fsmc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_internal.h"
|
||||
#include "stm32.h"
|
||||
#include "stm3210e-internal.h"
|
||||
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
* configs/stm3210e-eval/src/up_selectsram.c
|
||||
* arch/arm/src/board/up_selectsram.c
|
||||
*
|
||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -46,9 +46,7 @@
|
||||
#include "chip.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_fsmc.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_internal.h"
|
||||
#include "stm32.h"
|
||||
#include "stm3210e-internal.h"
|
||||
|
||||
#ifdef CONFIG_STM32_FSMC
|
||||
|
||||
Loading…
Reference in New Issue
Block a user