Minor update to some comments
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@ -86,20 +86,20 @@
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*
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* Fpllclock = = (Fclkin / NR) x NF / OD / R
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*
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* For example, if the clock source is a 16MHz crystal, then
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* In this case, we have:
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*
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* Fclkin = 16,000,000
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* NR = 6 (REFCLKDIV=5)
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* NF = 120 (PLLMUL = 119 * 256)
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* OD = 1 (ODPLL = 0)
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* R = 32 (PLLDIV=31)
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* R = 2 (PLLDIV=1)
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*
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* Then:
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*
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* Fintclk = 16 MHz / 6 = 2.667 MHz
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* Fintclk = 16 MHz / 6 = 2.667 MHz
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* Foutputclock = 2.667 MHz * 120 = 320 MHz
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* Fpostodclock = 320 MHz / 2 = 160 MHz
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* Fpllclock = 160 MHz / 2 = 8 MHz
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* Fpostodclock = 320 MHz / 2 = 160 MHz
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* Fpllclock = 160 MHz / 2 = 80 MHz
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*/
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#define BOARD_PLL_NR 6 /* REFCLKDIV = 5 */
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