From 2bdb7c0e8d233525140e2fb7389eab401a105690 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Tue, 17 Jan 2023 18:43:50 -0300 Subject: [PATCH] esp32s2: Add support to EFUSE --- arch/xtensa/src/esp32s2/Kconfig | 6 + arch/xtensa/src/esp32s2/Make.defs | 6 + arch/xtensa/src/esp32s2/esp32s2_efuse.c | 712 +++++++++ arch/xtensa/src/esp32s2/esp32s2_efuse.h | 189 +++ .../src/esp32s2/esp32s2_efuse_lowerhalf.c | 241 +++ arch/xtensa/src/esp32s2/esp32s2_efuse_table.c | 1347 +++++++++++++++++ 6 files changed, 2501 insertions(+) create mode 100644 arch/xtensa/src/esp32s2/esp32s2_efuse.c create mode 100644 arch/xtensa/src/esp32s2/esp32s2_efuse.h create mode 100644 arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c create mode 100644 arch/xtensa/src/esp32s2/esp32s2_efuse_table.c diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index cf7069d09b..166ed14f81 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -354,6 +354,12 @@ config ESP32S2_SPIRAM bool "SPI RAM Support" default n +config ESP32S2_EFUSE + bool "EFUSE support" + default n + ---help--- + Enable ESP32-S2 efuse support. + config ESP32S2_TIMER0 bool "64-bit Timer 0 (Group 0 Timer 0)" default n diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs index 171c38d098..4b8927cdda 100644 --- a/arch/xtensa/src/esp32s2/Make.defs +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -42,6 +42,12 @@ ifeq ($(CONFIG_ESP32S2_UART),y) CHIP_CSRCS += esp32s2_serial.c endif +ifeq ($(CONFIG_ESP32S2_EFUSE),y) +CHIP_CSRCS += esp32s2_efuse.c +CHIP_CSRCS += esp32s2_efuse_table.c +CHIP_CSRCS += esp32s2_efuse_lowerhalf.c +endif + ifeq ($(CONFIG_ESP32S2_RNG),y) CHIP_CSRCS += esp32s2_rng.c endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse.c b/arch/xtensa/src/esp32s2/esp32s2_efuse.c new file mode 100644 index 0000000000..10b547cddd --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_efuse.c @@ -0,0 +1,712 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_efuse.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" +#include "hardware/esp32s2_soc.h" +#include "hardware/esp32s2_efuse.h" + +#include "esp32s2_clockconfig.h" +#include "esp32s2_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_CONF_WRITE 0x5a5a /* eFuse_pgm_op_ena, force no rd/wr dis. */ +#define EFUSE_CONF_READ 0x5aa5 /* eFuse_read_op_ena, release force. */ +#define EFUSE_CMD_PGM 0x02 /* Command to program. */ +#define EFUSE_CMD_READ 0x01 /* Command to read. */ +#define EFUSE_MAX_BLK_LEN 256 /* Max length of efuse block. */ + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_start_efuse_rdreg[] = +{ + EFUSE_RD_WR_DIS_REG, + EFUSE_RD_MAC_SPI_SYS_0_REG, + EFUSE_RD_SYS_DATA_PART1_0_REG, + EFUSE_RD_USR_DATA0_REG, + EFUSE_RD_KEY0_DATA0_REG, + EFUSE_RD_KEY1_DATA0_REG, + EFUSE_RD_KEY2_DATA0_REG, + EFUSE_RD_KEY3_DATA0_REG, + EFUSE_RD_KEY4_DATA0_REG, + EFUSE_RD_KEY5_DATA0_REG, + EFUSE_RD_SYS_DATA_PART2_0_REG +}; + +static uint32_t g_start_efuse_wrreg[] = +{ + EFUSE_PGM_DATA0_REG, + EFUSE_PGM_CHECK_VALUE0_REG +}; + +/**************************************************************************** + * Private Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_efuse_set_timing + * + * Description: + * Modify both EFUSE_CLK_REG and EFUSE_DAC_CONF_REG + * for match ABP frequency in Hertz. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_set_timing(void) +{ + uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; + uint32_t clk_sel0; + uint32_t clk_sel1; + uint32_t dac_clk_div; + + if (apb_freq_mhz <= 26) + { + clk_sel0 = 250; + clk_sel1 = 255; + dac_clk_div = 52; + } + else + { + if (apb_freq_mhz <= 40) + { + clk_sel0 = 160; + clk_sel1 = 255; + dac_clk_div = 80; + } + else + { + clk_sel0 = 80; + clk_sel1 = 128; + dac_clk_div = 100; + } + } + + modifyreg32(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, dac_clk_div); + modifyreg32(EFUSE_CLK_REG, EFUSE_DAC_CLK_DIV, clk_sel0); + modifyreg32(EFUSE_CLK_REG, EFUSE_DAC_CLK_DIV, clk_sel1); + return OK; +} + +/**************************************************************************** + * Name: esp32s2_efuse_get_mask + * + * Description: + * Return mask with required the number of ones with shift. + * + * Input Parameters: + * bit_count - The number of bits required + * shift - The shift of programmed as, '1' or '0' + * + * Returned Value: + * The mask with required the number of ones with shift. + * + ****************************************************************************/ + +static uint32_t esp32s2_efuse_get_mask(uint32_t bit_count, uint32_t shift) +{ + uint32_t mask; + + if (bit_count != 32) + { + mask = (1 << bit_count) - 1; + } + else + { + mask = 0xffffffff; + } + + return mask << shift; +} + +/**************************************************************************** + * Name: esp32s2_efuse_get_reg_num + * + * Description: + * Returns the number of bits in the register. + * + * Input Parameters: + * bit_offset - Start bit in block + * bit_count - The number of bits required + * i_reg - The register number in the block + * + * Returned Value: + * The register number in the array. + * + ****************************************************************************/ + +static int esp32s2_efuse_get_reg_num(int bit_offset, + int bit_count, int i_reg) +{ + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + int num_reg = i_reg + bit_start / 32; + + if (num_reg > (bit_start + bit_count - 1) / 32) + { + return -1; + } + + return num_reg; +} + +/**************************************************************************** + * Name: esp32s2_efuse_get_count_bits_in_reg + * + * Description: + * Returns the number of bits in the register. + * + * Input Parameters: + * bit_offset - Start bit in block + * bit_count - The number of bits required + * i_reg - The register number in the block + * + * Returned Value: + * The number of bits in the register. + * + ****************************************************************************/ + +static int esp32s2_efuse_get_count_bits_in_reg(int bit_offset, + int bit_count, int i_reg) +{ + int ret_count = 0; + int num_reg = 0; + int bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + int last_used_bit = (bit_start + bit_count - 1); + + for (int num_bit = bit_start; num_bit <= last_used_bit; ++num_bit) + { + ++ret_count; + if ((((num_bit + 1) % 32) == 0) || (num_bit == last_used_bit)) + { + if (i_reg == num_reg) + { + return ret_count; + } + + ++num_reg; + ret_count = 0; + } + } + + return 0; +} + +/**************************************************************************** + * Name: esp32s2_efuse_get_field_size + * + * Description: + * Get the length of the field in bits. + * + * Input Parameters: + * field - Pointer to the structure describing the efuse field + * + * Returned Value: + * The length of the field in bits. + * + ****************************************************************************/ + +static int esp32s2_efuse_get_field_size(const efuse_desc_t *field[]) +{ + int bits_counter = 0; + + if (field != NULL) + { + int i = 0; + + while (field[i] != NULL) + { + bits_counter += field[i]->bit_count; + ++i; + } + } + + return bits_counter; +} + +/**************************************************************************** + * Name: esp32s2_efuse_check_range_of_bits + * + * Description: + * Check range of bits for any coding scheme. + * + * Input Parameters: + * offset_in_bits - The bit offset related to beginning of efuse + * size_bits - The length of bit field + * + * Returned Value: + * True is returned if the bits offset matched. Otherwise false. + * + ****************************************************************************/ + +static bool esp32s2_efuse_check_range_of_bits(int offset_in_bits, + int size_bits) +{ + int blk_offset = offset_in_bits % EFUSE_MAX_BLK_LEN; + int max_num_bit = blk_offset + size_bits; + + if (max_num_bit > EFUSE_MAX_BLK_LEN) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: esp32s2_efuse_get_number_of_items + * + * Description: + * Returns the number of array elements for placing these bits in an array + * with the length of each element equal to size_of_base. + * + * Input Parameters: + * bits - The number of bits required + * size_of_base - The base of bits required + * + * Returned Value: + * The number of array elements. + * + ****************************************************************************/ + +static int esp32s2_efuse_get_number_of_items(int bits, int size_of_base) +{ + return bits / size_of_base + (bits % size_of_base > 0 ? 1 : 0); +} + +/**************************************************************************** + * Name: esp32s2_efuse_fill_reg + * + * Description: + * Fill efuse register from array. + * + * Input Parameters: + * bit_start_in_reg - Start bit in block + * bit_count_in_reg - The number of bits required to write + * blob - A pointer that will contain the value + * filled_bits_blob - A pointer that will contain the bits counter + * + * Returned Value: + * The value to write efuse register. + * + ****************************************************************************/ + +static uint32_t esp32s2_efuse_fill_reg(int bit_start_in_reg, + int bit_count_in_reg, + uint8_t *blob, int *filled_bits_blob) +{ + uint32_t reg_to_write = 0; + uint32_t temp_blob_32; + int shift_reg; + int shift_bit = (*filled_bits_blob) % 8; + + if (shift_bit != 0) + { + temp_blob_32 = blob[(*filled_bits_blob) / 8] >> shift_bit; + shift_bit = MIN((8 - shift_bit), bit_count_in_reg); + + reg_to_write = temp_blob_32 & esp32s2_efuse_get_mask(shift_bit, 0); + (*filled_bits_blob) += shift_bit; + bit_count_in_reg -= shift_bit; + } + + shift_reg = shift_bit; + + while (bit_count_in_reg > 0) + { + temp_blob_32 = blob[(*filled_bits_blob) / 8]; + shift_bit = MIN(bit_count_in_reg, 8); + reg_to_write |= (temp_blob_32 & \ + esp32s2_efuse_get_mask(shift_bit, 0)) << shift_reg; + (*filled_bits_blob) += shift_bit; + bit_count_in_reg -= shift_bit; + shift_reg += 8; + }; + + return reg_to_write << bit_start_in_reg; +} + +/**************************************************************************** + * Name: esp32s2_efuse_process + * + * Description: + * Processes the field by calling the passed function. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * ptr - A pointer to array that will contain the result + * ptr_size_bits - The number of bits required to read + * func_proc - A callback for handle the efuse field register + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_process(const efuse_desc_t *field[], void *ptr, + size_t ptr_size_bits, + efuse_func_proc_t func_proc) +{ + int err = OK; + int bits_counter = 0; + int field_len; + int req_size; + int i = 0; + + /* get and check size */ + + field_len = esp32s2_efuse_get_field_size(field); + req_size = (ptr_size_bits == 0) ? field_len : \ + MIN(ptr_size_bits, field_len); + + while (err == OK && req_size > bits_counter && field[i] != NULL) + { + int i_reg = 0; + int num_reg; + + if (esp32s2_efuse_check_range_of_bits(field[i]->bit_offset, + field[i]->bit_count) == false) + { + minfo("Range of data does not match the coding scheme"); + err = -EINVAL; + } + + while (err == OK && req_size > bits_counter && + (num_reg = esp32s2_efuse_get_reg_num(field[i]->bit_offset, + field[i]->bit_count, i_reg)) != -1) + { + int num_bits = esp32s2_efuse_get_count_bits_in_reg( + field[i]->bit_offset, + field[i]->bit_count, + i_reg); + int bit_offset = field[i]->bit_offset; + + if ((bits_counter + num_bits) > req_size) + { + /* Limits the length of the field */ + + num_bits = req_size - bits_counter; + } + + err = func_proc(num_reg, bit_offset, num_bits, ptr, &bits_counter); + ++i_reg; + } + + i++; + } + + DEBUGASSERT(bits_counter <= req_size); + return err; +} + +/**************************************************************************** + * Name: esp32s2_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp32s2_efuse_write_reg(uint32_t blk, uint32_t num_reg, + uint32_t value) +{ + uint32_t addr_wr_reg; + uint32_t reg_to_write; + uint32_t blk_start = g_start_efuse_wrreg[blk]; + + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + + DEBUGASSERT(num_reg <= 7); + + /* The block 0 and register 7 doesn't exist */ + + if (blk == 0 && num_reg == 7) + { + merr("Block 0 Register 7 doesn't exist!\n"); + return; + } + + addr_wr_reg = blk_start + num_reg * 4; + reg_to_write = getreg32(addr_wr_reg) | value; + + /* The register can be written in parts so we combine the new value + * with the one already available. + */ + + putreg32(reg_to_write, addr_wr_reg); +} + +/**************************************************************************** + * Name: esp32s2_efuse_write_blob + * + * Description: + * Fill registers from array for writing. + * + * Input Parameters: + * num_reg - The register number in the block + * bit_offset - Start bit in block + * bit_count - The number of bits required to read + * arr_in - A pointer to array that will contain the value of writing + * bits_counter - A pointer that will contain the bits counter of writing + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_write_blob(uint32_t num_reg, int bit_offset, + int bit_count, void *arr_in, + int *bits_counter) +{ + uint32_t block = (bit_offset / EFUSE_MAX_BLK_LEN); + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + uint32_t reg_to_write = esp32s2_efuse_fill_reg(bit_start, bit_count, + (uint8_t *) arr_in, + bits_counter); + + esp32s2_efuse_write_reg(block, num_reg, reg_to_write); + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +static uint32_t esp32s2_efuse_read_reg(uint32_t blk, uint32_t num_reg) +{ + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + uint32_t value; + uint32_t blk_start = g_start_efuse_rdreg[blk]; + + DEBUGASSERT(num_reg <= 7); + + value = getreg32(blk_start + num_reg * 4); + return value; +} + +/**************************************************************************** + * Name: esp32s2_efuse_fill_buff + * + * Description: + * Read efuse register and write this value to array. + * + * Input Parameters: + * num_reg - The register number in the block + * bit_offset - Start bit in block + * bit_count - The number of bits required to read + * arr_out - A pointer to array that will contain the result + * bits_counter - A pointer that will contain the bits counter of reading + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_fill_buff(uint32_t num_reg, int bit_offset, + int bit_count, void *arr_out, + int *bits_counter) +{ + uint8_t *blob = (uint8_t *) arr_out; + uint32_t efuse_block = (bit_offset / EFUSE_MAX_BLK_LEN); + uint32_t bit_start = (bit_offset % EFUSE_MAX_BLK_LEN); + uint32_t reg = esp32s2_efuse_read_reg(efuse_block, num_reg); + uint64_t reg_of_aligned_bits = (reg >> bit_start) & \ + esp32s2_efuse_get_mask(bit_count, 0); + int sum_shift = 0; + int shift_bit = (*bits_counter) % 8; + + if (shift_bit != 0) + { + blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits << \ + shift_bit); + shift_bit = ((8 - shift_bit) < bit_count) ? (8 - shift_bit) : \ + bit_count; + (*bits_counter) += shift_bit; + bit_count -= shift_bit; + } + + while (bit_count > 0) + { + sum_shift += shift_bit; + blob[(*bits_counter) / 8] |= (uint8_t)(reg_of_aligned_bits >> \ + sum_shift); + shift_bit = (bit_count > 8) ? 8 : bit_count; + (*bits_counter) += shift_bit; + bit_count -= shift_bit; + }; + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_efuse_read_field + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * dst_size_bits - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_read_field(const efuse_desc_t *field[], void *dst, + size_t dst_size_bits) +{ + int err = OK; + + if (field == NULL || dst == NULL || dst_size_bits == 0) + { + err = -EINVAL; + } + else + { + memset((uint8_t *)dst, 0, + esp32s2_efuse_get_number_of_items(dst_size_bits, 8)); + + err = esp32s2_efuse_process(field, dst, dst_size_bits, + esp32s2_efuse_fill_buff); + } + + return err; +} + +/**************************************************************************** + * Name: esp32s2_efuse_write_field + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * src - A pointer to array that contains the data for writing + * src_size_bits - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_write_field(const efuse_desc_t *field[], + const void *src, size_t src_size_bits) +{ + int err = OK; + + if (field == NULL || src == NULL || src_size_bits == 0) + { + err = -EINVAL; + } + else + { + err = esp32s2_efuse_process(field, (void *)src, src_size_bits, + esp32s2_efuse_write_blob); + } + + return err; +} + +/**************************************************************************** + * Name: esp32s2_efuse_burn_efuses + * + * Description: + * Burn values written to the efuse write registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s2_efuse_burn_efuses(void) +{ + esp32s2_efuse_set_timing(); + + /* Permanently update values written to the efuse write registers */ + + putreg32(EFUSE_CONF_WRITE, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_PGM, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; + + putreg32(EFUSE_CONF_READ, EFUSE_CONF_REG); + putreg32(EFUSE_CMD_READ, EFUSE_CMD_REG); + + while (getreg32(EFUSE_CMD_REG) != 0) + { + }; +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse.h b/arch/xtensa/src/esp32s2/esp32s2_efuse.h new file mode 100644 index 0000000000..2c927608ac --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_efuse.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Type of eFuse blocks for ESP32S2 */ + +typedef enum +{ + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA */ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA */ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/**************************************************************************** + * Name: efuse_func_proc_t + * + * Description: + * This is type of function that will handle the efuse field register. + * + * Input Parameters: + * num_reg - The register number in the block. + * bit_start - Start bit in the register. + * bit_count - The number of bits used in the register. + * arr - A pointer to an array or variable. + * bits_counter - Counter bits. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +typedef int (*efuse_func_proc_t) (uint32_t num_reg, + int bit_start, + int bit_count, + void *arr, int *bits_counter); + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_efuse_read_field + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * dst_size_bits - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_read_field(const efuse_desc_t *field[], void *dst, + size_t dst_size_bits); + +/**************************************************************************** + * Name: esp32s2_efuse_write_field + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * src - A pointer to array that contains the data for writing + * src_size_bits - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_write_field(const efuse_desc_t *field[], + const void *src, size_t src_size_bits); + +/**************************************************************************** + * Name: esp32s2_efuse_burn_efuses + * + * Description: + * Burn values written to the efuse write registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s2_efuse_burn_efuses(void); + +/**************************************************************************** + * Name: esp32s2_efuse_initialize + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the efuse device. + * This should be of the form /dev/efuse + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_initialize(const char *devpath); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c new file mode 100644 index 0000000000..fb76d0106a --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "hardware/esp32s2_soc.h" +#include "esp32s2_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +struct esp32s2_efuse_lowerhalf_s +{ + const struct efuse_ops_s *ops; /* Lower half operations */ + void *upper; /* Pointer to efuse_upperhalf_s */ +}; + +/**************************************************************************** + * Private Functions Prototypes + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static int esp32s2_efuse_lowerhalf_read(struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + uint8_t *data, size_t bits_len); +static int esp32s2_efuse_lowerhalf_write(struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + const uint8_t *data, + size_t bits_len); +static int esp32s2_efuse_lowerhalf_ioctl(struct efuse_lowerhalf_s *lower, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* "Lower half" driver methods */ + +static const struct efuse_ops_s g_esp32s2_efuse_ops = +{ + .read_field = esp32s2_efuse_lowerhalf_read, + .write_field = esp32s2_efuse_lowerhalf_write, + .ioctl = esp32s2_efuse_lowerhalf_ioctl, +}; + +/* EFUSE lower-half */ + +static struct esp32s2_efuse_lowerhalf_s g_esp32s2_efuse_lowerhalf = +{ + .ops = &g_esp32s2_efuse_ops, + .upper = NULL, +}; + +/**************************************************************************** + * Private functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_efuse_lowerhalf_read + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * bits_len - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_lowerhalf_read(struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + uint8_t *data, size_t bits_len) +{ + int ret = OK; + + /* Read the requested field */ + + ret = esp32s2_efuse_read_field(field, data, bits_len); + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_efuse_lowerhalf_write + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * field - A pointer to describing the fields of efuse + * data - A pointer to array that contains the data for writing + * bits_len - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_lowerhalf_write(struct efuse_lowerhalf_s *lower, + const efuse_desc_t *field[], + const uint8_t *data, + size_t bits_len) +{ + irqstate_t flags; + int ret = OK; + + flags = enter_critical_section(); + + /* Write the blob data to the field */ + + ret = esp32s2_efuse_write_field(field, data, bits_len); + + /* Burn the EFUSEs */ + + esp32s2_efuse_burn_efuses(); + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_efuse_lowerhalf_ioctl + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of + * the "lower-half" driver state structure + * cmd - The ioctl command value + * arg - The optional argument that accompanies the 'cmd' + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +static int esp32s2_efuse_lowerhalf_ioctl(struct efuse_lowerhalf_s *lower, + int cmd, unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + /* We don't have proprietary EFUSE ioctls */ + + default: + { + minfo("Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + } + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_efuse_initialize + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the efuse device. + * This should be of the form /dev/efuse + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s2_efuse_initialize(const char *devpath) +{ + struct esp32s2_efuse_lowerhalf_s *lower = NULL; + int ret = OK; + + DEBUGASSERT(devpath != NULL); + + lower = &g_esp32s2_efuse_lowerhalf; + + /* Register the efuse upper driver */ + + lower->upper = efuse_register(devpath, + (struct efuse_lowerhalf_s *)lower); + + if (lower->upper == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the efuser driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + ret = -EEXIST; + } + + return ret; +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c b/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c new file mode 100644 index 0000000000..45bfcb39f5 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_efuse_table.c @@ -0,0 +1,1347 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_efuse_table.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include "esp32s2_efuse.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +static const efuse_desc_t WR_DIS[] = +{ + { + 0, 32 /* Write protection */ + }, +}; + +static const efuse_desc_t WR_DIS_RD_DIS[] = +{ + { + 0, 1 /* Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_1[] = +{ + { + 2, 1 /* Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_2[] = +{ + { + 3, 1 /* Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL, */ + }, +}; + +static const efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = +{ + { + 4, 1 /* Write protection for SPI_BOOT_CRYPT_CNT, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = +{ + { + 5, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE0, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = +{ + { + 6, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE1, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = +{ + { + 7, 1 /* Write protection for SECURE_BOOT_KEY_REVOKE2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY0_PURPOSE[] = +{ + { + 8, 1 /* Write protection for key_purpose. KEY0, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY1_PURPOSE[] = +{ + { + 9, 1 /* Write protection for key_purpose. KEY1, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY2_PURPOSE[] = +{ + { + 10, 1 /* Write protection for key_purpose. KEY2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY3_PURPOSE[] = +{ + { + 11, 1 /* Write protection for key_purpose. KEY3, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY4_PURPOSE[] = +{ + { + 12, 1 /* Write protection for key_purpose. KEY4, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY5_PURPOSE[] = +{ + { + 13, 1 /* Write protection for key_purpose. KEY5, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = +{ + { + 15, 1 /* Write protection for SECURE_BOOT_EN, */ + }, +}; + +static const efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + { + 16, 1 /* Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, */ + }, +}; + +static const efuse_desc_t WR_DIS_GROUP_3[] = +{ + { + 18, 1 /* Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, */ + }, +}; + +static const efuse_desc_t WR_DIS_BLK1[] = +{ + { + 20, 1 /* Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, */ + }, +}; + +static const efuse_desc_t WR_DIS_SYS_DATA_PART1[] = +{ + { + 21, 1 /* Write protection for EFUSE_BLK2. SYS_DATA_PART1, */ + }, +}; + +static const efuse_desc_t WR_DIS_USER_DATA[] = +{ + { + 22, 1 /* Write protection for EFUSE_BLK3. USER_DATA, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY0[] = +{ + { + 23, 1 /* Write protection for EFUSE_BLK4. KEY0, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY1[] = +{ + { + 24, 1 /* Write protection for EFUSE_BLK5. KEY1, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY2[] = +{ + { + 25, 1 /* Write protection for EFUSE_BLK6. KEY2, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY3[] = +{ + { + 26, 1 /* Write protection for EFUSE_BLK7. KEY3, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY4[] = +{ + { + 27, 1 /* Write protection for EFUSE_BLK8. KEY4, */ + }, +}; + +static const efuse_desc_t WR_DIS_KEY5[] = +{ + { + 28, 1 /* Write protection for EFUSE_BLK9. KEY5, */ + }, +}; + +static const efuse_desc_t WR_DIS_SYS_DATA_PART2[] = +{ + { + 29, 1 /* Write protection for EFUSE_BLK10. SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = +{ + { + 30, 1 /* Write protection for USB_EXCHG_PINS, */ + }, +}; + +static const efuse_desc_t RD_DIS[] = +{ + { + 32, 7 /* Read protection */ + }, +}; + +static const efuse_desc_t RDWR_DIS_SYS_DATA_PART2_DIS_KEY0[] = +{ + { + 32, 1 /* Read protection for EFUSE_BLK4. KEY0, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY1[] = +{ + { + 33, 1 /* Read protection for EFUSE_BLK5. KEY1, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY2[] = +{ + { + 34, 1 /* Read protection for EFUSE_BLK6. KEY2, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY3[] = +{ + { + 35, 1 /* Read protection for EFUSE_BLK7. KEY3, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY4[] = +{ + { + 36, 1 /* Read protection for EFUSE_BLK8. KEY4, */ + }, +}; + +static const efuse_desc_t RD_DIS_KEY5[] = +{ + { + 37, 1 /* Read protection for EFUSE_BLK9. KEY5, */ + }, +}; + +static const efuse_desc_t RD_DIS_SYS_DATA_PART2[] = +{ + { + 38, 1 /* Read protection for EFUSE_BLK10. SYS_DATA_PART2, */ + }, +}; + +static const efuse_desc_t DIS_RTC_RAM_BOOT[] = +{ + { + 39, 1 /* Disable boot from RTC RAM, */ + }, +}; + +static const efuse_desc_t DIS_ICACHE[] = +{ + { + 40, 1 /* Disable Icache, */ + }, +}; + +static const efuse_desc_t DIS_DCACHE[] = +{ + { + 41, 1 /* Disable DCACHE, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_ICACHE[] = +{ + { + 42, 1 /* Disable Icache in download mode, include boot_mode 0 1 2 3 6 7, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_DCACHE[] = +{ + { + 43, 1 /* Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, */ + }, +}; + +static const efuse_desc_t DIS_FORCE_DOWNLOAD[] = +{ + { + 44, 1 /* Disable force chip go to download mode function, */ + }, +}; + +static const efuse_desc_t DIS_USB[] = +{ + { + 45, 1 /* Disable USB function, */ + }, +}; + +static const efuse_desc_t DIS_CAN[] = +{ + { + 46, 1 /* Disable CAN function, */ + }, +}; + +static const efuse_desc_t DIS_BOOT_REMAP[] = +{ + { + 47, 1 /* Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function, */ + }, +}; + +static const efuse_desc_t SOFT_DIS_JTAG[] = +{ + { + 49, 1 /* Software disable jtag jtag can be activated again by hmac module, */ + }, +}; + +static const efuse_desc_t HARD_DIS_JTAG[] = +{ + { + 50, 1 /* Hardware disable jtag permanently disable jtag function, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = +{ + { + 51, 1 /* Disable flash encrypt function, */ + }, +}; + +static const efuse_desc_t USB_EXCHG_PINS[] = +{ + { + 56, 1 /* Exchange D+ D- pins, */ + }, +}; + +static const efuse_desc_t USB_EXT_PHY_ENABLE[] = +{ + { + 57, 1 /* Enable external PHY, */ + }, +}; + +static const efuse_desc_t BLOCK0_VERSION[] = +{ + { + 59, 2 /* BLOCK0 efuse version, */ + }, +}; + +static const efuse_desc_t VDD_SPI_XPD[] = +{ + { + 68, 1 /* VDD_SPI regulator power up, */ + }, +}; + +static const efuse_desc_t VDD_SPI_TIEH[] = +{ + { + 69, 1 /* VDD_SPI regulator tie high to vdda, */ + }, +}; + +static const efuse_desc_t VDD_SPI_FORCE[] = +{ + { + 70, 1 /* Force using eFuse configuration of VDD_SPI, */ + }, +}; + +static const efuse_desc_t WDT_DELAY_SEL[] = +{ + { + 80, 2 /* Select RTC WDT time out threshold, */ + }, +}; + +static const efuse_desc_t SPI_BOOT_CRYPT_CNT[] = +{ + { + 82, 3 /* SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = +{ + { + 85, 1 /* Enable revoke first secure boot key, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = +{ + { + 86, 1 /* Enable revoke second secure boot key, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = +{ + { + 87, 1 /* Enable revoke third secure boot key, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_0[] = +{ + { + 88, 4 /* Key0 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_1[] = +{ + { + 92, 4 /* Key1 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_2[] = +{ + { + 96, 4 /* Key2 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_3[] = +{ + { + 100, 4 /* Key3 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_4[] = +{ + { + 104, 4 /* Key4 purpose, */ + }, +}; + +static const efuse_desc_t KEY_PURPOSE_5[] = +{ + { + 108, 4 /* Key5 purpose, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_EN[] = +{ + { + 116, 1 /* Secure boot enable, */ + }, +}; + +static const efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + { + 117, 1 /* Enable aggressive secure boot revoke, */ + }, +}; + +static const efuse_desc_t FLASH_TPUW[] = +{ + { + 124, 4 /* Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, */ + }, +}; + +static const efuse_desc_t DIS_DOWNLOAD_MODE[] = +{ + { + 128, 1 /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, */ + }, +}; + +static const efuse_desc_t DIS_LEGACY_SPI_BOOT[] = +{ + { + 129, 1 /* Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, */ + }, +}; + +static const efuse_desc_t UART_PRINT_CHANNEL[] = +{ + { + 130, 1 /* 0: UART0. 1: UART1, */ + }, +}; + +static const efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = +{ + { + 132, 1 /* Disable download through USB, */ + }, +}; + +static const efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = +{ + { + 133, 1 /* Enable security download mode, */ + }, +}; + +static const efuse_desc_t UART_PRINT_CONTROL[] = +{ + { + 134, 2 /* b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print., */ + }, +}; + +static const efuse_desc_t PIN_POWER_SELECTION[] = +{ + { + 136, 1 /* GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., */ + }, +}; + +static const efuse_desc_t FLASH_TYPE[] = +{ + { + 137, 1 /* Connected Flash interface type. 0: 4 data line. 1: 8 data line, */ + }, +}; + +static const efuse_desc_t FORCE_SEND_RESUME[] = +{ + { + 138, 1 /* Force ROM code to send a resume command during SPI boot, */ + }, +}; + +static const efuse_desc_t SECURE_VERSION[] = +{ + { + 139, 16 /* Secure version for anti-rollback, */ + }, +}; + +static const efuse_desc_t MAC_FACTORY[] = +{ + { + 296, 8 /* Factory MAC addr [0], */ + }, + { + 288, 8 /* Factory MAC addr [1], */ + }, + { + 280, 8 /* Factory MAC addr [2], */ + }, + { + 272, 8 /* Factory MAC addr [3], */ + }, + { + 264, 8 /* Factory MAC addr [4], */ + }, + { + 256, 8 /* Factory MAC addr [5], */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_CLK[] = +{ + { + 304, 6 /* SPI_PAD_configure CLK, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = +{ + { + 310, 6 /* SPI_PAD_configure Q(D1), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D_D0[] = +{ + { + 316, 6 /* SPI_PAD_configure D(D0), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_CS[] = +{ + { + 322, 6 /* SPI_PAD_configure CS, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = +{ + { + 328, 6 /* SPI_PAD_configure HD(D3), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = +{ + { + 334, 6 /* SPI_PAD_configure WP(D2), */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_DQS[] = +{ + { + 340, 6 /* SPI_PAD_configure DQS, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D4[] = +{ + { + 346, 6 /* SPI_PAD_configure D4, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D5[] = +{ + { + 352, 6 /* SPI_PAD_configure D5, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D6[] = +{ + { + 358, 6 /* SPI_PAD_configure D6, */ + }, +}; + +static const efuse_desc_t SPI_PAD_CONFIG_D7[] = +{ + { + 364, 6 /* SPI_PAD_configure D7, */ + }, +}; + +static const efuse_desc_t SYS_DATA_PART1[] = +{ + { + 512, 256 /* System configuration, */ + }, +}; + +static const efuse_desc_t USER_DATA[] = +{ + { + 768, 256 /* User data, */ + }, +}; + +static const efuse_desc_t KEY0[] = +{ + { + 1024, 256 /* Key0 or user data, */ + }, +}; + +static const efuse_desc_t KEY1[] = +{ + { + 1280, 256 /* Key1 or user data, */ + }, +}; + +static const efuse_desc_t KEY2[] = +{ + { + 1536, 256 /* Key2 or user data, */ + }, +}; + +static const efuse_desc_t KEY3[] = +{ + { + 1792, 256 /* Key3 or user data, */ + }, +}; + +static const efuse_desc_t KEY4[] = +{ + { + 2048, 256 /* Key4 or user data, */ + }, +}; + +static const efuse_desc_t KEY5[] = +{ + { + 2304, 256 /* Key5 or user data, */ + }, +}; + +static const efuse_desc_t SYS_DATA_PART2[] = +{ + { + 2560, 256 /* System configuration, */ + }, +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_RD_DIS[] = +{ + &WR_DIS_RD_DIS[0], /* Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[] = +{ + &WR_DIS_DIS_RTC_RAM_BOOT[0], /* Write protection for DIS_RTC_RAM_BOOT */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_1[] = +{ + &WR_DIS_GROUP_1[0], /* Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_2[] = +{ + &WR_DIS_GROUP_2[0], /* Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = +{ + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], /* Write protection for SPI_BOOT_CRYPT_CNT */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], /* Write protection for SECURE_BOOT_KEY_REVOKE0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], /* Write protection for SECURE_BOOT_KEY_REVOKE1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = +{ + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], /* Write protection for SECURE_BOOT_KEY_REVOKE2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = +{ + &WR_DIS_KEY0_PURPOSE[0], /* Write protection for key_purpose. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = +{ + &WR_DIS_KEY1_PURPOSE[0], /* Write protection for key_purpose. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = +{ + &WR_DIS_KEY2_PURPOSE[0], /* Write protection for key_purpose. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = +{ + &WR_DIS_KEY3_PURPOSE[0], /* Write protection for key_purpose. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = +{ + &WR_DIS_KEY4_PURPOSE[0], /* Write protection for key_purpose. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = +{ + &WR_DIS_KEY5_PURPOSE[0], /* Write protection for key_purpose. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = +{ + &WR_DIS_SECURE_BOOT_EN[0], /* Write protection for SECURE_BOOT_EN */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], /* Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_GROUP_3[] = +{ + &WR_DIS_GROUP_3[0], /* Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK1[] = +{ + &WR_DIS_BLK1[0], /* Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = +{ + &WR_DIS_SYS_DATA_PART1[0], /* Write protection for EFUSE_BLK2. SYS_DATA_PART1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_USER_DATA[] = +{ + &WR_DIS_USER_DATA[0], /* Write protection for EFUSE_BLK3. USER_DATA */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY0[] = +{ + &WR_DIS_KEY0[0], /* Write protection for EFUSE_BLK4. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY1[] = +{ + &WR_DIS_KEY1[0], /* Write protection for EFUSE_BLK5. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY2[] = +{ + &WR_DIS_KEY2[0], /* Write protection for EFUSE_BLK6. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY3[] = +{ + &WR_DIS_KEY3[0], /* Write protection for EFUSE_BLK7. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY4[] = +{ + &WR_DIS_KEY4[0], /* Write protection for EFUSE_BLK8. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_KEY5[] = +{ + &WR_DIS_KEY5[0], /* Write protection for EFUSE_BLK9. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = +{ + &WR_DIS_SYS_DATA_PART2[0], /* Write protection for EFUSE_BLK10. SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = +{ + &WR_DIS_USB_EXCHG_PINS[0], /* Write protection for USB_EXCHG_PINS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS[] = +{ + &RD_DIS[0], /* Read protection */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RDWR_DIS_SYS_DATA_PART2_DIS_KEY0[] = +{ + &RDWR_DIS_SYS_DATA_PART2_DIS_KEY0[0], /* Read protection for EFUSE_BLK4. KEY0 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY1[] = +{ + &RD_DIS_KEY1[0], /* Read protection for EFUSE_BLK5. KEY1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY2[] = +{ + &RD_DIS_KEY2[0], /* Read protection for EFUSE_BLK6. KEY2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY3[] = +{ + &RD_DIS_KEY3[0], /* Read protection for EFUSE_BLK7. KEY3 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY4[] = +{ + &RD_DIS_KEY4[0], /* Read protection for EFUSE_BLK8. KEY4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_KEY5[] = +{ + &RD_DIS_KEY5[0], /* Read protection for EFUSE_BLK9. KEY5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = +{ + &RD_DIS_SYS_DATA_PART2[0], /* Read protection for EFUSE_BLK10. SYS_DATA_PART2 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_RTC_RAM_BOOT[] = +{ + &DIS_RTC_RAM_BOOT[0], /* Disable boot from RTC RAM */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_ICACHE[] = +{ + &DIS_ICACHE[0], /* Disable Icache */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DCACHE[] = +{ + &DIS_DCACHE[0], /* Disable DCACHE */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = +{ + &DIS_DOWNLOAD_ICACHE[0], /* Disable Icache in download mode */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_DCACHE[] = +{ + &DIS_DOWNLOAD_DCACHE[0], /* Disable Dcache in download mode include boot_mode 0 1 2 3 6 7, */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = +{ + &DIS_FORCE_DOWNLOAD[0], /* Disable force chip go to download mode function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB[] = +{ + &DIS_USB[0], /* Disable USB function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_CAN[] = +{ + &DIS_CAN[0], /* Disable CAN function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_BOOT_REMAP[] = +{ + &DIS_APP_CPU[0], /* Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SOFT_DIS_JTAG[] = +{ + &SOFT_DIS_JTAG[0], /* Software disable jtag jtag can be activated again by hmac module */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_HARD_DIS_JTAG[] = +{ + &HARD_DIS_JTAG[0], /* Hardware disable jtag permanently disable jtag function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = +{ + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], /* Disable flash encrypt function */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USB_EXCHG_PINS[] = +{ + &USB_EXCHG_PINS[0], /* Exchange D+ D- pins */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USB_EXT_PHY_ENABLE[] = +{ + &USB_EXT_PHY_ENABLE[0], /* Enable external PHY */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_BLOCK0_VERSION[] = +{ + &BLOCK0_VERSION[0], /* BLOCK0 efuse version */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_VDD_SPI_XPD[] = +{ + &VDD_SPI_XPD[0], /* VDD_SPI regulator power up */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_VDD_SPI_TIEH[] = +{ + &VDD_SPI_TIEH[0], /* VDD_SPI regulator tie high to vdda */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_VDD_SPI_FORCE[] = +{ + &VDD_SPI_FORCE[0], /* Force using eFuse configuration of VDD_SPI */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_WDT_DELAY_SEL[] = +{ + &WDT_DELAY_SEL[0], /* Select RTC WDT time out threshold */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = +{ + &SPI_BOOT_CRYPT_CNT[0], /* SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = +{ + &SECURE_BOOT_KEY_REVOKE0[0], /* Enable revoke first secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = +{ + &SECURE_BOOT_KEY_REVOKE1[0], /* Enable revoke second secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = +{ + &SECURE_BOOT_KEY_REVOKE2[0], /* Enable revoke third secure boot key */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_0[] = +{ + &KEY_PURPOSE_0[0], /* Key0 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_1[] = +{ + &KEY_PURPOSE_1[0], /* Key1 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_2[] = +{ + &KEY_PURPOSE_2[0], /* Key2 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_3[] = +{ + &KEY_PURPOSE_3[0], /* Key3 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_4[] = +{ + &KEY_PURPOSE_4[0], /* Key4 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY_PURPOSE_5[] = +{ + &KEY_PURPOSE_5[0], /* Key5 purpose */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_EN[] = +{ + &SECURE_BOOT_EN[0], /* Secure boot enable */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = +{ + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], /* Enable aggressive secure boot revoke */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_TPUW[] = +{ + &FLASH_TPUW[0], /* Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_DOWNLOAD_MODE[] = +{ + &DIS_DOWNLOAD_MODE[0], /* Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = +{ + &DIS_LEGACY_SPI_BOOT[0], /* Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_UART_PRINT_CHANNEL[] = +{ + &UART_PRINT_CHANNEL[0], /* 0: UART0. 1: UART1 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = +{ + &DIS_USB_DOWNLOAD_MODE[0], /* Disable download through USB */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = +{ + &ENABLE_SECURITY_DOWNLOAD[0], /* Enable security download mode */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_UART_PRINT_CONTROL[] = +{ + &UART_PRINT_CONTROL[0], /* b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_PIN_POWER_SELECTION[] = +{ + &PIN_POWER_SELECTION[0], /* GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FLASH_TYPE[] = +{ + &FLASH_TYPE[0], /* Connected Flash interface type. 0: 4 data line. 1: 8 data line */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_FORCE_SEND_RESUME[] = +{ + &FORCE_SEND_RESUME[0], /* Force ROM code to send a resume command during SPI boot */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SECURE_VERSION[] = +{ + &SECURE_VERSION[0], /* Secure version for anti-rollback */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_MAC_FACTORY[] = +{ + &MAC_FACTORY[0], /* Factory MAC addr [0] */ + &MAC_FACTORY[1], /* Factory MAC addr [1] */ + &MAC_FACTORY[2], /* Factory MAC addr [2] */ + &MAC_FACTORY[3], /* Factory MAC addr [3] */ + &MAC_FACTORY[4], /* Factory MAC addr [4] */ + &MAC_FACTORY[5], /* Factory MAC addr [5] */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = +{ + &SPI_PAD_CONFIG_CLK[0], /* SPI_PAD_configure CLK */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = +{ + &SPI_PAD_CONFIG_Q_D1[0], /* SPI_PAD_configure Q(D1) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = +{ + &SPI_PAD_CONFIG_D_D0[0], /* SPI_PAD_configure D(D0) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_CS[] = +{ + &SPI_PAD_CONFIG_CS[0], /* SPI_PAD_configure CS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = +{ + &SPI_PAD_CONFIG_HD_D3[0], /* SPI_PAD_configure HD(D3) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = +{ + &SPI_PAD_CONFIG_WP_D2[0], /* SPI_PAD_configure WP(D2) */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = +{ + &SPI_PAD_CONFIG_DQS[0], /* SPI_PAD_configure DQS */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D4[] = +{ + &SPI_PAD_CONFIG_D4[0], /* SPI_PAD_configure D4 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D5[] = +{ + &SPI_PAD_CONFIG_D5[0], /* SPI_PAD_configure D5 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D6[] = +{ + &SPI_PAD_CONFIG_D6[0], /* SPI_PAD_configure D6 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SPI_PAD_CONFIG_D7[] = +{ + &SPI_PAD_CONFIG_D7[0], /* SPI_PAD_configure D7 */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART1[] = +{ + &SYS_DATA_PART1[0], /* System configuration */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_USER_DATA[] = +{ + &USER_DATA[0], /* User data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY0[] = +{ + &KEY0[0], /* Key0 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY1[] = +{ + &KEY1[0], /* Key1 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY2[] = +{ + &KEY2[0], /* Key2 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY3[] = +{ + &KEY3[0], /* Key3 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY4[] = +{ + &KEY4[0], /* Key4 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_KEY5[] = +{ + &KEY5[0], /* Key5 or user data */ + NULL +}; + +const efuse_desc_t *ESP_EFUSE_SYS_DATA_PART2[] = +{ + &SYS_DATA_PART2[0], /* System configuration */ + NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/