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stm32l4 ADC: on 47x/48x parts, the ACSR register needs to be configured for ADC inputs to work

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This commit is contained in:
Matias Nitsche 2020-06-08 16:04:49 -03:00 committed by Abdelatif Guettouche
parent 9786e3a1a8
commit 2bdc0c5bc8
2 changed files with 43 additions and 0 deletions
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24
arch/arm/src/stm32l4/hardware/stm32l4_gpio.h
View File

@ -59,6 +59,8 @@
#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */
/* Register Addresses ***************************************************************/
@ -73,6 +75,8 @@
# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 1
@ -86,6 +90,8 @@
# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 2
@ -99,6 +105,8 @@
# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 3
@ -112,6 +120,8 @@
# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 4
@ -125,6 +135,8 @@
# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 5
@ -138,6 +150,8 @@
# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 6
@ -151,6 +165,8 @@
# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 7
@ -164,6 +180,8 @@
# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
#if STM32L4_NPORTS > 8
@ -177,6 +195,8 @@
# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET)
# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
@ -371,4 +391,8 @@
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
/* GPIO port analog switch control register */
#define GPIO_ASCR(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H */

19
arch/arm/src/stm32l4/stm32l4_gpio.c
View File

@ -334,6 +334,25 @@ int stm32l4_configgpio(uint32_t cfgset)
putreg32(regval, regaddr);
}
/* On STM32L47x/STM32L48x parts, the ACSR register also needs to be set
* (RM0351 Rev 7, p521)
*/
#if defined(CONFIG_STM32L4_STM32L471XX) || \
defined(CONFIG_STM32L4_STM32L475XX) || \
defined(CONFIG_STM32L4_STM32L476XX) || \
defined(CONFIG_STM32L4_STM32L486XX)
if (pinmode == GPIO_MODER_ANALOG)
{
modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin));
}
else
{
modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0);
}
#endif
leave_critical_section(flags);
return OK;
}