STM32F7: Bring over a couple more Cortex-M7 files from SAMV7
This commit is contained in:
Gregory Nutt
parent
be16a06857
commit
2bdca23c92
@ -107,4 +107,4 @@ endif
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# Required STM32F7 files
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CHIP_ASRCS =
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CHIP_CSRCS =
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CHIP_CSRCS = stm32_irq.c stm32_start.c stm32_timerisr.c
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292
arch/arm/src/stm32f7/stm32_config.h
Normal file
292
arch/arm/src/stm32f7/stm32_config.h
Normal file
@ -0,0 +1,292 @@
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/****************************************************************************
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* arch/arm/src/stm32f7/stm32_config.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H
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#define __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/chip/chip.h>
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* GPIO IRQs ****************************************************************/
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#ifndef CONFIG_STM32F7_GPIO_IRQ
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# undef CONFIG_STM32F7_GPIOA_IRQ
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# undef CONFIG_STM32F7_GPIOB_IRQ
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# undef CONFIG_STM32F7_GPIOC_IRQ
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# undef CONFIG_STM32F7_GPIOD_IRQ
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# undef CONFIG_STM32F7_GPIOE_IRQ
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#endif
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#if STM32F7_NPORTS < 1
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# undef CONFIG_STM32F7_GPIOA_IRQ
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#endif
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#if STM32F7_NPORTS < 2
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# undef CONFIG_STM32F7_GPIOB_IRQ
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#endif
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#if STM32F7_NPORTS < 3
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# undef CONFIG_STM32F7_GPIOC_IRQ
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#endif
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#if STM32F7_NPORTS < 4
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# undef CONFIG_STM32F7_GPIOD_IRQ
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#endif
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#if STM32F7_NPORTS < 5
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# undef CONFIG_STM32F7_GPIOE_IRQ
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#endif
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/* UARTs ********************************************************************/
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/* Don't enable UARTs not supported by the chip. */
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#if STM32F7_NUART < 1
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# undef CONFIG_STM32F7_UART0
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# undef CONFIG_STM32F7_UART1
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# undef CONFIG_STM32F7_UART2
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# undef CONFIG_STM32F7_UART3
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# undef CONFIG_STM32F7_UART4
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#elif STM32F7_NUART < 2
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# undef CONFIG_STM32F7_UART1
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# undef CONFIG_STM32F7_UART2
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# undef CONFIG_STM32F7_UART3
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# undef CONFIG_STM32F7_UART4
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#elif STM32F7_NUART < 3
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# undef CONFIG_STM32F7_UART2
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# undef CONFIG_STM32F7_UART3
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# undef CONFIG_STM32F7_UART4
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#elif STM32F7_NUART < 4
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# undef CONFIG_STM32F7_UART3
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# undef CONFIG_STM32F7_UART4
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#elif STM32F7_NUART < 5
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# undef CONFIG_STM32F7_UART4
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#endif
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/* Are any UARTs enabled? */
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#undef HAVE_UART_DEVICE
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#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \
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defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \
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defined(CONFIG_STM32F7_UART4)
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# define HAVE_UART_DEVICE 1
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#endif
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/* USARTs *******************************************************************/
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/* If the USART is not being used as a UART, then it really isn't enabled
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* for our purposes.
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*/
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#ifndef CONFIG_USART0_ISUART
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# undef CONFIG_STM32F7_USART0
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#endif
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#ifndef CONFIG_USART1_ISUART
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# undef CONFIG_STM32F7_USART1
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#endif
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#ifndef CONFIG_USART2_ISUART
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# undef CONFIG_STM32F7_USART2
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#endif
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/* Don't enable USARTs not supported by the chip. */
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#if STM32F7_NUSART < 1
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# undef CONFIG_STM32F7_USART0
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# undef CONFIG_STM32F7_USART1
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# undef CONFIG_STM32F7_USART2
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#elif STM32F7_NUSART < 2
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# undef CONFIG_STM32F7_USART1
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# undef CONFIG_STM32F7_USART2
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#elif STM32F7_NUSART < 3
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# undef CONFIG_STM32F7_USART2
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#endif
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/* Are any USARTs enabled? */
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#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \
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defined(CONFIG_STM32F7_USART2)
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# undef HAVE_UART_DEVICE
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# define HAVE_UART_DEVICE 1
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#endif
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/* UART Flow Control ********************************************************/
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/* UARTs do not support flow control */
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#undef CONFIG_UART0_IFLOWCONTROL
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#undef CONFIG_UART1_IFLOWCONTROL
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#undef CONFIG_UART2_IFLOWCONTROL
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#undef CONFIG_UART3_IFLOWCONTROL
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#undef CONFIG_UART4_IFLOWCONTROL
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/* Hardware flow control requires using DMAC channel (not yet supported) */
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#ifdef CONFIG_SERIAL_IFLOWCONTROL
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# warning PDC or DMAC support is required for RTS hardware flow control
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# undef CONFIG_SERIAL_IFLOWCONTROL
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# undef CONFIG_USART0_IFLOWCONTROL
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# undef CONFIG_USART1_IFLOWCONTROL
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# undef CONFIG_USART2_IFLOWCONTROL
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#endif
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/* Serial Console ***********************************************************/
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/* Is there a serial console? There should be no more than one defined. It
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* could be on any UARTn, n=1,..,STM32F7_NUART, or USARTn, n=1,.., STM32F7_NUSART
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*/
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#undef HAVE_SERIAL_CONSOLE
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#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART0)
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART1)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART2)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART3)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART0)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2)
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# define HAVE_SERIAL_CONSOLE 1
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#else
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# undef CONFIG_UART0_SERIAL_CONSOLE
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# undef CONFIG_UART1_SERIAL_CONSOLE
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# undef CONFIG_UART2_SERIAL_CONSOLE
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# undef CONFIG_UART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART0_SERIAL_CONSOLE
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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#endif
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/* SPI ******************************************************************************/
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/* Don't enable SPI peripherals not supported by the chip. */
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#if CHIP_NSPI < 1
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# undef CONFIG_STM32F7_SPI0
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# undef CONFIG_STM32F7_SPI1
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#elif CHIP_NSPI < 2
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# undef CONFIG_STM32F7_SPI1
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#endif
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#ifndef CONFIG_STM32F7_HAVE_SPI
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# undef CONFIG_STM32F7_SPI0
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# undef CONFIG_STM32F7_SPI1
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#endif
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/* Are any SPI peripherals enabled? */
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#if !defined(CONFIG_STM32F7_SPI0) && !defined(CONFIG_STM32F7_SPI0)
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# undef CONFIG_STM32F7_HAVE_SPI
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H */
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148
arch/arm/src/stm32f7/stm32_timerisr.c
Normal file
148
arch/arm/src/stm32f7/stm32_timerisr.c
Normal file
@ -0,0 +1,148 @@
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/****************************************************************************
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* arch/arm/src/stm32f7/stm32_timerisr.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
|
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "nvic.h"
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#include "clock/clock.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Select MCU-specific settings
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*
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* The SysTick timer is driven by the output of the Mast Clock Controller
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* prescaler output (i.e., the MDIV output divider is not applied so that
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* the driving frequency is the same as the CPU frequency).
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*
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* The SysTick calibration value is fixed to 37500 which allows the generation
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* of a time base of 1 ms with SysTick clock to the maximum frequency on
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* MCK divided by 8. (?)
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*/
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#define STM32_SYSTICK_CLOCK BOARD_CPU_FREQUENCY
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*/
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#define SYSTICK_RELOAD ((STM32_SYSTICK_CLOCK / CLK_TCK) - 1)
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/* The size of the reload field is 24 bits. Verify that the reload value
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* will fit in the reload register.
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*/
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#if SYSTICK_RELOAD > 0x00ffffff
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# error SYSTICK_RELOAD exceeds the range of the RELOAD register
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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int up_timerisr(int irq, uint32_t *regs)
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{
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/* Process timer interrupt */
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sched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize the timer
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* interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t regval;
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/* Configure SysTick to interrupt at the requested rate */
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putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
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putreg32(0, NVIC_SYSTICK_CURRENT);
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/* Attach the timer interrupt vector */
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(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)up_timerisr);
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/* Enable SysTick interrupts (no divide-by-8) */
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regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
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NVIC_SYSTICK_CTRL_ENABLE);
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putreg32(regval, NVIC_SYSTICK_CTRL);
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/* And enable the timer interrupt */
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up_enable_irq(STM32_IRQ_SYSTICK);
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}
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