From 2bdca23c92e4c9297f12dee21a2057a7e73ce042 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 15 Jul 2015 14:51:41 -0600 Subject: [PATCH] STM32F7: Bring over a couple more Cortex-M7 files from SAMV7 --- arch/arm/src/stm32f7/Make.defs | 2 +- arch/arm/src/stm32f7/stm32_config.h | 292 ++++++++++++++++++++++++++ arch/arm/src/stm32f7/stm32_timerisr.c | 148 +++++++++++++ 3 files changed, 441 insertions(+), 1 deletion(-) create mode 100644 arch/arm/src/stm32f7/stm32_config.h create mode 100644 arch/arm/src/stm32f7/stm32_timerisr.c diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 45e6cc3f2d..4bc683c70c 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -107,4 +107,4 @@ endif # Required STM32F7 files CHIP_ASRCS = -CHIP_CSRCS = +CHIP_CSRCS = stm32_irq.c stm32_start.c stm32_timerisr.c diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h new file mode 100644 index 0000000000..09762b9c6b --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -0,0 +1,292 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_config.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H +#define __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* GPIO IRQs ****************************************************************/ + +#ifndef CONFIG_STM32F7_GPIO_IRQ +# undef CONFIG_STM32F7_GPIOA_IRQ +# undef CONFIG_STM32F7_GPIOB_IRQ +# undef CONFIG_STM32F7_GPIOC_IRQ +# undef CONFIG_STM32F7_GPIOD_IRQ +# undef CONFIG_STM32F7_GPIOE_IRQ +#endif + +#if STM32F7_NPORTS < 1 +# undef CONFIG_STM32F7_GPIOA_IRQ +#endif +#if STM32F7_NPORTS < 2 +# undef CONFIG_STM32F7_GPIOB_IRQ +#endif +#if STM32F7_NPORTS < 3 +# undef CONFIG_STM32F7_GPIOC_IRQ +#endif +#if STM32F7_NPORTS < 4 +# undef CONFIG_STM32F7_GPIOD_IRQ +#endif +#if STM32F7_NPORTS < 5 +# undef CONFIG_STM32F7_GPIOE_IRQ +#endif + +/* UARTs ********************************************************************/ +/* Don't enable UARTs not supported by the chip. */ + +#if STM32F7_NUART < 1 +# undef CONFIG_STM32F7_UART0 +# undef CONFIG_STM32F7_UART1 +# undef CONFIG_STM32F7_UART2 +# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32F7_UART4 +#elif STM32F7_NUART < 2 +# undef CONFIG_STM32F7_UART1 +# undef CONFIG_STM32F7_UART2 +# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32F7_UART4 +#elif STM32F7_NUART < 3 +# undef CONFIG_STM32F7_UART2 +# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32F7_UART4 +#elif STM32F7_NUART < 4 +# undef CONFIG_STM32F7_UART3 +# undef CONFIG_STM32F7_UART4 +#elif STM32F7_NUART < 5 +# undef CONFIG_STM32F7_UART4 +#endif + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ + defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ + defined(CONFIG_STM32F7_UART4) +# define HAVE_UART_DEVICE 1 +#endif + +/* USARTs *******************************************************************/ +/* If the USART is not being used as a UART, then it really isn't enabled + * for our purposes. + */ + +#ifndef CONFIG_USART0_ISUART +# undef CONFIG_STM32F7_USART0 +#endif +#ifndef CONFIG_USART1_ISUART +# undef CONFIG_STM32F7_USART1 +#endif +#ifndef CONFIG_USART2_ISUART +# undef CONFIG_STM32F7_USART2 +#endif + +/* Don't enable USARTs not supported by the chip. */ + +#if STM32F7_NUSART < 1 +# undef CONFIG_STM32F7_USART0 +# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32F7_USART2 +#elif STM32F7_NUSART < 2 +# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32F7_USART2 +#elif STM32F7_NUSART < 3 +# undef CONFIG_STM32F7_USART2 +#endif + +/* Are any USARTs enabled? */ + +#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \ + defined(CONFIG_STM32F7_USART2) +# undef HAVE_UART_DEVICE +# define HAVE_UART_DEVICE 1 +#endif + +/* UART Flow Control ********************************************************/ +/* UARTs do not support flow control */ + +#undef CONFIG_UART0_IFLOWCONTROL +#undef CONFIG_UART1_IFLOWCONTROL +#undef CONFIG_UART2_IFLOWCONTROL +#undef CONFIG_UART3_IFLOWCONTROL +#undef CONFIG_UART4_IFLOWCONTROL + +/* Hardware flow control requires using DMAC channel (not yet supported) */ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +# warning PDC or DMAC support is required for RTS hardware flow control +# undef CONFIG_SERIAL_IFLOWCONTROL +# undef CONFIG_USART0_IFLOWCONTROL +# undef CONFIG_USART1_IFLOWCONTROL +# undef CONFIG_USART2_IFLOWCONTROL +#endif + +/* Serial Console ***********************************************************/ +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn, n=1,..,STM32F7_NUART, or USARTn, n=1,.., STM32F7_NUSART + */ + +#undef HAVE_SERIAL_CONSOLE +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART3) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART0) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +#endif + +/* SPI ******************************************************************************/ +/* Don't enable SPI peripherals not supported by the chip. */ + +#if CHIP_NSPI < 1 +# undef CONFIG_STM32F7_SPI0 +# undef CONFIG_STM32F7_SPI1 +#elif CHIP_NSPI < 2 +# undef CONFIG_STM32F7_SPI1 +#endif + +#ifndef CONFIG_STM32F7_HAVE_SPI +# undef CONFIG_STM32F7_SPI0 +# undef CONFIG_STM32F7_SPI1 +#endif + +/* Are any SPI peripherals enabled? */ + +#if !defined(CONFIG_STM32F7_SPI0) && !defined(CONFIG_STM32F7_SPI0) +# undef CONFIG_STM32F7_HAVE_SPI +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_CONFIG_H */ diff --git a/arch/arm/src/stm32f7/stm32_timerisr.c b/arch/arm/src/stm32f7/stm32_timerisr.c new file mode 100644 index 0000000000..312868b0e3 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_timerisr.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_timerisr.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + + /* Select MCU-specific settings + * + * The SysTick timer is driven by the output of the Mast Clock Controller + * prescaler output (i.e., the MDIV output divider is not applied so that + * the driving frequency is the same as the CPU frequency). + * + * The SysTick calibration value is fixed to 37500 which allows the generation + * of a time base of 1 ms with SysTick clock to the maximum frequency on + * MCK divided by 8. (?) + */ + +#define STM32_SYSTICK_CLOCK BOARD_CPU_FREQUENCY + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + */ + +#define SYSTICK_RELOAD ((STM32_SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + putreg32(0, NVIC_SYSTICK_CURRENT); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts (no divide-by-8) */ + + regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE); + putreg32(regval, NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(STM32_IRQ_SYSTICK); +}