More fixes to problems noted by cppcheck. Some are kind of risky; some are real bugs.

arch/arm/src/c5471/c5471_serial.c

@@ -84,20 +84,20 @@ struct uart_regs_s
 
 struct up_dev_s
 {
-  unsigned int         uartbase;	/* Base address of UART registers */
+  unsigned int         uartbase;    /* Base address of UART registers */
-  unsigned int         baud_base;	/* Base baud for conversions */
+  unsigned int         baud_base;   /* Base baud for conversions */
-  unsigned int         baud;		/* Configured baud */
+  unsigned int         baud;        /* Configured baud */
-  uint8_t              xmit_fifo_size;	/* Size of transmit FIFO */
+  uint8_t              xmit_fifo_size; /* Size of transmit FIFO */
-  uint8_t              irq;			/* IRQ associated with this UART */
+  uint8_t              irq;         /* IRQ associated with this UART */
-  uint8_t              parity;		/* 0=none, 1=odd, 2=even */
+  uint8_t              parity;      /* 0=none, 1=odd, 2=even */
-  uint8_t              bits;		/* Number of bits (7 or 8) */
+  uint8_t              bits;        /* Number of bits (7 or 8) */
 #ifdef CONFIG_UART_HWFLOWCONTROL
-  bool                 flowcontrol;	/* true: Hardware flow control
+  bool                 flowcontrol; /* true: Hardware flow control
-									 * is enabled. */
+                                     * is enabled. */
 #endif
-  bool                 stopbits2;	/* true: Configure with 2
+  bool                 stopbits2;   /* true: Configure with 2
-									 * stop bits instead of 1 */
+                                     * stop bits instead of 1 */
-  struct uart_regs_s   regs;		/* Shadow copy of readonly regs */
+  struct uart_regs_s   regs;        /* Shadow copy of readonly regs */
 };
 
 /****************************************************************************

arch/arm/src/calypso/calypso_serial.c

@@ -94,23 +94,23 @@ struct uart_regs_s
 
 struct up_dev_s
 {
-  unsigned int         uartbase;	/* Base address of UART registers */
+  unsigned int         uartbase;    /* Base address of UART registers */
-  unsigned int         baud_base;	/* Base baud for conversions */
+  unsigned int         baud_base;   /* Base baud for conversions */
-  unsigned int         baud;		/* Configured baud */
+  unsigned int         baud;        /* Configured baud */
-  uint8_t              xmit_fifo_size;	/* Size of transmit FIFO */
+  uint8_t              xmit_fifo_size; /* Size of transmit FIFO */
-  uint8_t              irq;			/* IRQ associated with this UART */
+  uint8_t              irq;         /* IRQ associated with this UART */
-  uint8_t              parity;		/* 0=none, 1=odd, 2=even */
+  uint8_t              parity;      /* 0=none, 1=odd, 2=even */
-  uint8_t              bits;		/* Number of bits (7 or 8) */
+  uint8_t              bits;        /* Number of bits (7 or 8) */
 #ifdef CONFIG_UART_HWFLOWCONTROL
-  bool                 flowcontrol;	/* true: Hardware flow control
+  bool                 flowcontrol; /* true: Hardware flow control
-									 * is enabled. */
+                                     * is enabled. */
 #endif
-  bool                 stopbits2;	/* true: Configure with 2
+  bool                 stopbits2;   /* true: Configure with 2
-									 * stop bits instead of 1 */
+                                     * stop bits instead of 1 */
-  struct uart_regs_s   regs;		/* Shadow copy of readonly regs */
+  struct uart_regs_s   regs;        /* Shadow copy of readonly regs */
 
 #ifdef CONFIG_SERCOMM_CONSOLE
-  bool                 sercomm;		/* Call sercomm in interrupt if true */
+  bool                 sercomm;     /* Call sercomm in interrupt if true */
 #endif
 };
 

arch/arm/src/efm32/efm32_dma.c

@@ -717,7 +717,7 @@ void efm32_dmastop(DMA_HANDLE handle)
   uint32_t regval;
   uint32_t bit;
 
-  DEBUGASSERT(dmach && dmach);
+  DEBUGASSERT(dmach);
   bit = 1 << dmach->chan;
 
   /* Disable the channel */

arch/arm/src/str71x/str71x_serial.c

@@ -631,8 +631,8 @@ static int up_attach(struct uart_dev_s *dev)
        /* Set the uart interrupt priority (the default value is one) */
 
        up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
-    }
 #endif
+    }
 
   return ret;
 }

arch/arm/src/tiva/tiva_ssi.c

@@ -951,7 +951,6 @@ static int ssi_interrupt(int irq, void *context)
 {
   struct tiva_ssidev_s *priv = ssi_mapirq(irq);
   uint32_t regval;
-  int ntxd;
 
   DEBUGASSERT(priv != NULL);
 
@@ -975,7 +974,7 @@ static int ssi_interrupt(int irq, void *context)
 
   /* Handle outgoing Tx FIFO transfers */
 
-  ntxd = ssi_performtx(priv);
+  (void)ssi_performtx(priv);
 
   /* Handle incoming Rx FIFO transfers */
 

arch/avr/src/avr/up_spi.c

@@ -267,6 +267,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
           actual = BOARD_CPU_CLOCK / 128;
         }
 
+#warning REVIST: spcr/spsr are never used
+
       /* Save the frequency setting */
 
 #ifndef CONFIG_SPI_OWNBUS
@@ -531,6 +533,8 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
 #ifndef CONFIG_SPI_OWNBUS
   sem_init(&priv->exclsem, 0, 1);
 #endif
+
+  irqrestore(flags);
   return &priv->spidev;
 }
 #endif /* CONFIG_AVR_SPI */

arch/z80/src/ez80/ez80_spi.c

@@ -359,13 +359,12 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
                          size_t buflen)
 {
   FAR const uint8_t *ptr = (FAR const uint8_t*)buffer;
-  uint8_t response;
 
   /* Loop while there are bytes remaining to be sent */
 
   while (buflen-- > 0)
     {
-      response = spi_transfer(*ptr++);
+      (void)spi_transfer(*ptr++);
     }
 }
 

arch/z80/src/ez80/ez80_timerisr.c

@@ -76,16 +76,14 @@
 
 int up_timerisr(int irq, chipreg_t *regs)
 {
-  volatile uint8_t reg;
+  /* Read the appropriate timer0 register to clear the interrupt */
-
-  /* Read the appropropriate timer0 registr to clear the interrupt */
 
 #ifdef _EZ80F91
-  reg = inp(EZ80_TMR0_IIR);
+  (void)inp(EZ80_TMR0_IIR);
 #else
   /* _EZ80190, _EZ80L92, _EZ80F92, _EZ80F93 */
 
-  reg = inp(EZ80_TMR0_CTL);
+  (void)inp(EZ80_TMR0_CTL);
 #endif
 
   /* Process timer interrupt */
@@ -113,7 +111,6 @@ int up_timerisr(int irq, chipreg_t *regs)
 void up_timer_initialize(void)
 {
   uint16_t reload;
-  uint8_t  reg;
 
   /* Disable the timer */
 
@@ -149,9 +146,9 @@ void up_timer_initialize(void)
   /* Clear any pending timer interrupts */
 
 #if defined(_EZ80F91)
-  reg = inp(EZ80_TMR0_IIR);
+  (void)inp(EZ80_TMR0_IIR);
 #elif defined(_EZ80L92) || defined(_EZ80F92) ||defined(_EZ80F93)
-  reg = inp(EZ80_TMR0_CTL);
+  (void)inp(EZ80_TMR0_CTL);
 #endif
 
   /* Configure and enable the timer */

arch/z80/src/z180/z180_scc.c

@@ -575,8 +575,6 @@ static bool z180_txempty(struct uart_dev_s *dev)
 
 void up_serialinit(void)
 {
-  uint8_t regval;
-
   /* Make sure that all UART interrupts are disabled */
 #warning "Missing logic"
 

arch/z80/src/z180/z180_timerisr.c

@@ -94,16 +94,14 @@
 
 int up_timerisr(int irq, chipreg_t *regs)
 {
-  volatile uint8_t regval;
-
   /* "When TMDR0 decrements to 0, TIF0 is set to 1. This generates an interrupt
    * request if enabled by TIE0 = 1. TIF0 is reset to 0 when TCR is read and
    * the higher or lower byte of TMDR0 is read."
    */
 
-  regval = inp(Z180_PRT_TCR);
+  (void)inp(Z180_PRT_TCR);
-  regval = inp(Z180_PRT0_DRL);
+  (void)inp(Z180_PRT0_DRL);
-  regval = inp(Z180_PRT0_DRH);
+  (void)inp(Z180_PRT0_DRH);
 
   /* Process timer interrupt */
 

arch/z80/src/z8/z8_lowuart.c

@@ -75,9 +75,12 @@ extern uint32_t get_freq(void);
 
 void up_lowserialinit(void)
 {
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) || \
+   (defined(EZ8_UART1) && defined(CONFIG_UART1_SERIAL_CONSOLE))
   uint32_t freq = get_freq();
   uint16_t brg;
   uint8_t  val;
+#endif
 
 #ifdef CONFIG_UART0_SERIAL_CONSOLE
   /* Set the baudrate */