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Here's a patch to split the STM32 FMC/FSMC functionality (FSMC = flexible static memory controller, FMC = flexible memory controller = FSMC + sdram support). This commit makes FMC it's own thing rather than piggy backing on the FSMC code. The peripherals have a few utility functions and this commits lets you have a common function in the arch/arm/src/stm32 rather than having duplicate functions in the board code.

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This commit is contained in:
Jason Harris 2019-05-27 07:21:52 -06:00 committed by Gregory Nutt
parent 9c676a9e67
commit 2c3ca9d756
66 changed files with 1586 additions and 1150 deletions
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27
arch/arm/src/stm32/Kconfig
View File

@ -1662,7 +1662,7 @@ config STM32_STM32F407
config STM32_STM32F427
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_FMC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
select STM32_HAVE_UART4
@ -1704,7 +1704,7 @@ config STM32_STM32F427
config STM32_STM32F429
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_FMC
select STM32_HAVE_LTDC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
@ -1782,7 +1782,7 @@ config STM32_STM32F446
config STM32_STM32F469
bool
default n
select STM32_HAVE_FSMC
select STM32_HAVE_FMC
select STM32_HAVE_LTDC
select STM32_HAVE_CCM
select STM32_HAVE_USART3
@ -1854,6 +1854,10 @@ config STM32_HAVE_OTGFS
bool
default n
config STM32_HAVE_FMC
bool
default n
config STM32_HAVE_FSMC
bool
default n
@ -2374,6 +2378,11 @@ config STM32_FSMC
default n
depends on STM32_HAVE_FSMC
config STM32_FMC
bool "FMC"
default n
depends on STM32_HAVE_FMC
config STM32_HASH
bool "HASH"
default n
@ -3102,13 +3111,13 @@ config STM32_DMACAPABLE
Drivers then may use this information to determine if they should
attempt the DMA or fall back to a different transfer method.
config STM32_FSMC_SRAM
bool "External SRAM on FSMC"
config STM32_EXTERNAL_RAM
bool "External RAM on FSMC/FMC"
default n
depends on STM32_FSMC
depends on STM32_FSMC || STM32_FMC
select ARCH_HAVE_HEAP2
---help---
In addition to internal SRAM, SRAM may also be available through the FSMC.
In addition to internal SRAM, external RAM may be available through the FSMC/FMC.
menu "Timer Configuration"
depends on STM32_TIM
@ -9460,7 +9469,7 @@ config STM32_LTDC_FB_BASE
---help---
If you are using the LTDC, then you must provide the address
of the start of the framebuffer. This address will typically
be in the SRAM or SDRAM memory region of the FSMC.
be in the SRAM or SDRAM memory region of the FSMC/FMC.
config STM32_LTDC_FB_SIZE
int "Framebuffer memory size (bytes)"
@ -9634,7 +9643,7 @@ config STM32_DMA2D_FB_BASE
---help---
If you are using the DMA2D, then you must provide the address
of the start of the DMA2D overlays framebuffer. This address will typically
be in the SRAM or SDRAM memory region of the FSMC.
be in the SRAM or SDRAM memory region of the FSMC/FMC.
config STM32_DMA2D_FB_SIZE
int "Framebuffer memory size (bytes)"

8
arch/arm/src/stm32/Make.defs
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@ -265,3 +265,11 @@ endif
ifeq ($(CONFIG_STM32_BBSRAM),y)
CHIP_CSRCS += stm32_bbsram.c
endif
ifeq ($(CONFIG_STM32_FMC),y)
CHIP_CSRCS += stm32_fmc.c
endif
ifeq ($(CONFIG_STM32_FSMC),y)
CHIP_CSRCS += stm32_fsmc.c
endif

383
arch/arm/src/stm32/hardware/stm32_fmc.h Normal file
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@ -0,0 +1,383 @@
/************************************************************************************
* arch/arm/src/stm32/hardware/stm32_fmc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Jason T. Harris <sirmanlypowers@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_FMC_BCR_OFFSET(n) (8 * ((n) - 1))
#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
#define STM32_FMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004)
#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104)
#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
#define STM32_FMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040)
#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
#define STM32_FMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044)
#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048)
#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c)
#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
#define STM32_FMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054)
#define STM32_FMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */
#define STM32_FMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */
#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */
#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 2 */
#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 1 */
#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 2 */
#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */
#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
/* Register Addresses ***************************************************************/
#define STM32_FMC_BCR(n) (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n))
#define STM32_FMC_BCR1 (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET)
#define STM32_FMC_BCR2 (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET)
#define STM32_FMC_BCR3 (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET)
#define STM32_FMC_BCR4 (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET)
#define STM32_FMC_BTR(n) (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n))
#define STM32_FMC_BTR1 (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET)
#define STM32_FMC_BTR2 (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET)
#define STM32_FMC_BTR3 (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET)
#define STM32_FMC_BTR4 (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET)
#define STM32_FMC_BWTR(n) (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n))
#define STM32_FMC_BWTR1 (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET)
#define STM32_FMC_BWTR2 (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET)
#define STM32_FMC_BWTR3 (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET)
#define STM32_FMC_BWTR4 (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET)
#define STM32_FMC_PCR(n) (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n))
#define STM32_FMC_PCR2 (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET)
#define STM32_FMC_PCR3 (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET)
#define STM32_FMC_PCR4 (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET)
#define STM32_FMC_SR(n) (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n))
#define STM32_FMC_SR2 (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET)
#define STM32_FMC_SR3 (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET)
#define STM32_FMC_SR4 (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET)
#define STM32_FMC_PMEM(n) (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n))
#define STM32_FMC_PMEM2 (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET)
#define STM32_FMC_PMEM3 (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET)
#define STM32_FMC_PMEM4 (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET)
#define STM32_FMC_PATT(n) (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n))
#define STM32_FMC_PATT2 (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET)
#define STM32_FMC_PATT3 (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET)
#define STM32_FMC_PATT4 (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET)
#define STM32_FMC_PIO4 (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET)
#define STM32_FMC_ECCR(n) (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n))
#define STM32_FMC_ECCR2 (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET)
#define STM32_FMC_ECCR3 (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET)
#define STM32_FMC_SDCR1 (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET)
#define STM32_FMC_SDCR2 (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET)
#define STM32_FMC_SDTR1 (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET)
#define STM32_FMC_SDTR2 (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET)
#define STM32_FMC_SDCMR (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET)
#define STM32_FMC_SDRTR (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET)
#define STM32_FMC_SDSR (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FMC_BCR_RSTVALUE 0x000003d2
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
#define FMC_BTR_RSTVALUE 0xffffffff
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FMC_PCR_PTYP (1 << 3) /* Memory type */
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */
#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT)
# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */
#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT)
# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */
#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT)
# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */
#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT)
# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FMC_SDCR_RESERVED (0x1ffff << 15) /* reserved bits */
#define FMC_SDCR_RPIPE_0 (0 << 13) /* read pipe */
#define FMC_SDCR_RPIPE_1 (1 << 13)
#define FMC_SDCR_RPIPE_2 (2 << 13)
#define FMC_SDCR_READBURST (1 << 12) /* read burst */
#define FMC_SDCR_SDCLK_DISABLE (0 << 10) /* sdram clock */
#define FMC_SDCR_SDCLK_2X (2 << 10)
#define FMC_SDCR_SDCLK_3X (3 << 10)
#define FMC_SDCR_WP (1 << 9) /* write protect */
#define FMC_SDCR_CAS_LATENCY_1 (1 << 7) /* cas latency */
#define FMC_SDCR_CAS_LATENCY_2 (2 << 7)
#define FMC_SDCR_CAS_LATENCY_3 (3 << 7)
#define FMC_SDCR_NBANKS_2 (0 << 6) /* number of internal banks */
#define FMC_SDCR_NBANKS_4 (1 << 6)
#define FMC_SDCR_WIDTH_8 (0 << 4) /* memory width */
#define FMC_SDCR_WIDTH_16 (1 << 4)
#define FMC_SDCR_WIDTH_32 (2 << 4)
#define FMC_SDCR_ROWS_11 (0 << 2) /* number of rows */
#define FMC_SDCR_ROWS_12 (1 << 2)
#define FMC_SDCR_ROWS_13 (2 << 2)
#define FMC_SDCR_COLS_8 (0 << 0) /* number of columns */
#define FMC_SDCR_COLS_9 (1 << 0)
#define FMC_SDCR_COLS_10 (2 << 0)
#define FMC_SDCR_COLS_11 (3 << 0)
#define FMC_SDTR_RESERVED (15 << 28) /* reserved bits */
#define FMC_SDTR_TMRD(n) (((n & 15) - 1) << 0)
#define FMC_SDTR_TXSR(n) (((n & 15) - 1) << 4)
#define FMC_SDTR_TRAS(n) (((n & 15) - 1) << 8)
#define FMC_SDTR_TRC(n) (((n & 15) - 1) << 12)
#define FMC_SDTR_TWR(n) (((n & 15) - 1) << 16)
#define FMC_SDTR_TRP(n) (((n & 15) - 1) << 20)
#define FMC_SDTR_TRCD(n) (((n & 15) - 1) << 24)
/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet.
* They should be standard, but it's probably a good idea to review
* the datasheet for your SDRAM device.
*/
#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */
#define FMC_SDCMR_MDR_BURST_LENGTH_1 ((0 << 0) << 9)
#define FMC_SDCMR_MDR_BURST_LENGTH_2 ((1 << 0) << 9)
#define FMC_SDCMR_MDR_BURST_LENGTH_4 ((2 << 0) << 9)
#define FMC_SDCMR_MDR_BURST_LENGTH_8 ((3 << 0) << 9)
#define FMC_SDCMR_MDR_BURST_LENGTH_FULL ((7 << 0) << 9)
#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL ((0 << 3) << 9)
#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE ((1 << 3) << 9)
#define FMC_SDCMR_MDR_CAS_LATENCY_1 ((1 << 4) << 9)
#define FMC_SDCMR_MDR_CAS_LATENCY_2 ((2 << 4) << 9)
#define FMC_SDCMR_MDR_CAS_LATENCY_3 ((3 << 4) << 9)
#define FMC_SDCMR_MDR_MODE_NORMAL ((0 << 7) << 9)
#define FMC_SDCMR_MDR_WBL_BURST ((0 << 9) << 9)
#define FMC_SDCMR_MDR_WBL_SINGLE ((1 << 9) << 9)
#define FMC_SDCMR_NRFS(n) (((n & 15) - 1) << 5)
#define FMC_SDCMR_BANK_1 (1 << 4)
#define FMC_SDCMR_BANK_2 (1 << 3)
#define FMC_SDCMR_CMD_NORMAL (0 << 0)
#define FMC_SDCMR_CMD_CLK_ENABLE (1 << 0)
#define FMC_SDCMR_CMD_PALL (2 << 0)
#define FMC_SDCMR_CMD_AUTO_REFRESH (3 << 0)
#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0)
#define FMC_SDCMR_CMD_SELF_REFRESH (5 << 0)
#define FMC_SDCMR_CMD_POWER_DOWN (6 << 0)
#define FMC_SDSR_RE (1 << 0)
#define FMC_SDSR_BUSY (1 << 5)
#define FMC_SDSR_MODES1_NORMAL (0 << 1)
#define FMC_SDSR_MODES1_SELF_REFRESH (1 << 1)
#define FMC_SDSR_MODES1_POWER_DOWN (2 << 1)
#define FMC_SDSR_MODES2_NORMAL (0 << 3)
#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3)
#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3)
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */

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/************************************************************************************
* arch/arm/src/stm32/hardware/stm32_fsmc.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_FSMC_BCR_OFFSET(n) (8 * ((n) - 1))
#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
#define STM32_FSMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004)
#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104)
#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
#define STM32_FSMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040)
#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
#define STM32_FSMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044)
#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048)
#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c)
#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
#define STM32_FSMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054)
#define STM32_FSMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */
#define STM32_FSMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */
/* Register Addresses ***************************************************************/
#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n))
#define STM32_FSMC_BCR1 (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET)
#define STM32_FSMC_BCR2 (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET)
#define STM32_FSMC_BCR3 (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET)
#define STM32_FSMC_BCR4 (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET)
#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n))
#define STM32_FSMC_BTR1 (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET)
#define STM32_FSMC_BTR2 (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET)
#define STM32_FSMC_BTR3 (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET)
#define STM32_FSMC_BTR4 (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET)
#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n))
#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET)
#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET)
#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET)
#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET)
#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n))
#define STM32_FSMC_PCR2 (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET)
#define STM32_FSMC_PCR3 (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET)
#define STM32_FSMC_PCR4 (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET)
#define STM32_FSMC_SR(n) (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n))
#define STM32_FSMC_SR2 (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET)
#define STM32_FSMC_SR3 (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET)
#define STM32_FSMC_SR4 (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET)
#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n))
#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET)
#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET)
#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET)
#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n))
#define STM32_FSMC_PATT2 (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET)
#define STM32_FSMC_PATT3 (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET)
#define STM32_FSMC_PATT4 (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET)
#define STM32_FSMC_PIO4 (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET)
#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n))
#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET)
#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET)
/* Register Bitfield Definitions ****************************************************/
#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT)
#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT)
#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FSMC_BCR_RSTVALUE 0x000003d2
#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT)
# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT)
# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT)
# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT)
# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT)
# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT)
# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_BTR_RSTVALUE 0xffffffff
#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT)
# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT)
# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT)
# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT)
# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT)
# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR_PTYP (1 << 3) /* Memory type */
#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT)
#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT)
# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK)
# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT)
# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT)
# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT)
# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT)
# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT)
# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT)
# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT)
# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT)
# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT)
# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */
#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT)
# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */
#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT)
# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */
#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT)
# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */
#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT)
# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */

14
arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h
View File

@ -45,6 +45,7 @@
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
@ -52,7 +53,18 @@
# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_FSMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
/* 0xc0000000-0xdfffffff: 512Mb (not used) */
#define STM32_FMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FMC bank1&2 block */
# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
# define STM32_FMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define STM32_FMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FMC bank3&4 block */
# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define STM32_FMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb FMC register block */
#define STM32_FMC_BASE56 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FMC bank5&6 block */
# define STM32_FMC_BANK5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb SDRAM */
# define STM32_FMC_BANK6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb SDRAM */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0xf0000000

191
arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h
View File

@ -258,6 +258,141 @@
# define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
#endif
/* Flexible Memory Controller (FMC) */
#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
#define GPIO_FMC_NE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
#define GPIO_FMC_NE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#define GPIO_FMC_NE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
#define GPIO_FMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
#define GPIO_FMC_INT3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
#define GPIO_FMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_FMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
# define GPIO_FMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
# define GPIO_FMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
# define GPIO_FMC_NCE2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
# define GPIO_FMC_NCE4_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
# define GPIO_FMC_NCE4_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
# define GPIO_FMC_NIORD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
# define GPIO_FMC_NIOWR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
# define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
# define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
# define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
# define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
# define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
# define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
# define GPIO_FMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
# define GPIO_FMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
# define GPIO_FMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
#endif
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
# define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
# define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
# define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
# define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
# define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
# define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
# define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
# define GPIO_FMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
# define GPIO_FMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define GPIO_FMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
# define GPIO_FMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
# define GPIO_FMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
# define GPIO_FMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
# define GPIO_FMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
# define GPIO_FMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
# define GPIO_FMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
# define GPIO_FMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
# define GPIO_FMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
# define GPIO_FMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
# define GPIO_FMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
# define GPIO_FMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
# define GPIO_FMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
# define GPIO_FMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
# define GPIO_FMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
# define GPIO_FMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
# define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
# define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
# define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
# define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
# define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_STM32F446)
# define GPIO_FMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
#endif
#if defined(CONFIG_STM32_STM32F469)
# define GPIO_FMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
# define GPIO_FMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
#endif
/* Flexible Static Memory Controller (FSMC) */
#define GPIO_FSMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
@ -318,8 +453,7 @@
#define GPIO_FSMC_NCE3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
# define GPIO_FSMC_CD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
# define GPIO_FSMC_INT2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
# define GPIO_FSMC_INTR (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
@ -342,59 +476,6 @@
# define GPIO_FSMC_NREG (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
#endif
#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define GPIO_FSMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
# define GPIO_FSMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
# define GPIO_FSMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
# define GPIO_FSMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
# define GPIO_FSMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
# define GPIO_FSMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
# define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
# define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
# define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
# define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define GPIO_FSMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
# define GPIO_FSMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
# define GPIO_FSMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
# define GPIO_FSMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
# define GPIO_FSMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
# define GPIO_FSMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
# define GPIO_FSMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
# define GPIO_FSMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
# define GPIO_FSMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
# define GPIO_FSMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
# define GPIO_FSMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
# define GPIO_FSMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
# define GPIO_FSMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
# define GPIO_FSMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
# define GPIO_FSMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
# define GPIO_FSMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
# define GPIO_FSMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
# define GPIO_FSMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
# define GPIO_FSMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FSMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FSMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
# define GPIO_FSMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FSMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_FSMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
# define GPIO_FSMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_STM32F446)
# define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
#endif
#if defined(CONFIG_STM32_STM32F469)
# define GPIO_FSMC_CLE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
# define GPIO_FSMC_ALE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
#endif
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)

1
arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
View File

@ -448,6 +448,7 @@
/* AHB3 Peripheral Clock enable register */
#define RCC_AHB3ENR_FSMCEN (1 << 0) /* Bit 0: Flexible static memory controller module clock enable */
#define RCC_AHB3ENR_FMCEN (1 << 0) /* Bit 0: Flexible memory controller module clock enable */
#if defined(CONFIG_STM32_STM32F446)
# define RCC_AHB3ENR_QSPIEN (1 << 1) /* Bit 1: QUADSPI memory controller module clock enable */
#endif

1
arch/arm/src/stm32/stm32.h
View File

@ -64,6 +64,7 @@
#include "stm32_dac.h"
#include "stm32_exti.h"
#include "stm32_flash.h"
#include "stm32_fmc.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32_i2c.h"

59
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -76,24 +76,23 @@
*
* CONFIG_STM32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP
*
* In addition to internal SRAM, SRAM may also be available through the FSMC.
* In order to use FSMC SRAM, the following additional things need to be
* present in the NuttX configuration file:
* In addition to internal SRAM, external RAM may also be available through the
* FMC/FSMC. To use external RAM, the following things need to be present in
* the NuttX configuration file:
*
* CONFIG_STM32_FSMC=y : Enables the FSMC
* CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
* FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
* address space
* CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
* address space
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the FSMC SRAM (as determined by
* the rules provided below)
* CONFIG_STM32_FSMC=y : Enables the FSMC
* CONFIG_STM32_FMC=y : Enables the FMC
* CONFIG_STM32_EXTERNAL_RAM=y : Indicates external RAM is available via the
* FMC/FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the external RAM
* CONFIG_HEAP2_SIZE : The size of the external RAM
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the external RAM (as determined by
* the rules provided below)
*/
#ifndef CONFIG_STM32_FSMC
# undef CONFIG_STM32_FSMC_SRAM
#if !defined(CONFIG_STM32_FSMC) && !defined(CONFIG_STM32_FMC)
# undef CONFIG_STM32_EXTERNAL_RAM
#endif
/* The STM32L15xxx family has only internal SRAM. The heap is in one contiguous
@ -108,7 +107,7 @@
/* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not the STM32L15X */
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
/* The STM32L EnergyLite family has no CCM SRAM */
@ -134,10 +133,10 @@
/* Check if external FSMC SRAM is provided */
# ifdef CONFIG_STM32_FSMC_SRAM
# ifdef CONFIG_STM32_EXTERNAL_RAM
# if CONFIG_MM_REGIONS < 2
# warning "FSMC SRAM not included in the heap"
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
# elif CONFIG_MM_REGIONS > 2
# error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
@ -173,7 +172,7 @@
/* There is no FSMC */
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
/* There are 2 possible SRAM configurations:
*
@ -243,7 +242,7 @@
/* There is no FSMC */
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
/* There are 2 possible SRAM configurations:
*
@ -305,7 +304,7 @@
/* There is no FSMC */
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
/* The STM32 F37xx has no CCM SRAM */
@ -389,26 +388,26 @@
*
* Configuration 1. System SRAM (only)
* CONFIG_MM_REGIONS == 1
* CONFIG_STM32_FSMC_SRAM NOT defined
* CONFIG_STM32_EXTERNAL_RAM NOT defined
* CONFIG_STM32_CCMEXCLUDE defined
* Configuration 2. System SRAM and CCM SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_STM32_FSMC_SRAM NOT defined
* CONFIG_STM32_EXTERNAL_RAM NOT defined
* CONFIG_STM32_CCMEXCLUDE NOT defined
* Configuration 3. System SRAM and FSMC SRAM
* CONFIG_MM_REGIONS == 2
* CONFIG_STM32_FSMC_SRAM defined
* CONFIG_STM32_EXTERNAL_RAM defined
* CONFIG_STM32_CCMEXCLUDE defined
* Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_STM32_FSMC_SRAM defined
* CONFIG_STM32_EXTERNAL_RAM defined
* CONFIG_STM32_CCMEXCLUDE NOT defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
*/
# if defined(CONFIG_STM32_FSMC_SRAM)
# if defined(CONFIG_STM32_EXTERNAL_RAM)
/* Configuration 3 or 4. External SRAM is available. CONFIG_MM_REGIONS
* should be at least 2.
@ -419,7 +418,7 @@
/* Only one memory region. Force Configuration 1 */
# warning "FSMC SRAM (and CCM SRAM) excluded from the heap"
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
# undef CONFIG_STM32_CCMEXCLUDE
# define CONFIG_STM32_CCMEXCLUDE 1
@ -497,10 +496,10 @@
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_STM32_FSMC_SRAM
#ifdef CONFIG_STM32_EXTERNAL_RAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_STM32_FSMC_SRAM
# undef CONFIG_STM32_EXTERNAL_RAM
# endif
#endif
@ -688,7 +687,7 @@ void up_addregion(void)
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
#endif
#ifdef CONFIG_STM32_FSMC_SRAM
#ifdef CONFIG_STM32_EXTERNAL_RAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */

219
arch/arm/src/stm32/stm32_fmc.c Normal file
View File

@ -0,0 +1,219 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_fmc.c
*
* Copyright (C) 20019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "stm32.h"
#if defined(CONFIG_STM32_FMC)
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: stm32_fmc_sdram_wait
*
* Description:
* Wait for the SDRAM controller to be ready.
*
****************************************************************************/
void stm32_fmc_sdram_wait(void)
{
int timeout = 0xffff;
while (timeout > 0)
{
if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
{
break;
}
timeout--;
}
DEBUGASSERT(timeout > 0);
}
/****************************************************************************
* Name: stm32_fmc_enable
*
* Description:
* Enable clocking to the FMC.
*
****************************************************************************/
void stm32_fmc_enable(void)
{
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
}
/****************************************************************************
* Name: stm32_fmc_disable
*
* Description:
* Disable clocking to the FMC.
*
****************************************************************************/
void stm32_fmc_disable(void)
{
modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0);
}
/****************************************************************************
* Name: stm32_fmc_sdram_write_protect
*
* Description:
* Enable/Disable writes to an SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_write_protect(int bank, bool state)
{
uint32_t val, sdcr;
DEBUGASSERT(bank == 1 || bank == 2);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
stm32_fmc_sdram_wait();
val = getreg32(sdcr);
if (state)
{
val |= FMC_SDCR_WP; /* wp == 1 */
}
else
{
val &= ~FMC_SDCR_WP; /* wp == 0 */
}
putreg32(val, sdcr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_refresh_rate
*
* Description:
* Set the SDRAM refresh rate.
*
****************************************************************************/
void stm32_fmc_sdram_set_refresh_rate(int count)
{
uint32_t val;
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDRTR);
val &= ~(0x1fff << 1); /* preserve non-count bits */
val |= (count << 1);
putreg32(val, STM32_FMC_SDRTR);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
* Set the SDRAM timing parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
{
uint32_t val, sdtr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
val = getreg32(sdtr);
val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
val |= timing;
putreg32(val, sdtr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
* Set the SDRAM control parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
{
uint32_t val, sdcr;
DEBUGASSERT((bank == 1) || (bank == 2));
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
val = getreg32(sdcr);
val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
val |= ctrl;
putreg32(val, sdcr);
}
/****************************************************************************
* Name: stm32_fmc_sdram_command
*
* Description:
* Send a command to the SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_command(uint32_t cmd)
{
uint32_t val;
DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
/* Wait for the controller to be ready */
stm32_fmc_sdram_wait();
val = getreg32(STM32_FMC_SDCMR);
val &= FMC_SDCMR_RESERVED; /* Preserve reserved bits */
val |= cmd;
putreg32(val, STM32_FMC_SDCMR);
}
#endif /* CONFIG_STM32_FMC */

149
arch/arm/src/stm32/stm32_fmc.h Normal file
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@ -0,0 +1,149 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_fmc.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H
#define __ARCH_ARM_STC_STM32_STM32_FMC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32_fmc.h"
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_fmc_sdram_wait
*
* Description:
* Wait for the SDRAM controller to be ready.
*
****************************************************************************/
void stm32_fmc_sdram_wait(void);
/****************************************************************************
* Name: stm32_fmc_enable
*
* Description:
* Enable clocking to the FMC.
*
****************************************************************************/
void stm32_fmc_enable(void);
/****************************************************************************
* Name: stm32_fmc_disable
*
* Description:
* Disable clocking to the FMC.
*
****************************************************************************/
void stm32_fmc_disable(void);
/****************************************************************************
* Name: stm32_fmc_sdram_write_protect
*
* Description:
* Enable/Disable writes to an SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_write_protect(int bank, bool state);
/****************************************************************************
* Name: stm32_fmc_sdram_set_refresh_rate
*
* Description:
* Set the SDRAM refresh rate.
*
****************************************************************************/
void stm32_fmc_sdram_set_refresh_rate(int count);
/****************************************************************************
* Name: stm32_fmc_sdram_set_timing
*
* Description:
* Set the SDRAM timing parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing);
/****************************************************************************
* Name: stm32_fmc_sdram_set_control
*
* Description:
* Set the SDRAM control parameters.
*
****************************************************************************/
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl);
/****************************************************************************
* Name: stm32_fmc_sdram_command
*
* Description:
* Send a command to the SDRAM.
*
****************************************************************************/
void stm32_fmc_sdram_command(uint32_t cmd);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */

98
arch/arm/src/stm32/stm32_fsmc.c Normal file
View File

@ -0,0 +1,98 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_fsmc.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "stm32.h"
#if defined(CONFIG_STM32_FSMC)
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Name: stm32_fsmc_enable
*
* Description:
* Enable clocking to the FSMC.
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX)
void stm32_fsmc_enable(void)
{
modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN);
}
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
void stm32_fsmc_enable(void)
{
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FSMCEN);
}
#endif
/****************************************************************************
* Name: stm32_fsmc_disable
*
* Description:
* Disable clocking to the FSMC.
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX)
void stm32_fsmc_disable(void)
{
modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0);
}
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
void stm32_fsmc_disable(void)
{
modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FSMCEN, 0);
}
#endif
#endif /* CONFIG_STM32_FSMC */

394
arch/arm/src/stm32/stm32_fsmc.h
View File

@ -1,8 +1,8 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_fsmc.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_STM32_FSMC_H
#define __ARCH_ARM_SRC_STM32_STM32_FSMC_H
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FSMC_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FSMC_H
/************************************************************************************
* Included Files
@ -43,355 +43,47 @@
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_FSMC_BCR_OFFSET(n) (8*((n)-1))
#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
#define STM32_FSMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
#define STM32_FSMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
#define STM32_FSMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040)
#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
#define STM32_FSMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044)
#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
#define STM32_FSMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048)
#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
#define STM32_FSMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c)
#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
#define STM32_FSMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c)
#define STM32_FSMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */
#define STM32_FSMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */
#if defined(CONFIG_STM32_STM32F429)
# define STM32_FSMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
# define STM32_FSMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
# define STM32_FSMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register?, Bank 0 */
# define STM32_FSMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register?, Bank 1 */
# define STM32_FSMC_SDCMR_OFFSET 0x0150 /* SDRAM Config register? */
# define STM32_FSMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe? */
# define STM32_FSMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
#endif
/* Register Addresses ***************************************************************/
#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE+STM32_FSMC_BCR_OFFSET(n))
#define STM32_FSMC_BCR1 (STM32_FSMC_BASE+STM32_FSMC_BCR1_OFFSET )
#define STM32_FSMC_BCR2 (STM32_FSMC_BASE+STM32_FSMC_BCR2_OFFSET )
#define STM32_FSMC_BCR3 (STM32_FSMC_BASE+STM32_FSMC_BCR3_OFFSET )
#define STM32_FSMC_BCR4 (STM32_FSMC_BASE+STM32_FSMC_BCR4_OFFSET )
#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE+STM32_FSMC_BTR_OFFSET(n))
#define STM32_FSMC_BTR1 (STM32_FSMC_BASE+STM32_FSMC_BTR1_OFFSET )
#define STM32_FSMC_BTR2 (STM32_FSMC_BASE+STM32_FSMC_BTR2_OFFSET )
#define STM32_FSMC_BTR3 (STM32_FSMC_BASE+STM32_FSMC_BTR3_OFFSET )
#define STM32_FSMC_BTR4 (STM32_FSMC_BASE+STM32_FSMC_BTR4_OFFSET )
#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE+STM32_FSMC_BWTR_OFFSET(n))
#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE+STM32_FSMC_BWTR1_OFFSET )
#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE+STM32_FSMC_BWTR2_OFFSET )
#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE+STM32_FSMC_BWTR3_OFFSET )
#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE+STM32_FSMC_BWTR4_OFFSET )
#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE+STM32_FSMC_PCR_OFFSET(n))
#define STM32_FSMC_PCR2 (STM32_FSMC_BASE+STM32_FSMC_PCR2_OFFSET )
#define STM32_FSMC_PCR3 (STM32_FSMC_BASE+STM32_FSMC_PCR3_OFFSET )
#define STM32_FSMC_PCR4 (STM32_FSMC_BASE+STM32_FSMC_PCR4_OFFSET )
#define STM32_FSMC_SR(n) (STM32_FSMC_BASE+STM32_FSMC_SR_OFFSET(n))
#define STM32_FSMC_SR2 (STM32_FSMC_BASE+STM32_FSMC_SR2_OFFSET )
#define STM32_FSMC_SR3 (STM32_FSMC_BASE+STM32_FSMC_SR3_OFFSET )
#define STM32_FSMC_SR4 (STM32_FSMC_BASE+STM32_FSMC_SR4_OFFSET )
#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE+STM32_FSMC_PMEM_OFFSET(n))
#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE+STM32_FSMC_PMEM2_OFFSET )
#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE+STM32_FSMC_PMEM3_OFFSET )
#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE+STM32_FSMC_PMEM4_OFFSET )
#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE+STM32_FSMC_PATT_OFFSET(n))
#define STM32_FSMC_PATT2 (STM32_FSMC_BASE+STM32_FSMC_PATT2_OFFSET )
#define STM32_FSMC_PATT3 (STM32_FSMC_BASE+STM32_FSMC_PATT3_OFFSET )
#define STM32_FSMC_PATT4 (STM32_FSMC_BASE+STM32_FSMC_PATT4_OFFSET )
#define STM32_PIO4 (STM32_FSMC_BASE+STM32_FSMC_PIO4_OFFSET )
#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE+STM32_FSMC_ECCR_OFFSET(n))
#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE+STM32_FSMC_ECCR2_OFFSET )
#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE+STM32_FSMC_ECCR3_OFFSET )
#if defined(CONFIG_STM32_STM32F429)
# define STM32_FSMC_SDCR1 (STM32_FSMC_BASE+STM32_FSMC_SDCR1_OFFSET)
# define STM32_FSMC_SDCR2 (STM32_FSMC_BASE+STM32_FSMC_SDCR2_OFFSET)
# define STM32_FSMC_SDTR1 (STM32_FSMC_BASE+STM32_FSMC_SDTR1_OFFSET)
# define STM32_FSMC_SDTR2 (STM32_FSMC_BASE+STM32_FSMC_SDTR2_OFFSET)
# define STM32_FSMC_SDCMR (STM32_FSMC_BASE+STM32_FSMC_SDCMR_OFFSET)
# define STM32_FSMC_SDRTR (STM32_FSMC_BASE+STM32_FSMC_SDRTR_OFFSET)
# define STM32_FSMC_SDSR (STM32_FSMC_BASE+STM32_FSMC_SDSR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT)
#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT)
#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FSMC_BCR_RSTVALUE 0x000003d2
#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT)
# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT)
# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT)
# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT)
# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT)
# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT)
# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_BTR_RSTVALUE 0xffffffff
#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT)
# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT)
# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT)
# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT)
# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT)
# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR_PTYP (1 << 3) /* Memory type */
#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT)
#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT)
# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK)
# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT)
# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT)
# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT)
# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT)
# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT)
# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT)
# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT)
# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT)
# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT)
# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT)
# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT)
# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT)
# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT)
# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#if defined(CONFIG_STM32_STM32F429)
# define FSMC_SDRAM_CR_COLBITS_8 0x00000000
# define FSMC_SDRAM_CR_COLBITS_9 0x00000001
# define FSMC_SDRAM_CR_COLBITS_10 0x00000002
# define FSMC_SDRAM_CR_COLBITS_11 0x00000003
# define FSMC_SDRAM_CR_ROWBITS_11 0x00000000
# define FSMC_SDRAM_CR_ROWBITS_12 0x00000004
# define FSMC_SDRAM_CR_ROWBITS_13 0x00000008
# define FSMC_SDRAM_CR_WIDTH_8 0x00000000
# define FSMC_SDRAM_CR_WIDTH_16 0x00000010
# define FSMC_SDRAM_CR_WIDTH_32 0x00000020
# define FSMC_SDRAM_CR_BANKS_2 0x00000000
# define FSMC_SDRAM_CR_BANKS_4 0x00000040
# define FSMC_SDRAM_CR_CASLAT_1 0x00000080
# define FSMC_SDRAM_CR_CASLAT_2 0x00000100
# define FSMC_SDRAM_CR_CASLAT_3 0x00000180
# define FSMC_SDRAM_CR_WRITE_PROT 0x00000200
# define FSMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
# define FSMC_SDRAM_CR_SDCLK_2X 0x00000800
# define FSMC_SDRAM_CR_SDCLK_3X 0x00000C00
# define FSMC_SDRAM_CR_BURST_READ 0x00001000
# define FSMC_SDRAM_CR_RPIPE_0 0x00000000
# define FSMC_SDRAM_CR_RPIPE_1 0x00002000
# define FSMC_SDRAM_CR_RPIPE_2 0x00004000
# define FSMC_SDRAM_TR_TMRD_SHIFT 0
# define FSMC_SDRAM_TR_TXSR_SHIFT 4
# define FSMC_SDRAM_TR_TRAS_SHIFT 8
# define FSMC_SDRAM_TR_TRC_SHIFT 12
# define FSMC_SDRAM_TR_TWR_SHIFT 16
# define FSMC_SDRAM_TR_TRP_SHIFT 20
# define FSMC_SDRAM_TR_TRCD_SHIFT 24
# define FSMC_SDRAM_MODE_CMD_NORMAL 0
# define FSMC_SDRAM_MODE_CMD_CLK_ENABLE 1
# define FSMC_SDRAM_MODE_CMD_PALL 2
# define FSMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
# define FSMC_SDRAM_MODE_CMD_LOAD_MODE 4
# define FSMC_SDRAM_MODE_CMD_SELF_REFRESH 5
# define FSMC_SDRAM_MODE_CMD_POWER_DOWN 6
# define FSMC_SDRAM_CMD_BANK_1 0x00000010
# define FSMC_SDRAM_CMD_BANK_2 0x00000008
# define FSMC_SDRAM_AUTO_REFRESH_SHIFT 5
# define FSMC_SDRAM_MODEREG_SHIFT 9
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FSMC_SDRAM_MODEREG_SHIFT)
#endif
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
#include "hardware/stm32_fsmc.h"
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_fsmc_enable
*
* Description:
* Enable clocking to the FSMC.
*
****************************************************************************/
void stm32_fsmc_enable(void);
/****************************************************************************
* Name: stm32_fsmc_disable
*
* Description:
* Disable clocking to the FSMC.
*
****************************************************************************/
void stm32_fsmc_disable(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FSMC_H */

22
configs/fire-stm32v2/src/stm32_selectlcd.c
View File

@ -49,7 +49,6 @@
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "fire-stm32v2.h"
@ -140,25 +139,6 @@ static const uint16_t g_lcdconfig[NCOMMON_CONFIG] =
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* Enable clocking to the FSMC module
*
************************************************************************************/
static inline void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval |= RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/************************************************************************************
* Public Functions
************************************************************************************/
@ -186,7 +166,7 @@ void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */

50
configs/hymini-stm32v/src/stm32_r61505u.c
View File

@ -64,6 +64,10 @@
* Pre-processor Definitions
**************************************************************************************/
#ifndef CONFIG_STM32_FSMC
# error CONFIG_STM32_FSMC is required for LCD support
#endif
/* Color depth and format */
#define LCD_BPP 16
@ -278,48 +282,6 @@ static inline void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
}
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
#ifndef CONFIG_STM32_FSMC
# error CONFIG_STM32_FSMC is required for LCD support
#endif
static void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval |= RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
static void stm32_disablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval &= ~RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/************************************************************************************
* Name: stm32_selectlcd
*
@ -336,7 +298,7 @@ static void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */
@ -379,7 +341,7 @@ static void stm32_deselectlcd(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
/**************************************************************************************

26
configs/hymini-stm32v/src/stm32_ssd1289.c
View File

@ -105,7 +105,6 @@ static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data);
static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power);
static void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
static void stm32_enablefsmc(void);
/**************************************************************************************
* Private Data
@ -372,7 +371,7 @@ static void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */
@ -415,29 +414,6 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
}
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
#ifndef CONFIG_STM32_FSMC
# error CONFIG_STM32_FSMC is required for LCD support
#endif
static void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval |= RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/**************************************************************************************
* Public Functions
**************************************************************************************/

38
configs/mikroe-stm32f4/src/stm32_extmem.c
View File

@ -48,7 +48,6 @@
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "mikroe-stm32f4.h"
@ -148,40 +147,3 @@ void stm32_extmemdata(int ndata)
stm32_extmemgpios(g_dataconfig, ndata);
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Disable AHB clocking to the FSMC */
regval = getreg32(STM32_RCC_AHB3ENR);
regval &= ~RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}

21
configs/olimex-stm32-p407/src/stm32_sram.c
View File

@ -143,25 +143,6 @@ static const uint32_t g_sramconfig[] =
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* Enable clocking to the FSMC module
*
************************************************************************************/
static void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
/************************************************************************************
* Name: stm32_sramgpios
*
@ -220,7 +201,7 @@ void stm32_stram_configure(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration
*

2
configs/stm3210e-eval/README.txt
View File

@ -235,7 +235,7 @@ SRAM3. This memory will appear at address 0x68000000.
The on-board SRAM can be configured by setting
CONFIG_STM32_FSMC=y : Enables the FSMC
CONFIG_STM32_FSMC_SRAM=y : Enable external SRAM support
CONFIG_STM32_EXTERNAL_RAM=y : Enable external SRAM support
CONFIG_HEAP2_BASE=0x68000000 : SRAM will be located at 0x680000000
CONFIG_HEAP2_SIZE=1048576 : The size of the SRAM is 1Mbyte
CONFIG_MM_REGIONS=2 : There will be two memory regions

20
configs/stm3210e-eval/src/stm3210e-eval.h
View File

@ -268,26 +268,6 @@ void stm32_extcontextrestore(struct extmem_save_s *restore);
void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void);
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void);
/************************************************************************************
* Name: stm32_selectnor
*

4
configs/stm3210e-eval/src/stm32_boot.c
View File

@ -71,9 +71,9 @@
void stm32_boardinitialize(void)
{
/* If the FSMC and FSMC_SRAM are selected, then enable SRAM access */
/* If the FSMC and external RAM are selected, then enable SRAM access */
#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_FSMC_SRAM)
#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM)
stm32_selectsram();
#endif

4
configs/stm3210e-eval/src/stm32_deselectlcd.c
View File

@ -42,7 +42,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3210e-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -87,7 +87,7 @@ void stm32_deselectlcd(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

4
configs/stm3210e-eval/src/stm32_deselectnor.c
View File

@ -42,7 +42,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3210e-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -87,7 +87,7 @@ void stm32_deselectnor(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

7
configs/stm3210e-eval/src/stm32_deselectsram.c
View File

@ -42,7 +42,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3210e-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -87,10 +87,7 @@ void stm32_deselectsram(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

39
configs/stm3210e-eval/src/stm32_extmem.c
View File

@ -48,7 +48,6 @@
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "stm3210e-eval.h"
@ -150,41 +149,3 @@ void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
stm32_configgpio(gpios[i]);
}
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval |= RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval &= ~RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}

2
configs/stm3210e-eval/src/stm32_selectlcd.c
View File

@ -122,7 +122,7 @@ void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank4 NOR/SRAM control register configuration */

2
configs/stm3210e-eval/src/stm32_selectnor.c
View File

@ -119,7 +119,7 @@ void stm32_selectnor(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */

2
configs/stm3210e-eval/src/stm32_selectsram.c
View File

@ -122,7 +122,7 @@ void stm32_selectsram(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */

24
configs/stm3220g-eval/README.txt
View File

@ -163,7 +163,7 @@ select CAN1 or CAN2 if fitted; neither if not fitted.
The on-board SRAM can be configured by setting
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_HEAP2_BASE=0x64000000
CONFIG_HEAP2_SIZE=2097152
CONFIG_MM_REGIONS=2
@ -176,15 +176,15 @@ to internal SRAM, SRAM may also be available through the FSMC. In order to
use FSMC SRAM, the following additional things need to be present in the
NuttX configuration file:
CONFIG_STM32_FSMC=y : Enables the FSMC
CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
address space
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
address space
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FSMC SRAM
CONFIG_STM32_FSMC=y : Enables the FSMC
CONFIG_STM32_EXTERNAL_RAM=y : Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
address space
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
address space
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FSMC SRAM
SRAM Configurations
-------------------
@ -194,7 +194,7 @@ There are 2 possible SRAM configurations:
CONFIG_MM_REGIONS == 1
Configuration 2. System SRAM and FSMC SRAM
CONFIG_MM_REGIONS == 2
CONFIG_STM32_FSMC_SRAM defined
CONFIG_STM32_EXTERNAL_RAM defined
I/O Expanders
=============
@ -285,7 +285,7 @@ STM3220G-EVAL-specific Configuration Options
In order to use FSMC SRAM, the following additional things need to be
present in the NuttX configuration file:
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)

24
configs/stm3220g-eval/src/stm3220g-eval.h
View File

@ -341,30 +341,6 @@ void stm32_extmemaddr(int naddrs);
void stm32_extmemdata(int ndata);
#endif
/****************************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_enablefsmc(void);
#endif
/****************************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_disablefsmc(void);
#endif
/****************************************************************************************************
* Name: stm32_selectsram
*

4
configs/stm3220g-eval/src/stm32_deselectlcd.c
View File

@ -43,7 +43,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3220g-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -88,7 +88,7 @@ void stm32_deselectlcd(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

4
configs/stm3220g-eval/src/stm32_deselectsram.c
View File

@ -42,7 +42,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3220g-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -87,7 +87,7 @@ void stm32_deselectsram(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

39
configs/stm3220g-eval/src/stm32_extmem.c
View File

@ -48,7 +48,6 @@
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "stm3220g-eval.h"
@ -147,41 +146,3 @@ void stm32_extmemdata(int ndata)
{
stm32_extmemgpios(g_dataconfig, ndata);
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Disable AHB clocking to the FSMC */
regval = getreg32(STM32_RCC_AHB3ENR);
regval &= ~RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}

2
configs/stm3220g-eval/src/stm32_selectlcd.c
View File

@ -135,7 +135,7 @@ void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Color LCD configuration (LCD configured as follow):
*

2
configs/stm3220g-eval/src/stm32_selectsram.c
View File

@ -149,7 +149,7 @@ void stm32_selectsram(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration
*

28
configs/stm3240g-eval/README.txt
View File

@ -233,7 +233,7 @@ select CAN1 or CAN2 if fitted; neither if not fitted.
The on-board SRAM can be configured by setting
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_HEAP2_BASE=0x64000000
CONFIG_HEAP2_SIZE=2097152
CONFIG_MM_REGIONS=2 (or =3, see below)
@ -251,15 +251,15 @@ In addition to internal SRAM, SRAM may also be available through the FSMC.
In order to use FSMC SRAM, the following additional things need to be
present in the NuttX configuration file:
CONFIG_STM32_FSMC=y : Enables the FSMC
CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
CONFIG_STM32_FSMC=y : Enables the FSMC
CONFIG_STM32_EXTERNAL_RAM=y : Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
address space
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
address space
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FSMC SRAM
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
address space
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FSMC SRAM
SRAM Configurations
-------------------
@ -267,19 +267,19 @@ There are 4 possible SRAM configurations:
Configuration 1. System SRAM (only)
CONFIG_MM_REGIONS == 1
CONFIG_STM32_FSMC_SRAM NOT defined
CONFIG_STM32_EXTERNAL_RAM NOT defined
CONFIG_STM32_CCMEXCLUDE defined
Configuration 2. System SRAM and CCM SRAM
CONFIG_MM_REGIONS == 2
CONFIG_STM32_FSMC_SRAM NOT defined
CONFIG_STM32_EXTERNAL_RAM NOT defined
CONFIG_STM32_CCMEXCLUDE NOT defined
Configuration 3. System SRAM and FSMC SRAM
CONFIG_MM_REGIONS == 2
CONFIG_STM32_FSMC_SRAM defined
CONFIG_STM32_EXTERNAL_RAM defined
CONFIG_STM32_CCMEXCLUDE defined
Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
CONFIG_MM_REGIONS == 3
CONFIG_STM32_FSMC_SRAM defined
CONFIG_STM32_ETXERNAL_RAM defined
CONFIG_STM32_CCMEXCLUDE NOT defined
I/O Expanders
=============
@ -372,7 +372,7 @@ STM3240G-EVAL-specific Configuration Options
In order to use FSMC SRAM, the following additional things need to be
present in the NuttX configuration file:
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)

2
configs/stm3240g-eval/fb/defconfig
View File

@ -64,7 +64,7 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_START_DAY=17
CONFIG_START_MONTH=9
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_I2C1=y
CONFIG_STM32_JTAG_FULL_ENABLE=y
CONFIG_STM32_PWR=y

2
configs/stm3240g-eval/include/board.h
View File

@ -285,7 +285,7 @@
* select CAN1 or CAN2 if fitted; neither if not fitted.
*/
#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_FSMC_SRAM)
#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM)
# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)
# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM"
# endif

2
configs/stm3240g-eval/nxterm/defconfig
View File

@ -92,7 +92,7 @@ CONFIG_SDCLONE_DISABLE=y
CONFIG_STM32_DFU=y
CONFIG_STM32_ETHMAC=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_I2C1=y
CONFIG_STM32_JTAG_FULL_ENABLE=y
CONFIG_STM32_MII=y

24
configs/stm3240g-eval/src/stm3240g-eval.h
View File

@ -370,30 +370,6 @@ void stm32_extmemaddr(int naddrs);
void stm32_extmemdata(int ndata);
#endif
/****************************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_enablefsmc(void);
#endif
/****************************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_disablefsmc(void);
#endif
/****************************************************************************************************
* Name: stm32_selectsram
*

4
configs/stm3240g-eval/src/stm32_deselectlcd.c
View File

@ -43,7 +43,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3240g-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -88,7 +88,7 @@ void stm32_deselectlcd(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

7
configs/stm3240g-eval/src/stm32_deselectsram.c
View File

@ -42,7 +42,7 @@
#include <debug.h>
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32.h"
#include "stm3240g-eval.h"
#ifdef CONFIG_STM32_FSMC
@ -87,10 +87,7 @@ void stm32_deselectsram(void)
/* Disable AHB clocking to the FSMC */
stm32_disablefsmc();
stm32_fsmc_disable();
}
#endif /* CONFIG_STM32_FSMC */

39
configs/stm3240g-eval/src/stm32_extmem.c
View File

@ -48,7 +48,6 @@
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "stm3240g-eval.h"
@ -147,41 +146,3 @@ void stm32_extmemdata(int ndata)
{
stm32_extmemgpios(g_dataconfig, ndata);
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Disable AHB clocking to the FSMC */
regval = getreg32(STM32_RCC_AHB3ENR);
regval &= ~RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}

2
configs/stm3240g-eval/src/stm32_selectlcd.c
View File

@ -135,7 +135,7 @@ void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Color LCD configuration (LCD configured as follow):
*

2
configs/stm3240g-eval/src/stm32_selectsram.c
View File

@ -149,7 +149,7 @@ void stm32_selectsram(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration
*

54
configs/stm32f429i-disco/README.txt
View File

@ -41,7 +41,7 @@ Contents
- Ser
- Timer Inputs/Outputs
- FPU
- FSMC SRAM
- FMC SDRAM
- STM32F429I-DISCO-specific Configuration Options
- Configurations
@ -323,7 +323,7 @@ FMC SDRAM
On-board SDRAM
--------------
The STM32F429I-DISCO has 8 MBytes on-board SDRAM connected to the MCU's
SDRAM Bank 2 connections (Bank 6 of the FSMC). This means the 8 MBytes
SDRAM Bank 2 connections (Bank 6 of the FMC). This means the 8 MiB
(when enabled) is mapped to address 0xD0000000-0xD07FFFFF. The port for
the STM32F429I-DISCO board includes support for using the onboard 8M SDRAM.
@ -336,20 +336,20 @@ to exclude CCM SRAM from the heap:
CONFIG_STM32_CCMEXCLUDE : Exclude CCM SRAM from the HEAP
In addition to internal SRAM, SRAM may also be available through the FSMC.
In order to use FSMC SRAM, the following additional things need to be
In addition to internal SRAM, SRAM may also be available through the FMC.
In order to use FMC SDRAM, the following additional things need to be
present in the NuttX configuration file:
CONFIG_STM32_FSMC=y : Enables the FSMC and the 8MByte SDRAM
CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
address space. This should be 0xD0000000.
CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
address space. This should be 8388608.
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FSMC SDRAM (1, 2 or 3 depending
if the CCM RAM and/or FSCM SDRAM are enabled).
CONFIG_STM32_FMC=y : Enables the FMC and the 8MiB SDRAM
CONFIG_STM32_EXTERNAL_RAM=y : Indicates that RAM is available via the
FMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE : The base address of the RAM in the FMC
address space. This should be 0xD0000000.
CONFIG_HEAP2_SIZE : The size of the RAM in the FMC
address space. This should be 8388608.
CONFIG_MM_REGIONS : Must be set to a large enough value to
include the FMC SDRAM (1, 2 or 3 depending
if the CCM RAM and/or FMC SDRAM are enabled).
SRAM Configurations
--------------------
@ -357,19 +357,19 @@ There are 4 possible SRAM configurations:
Configuration 1. System SRAM (only)
CONFIG_MM_REGIONS == 1
CONFIG_STM32_FSMC_SRAM NOT defined
CONFIG_STM32_EXTERNAL_RAM NOT defined
CONFIG_STM32_CCMEXCLUDE defined
Configuration 2. System SRAM and CCM SRAM
CONFIG_MM_REGIONS == 2
CONFIG_STM32_FSMC_SRAM NOT defined
CONFIG_STM32_EXTERNAL_RAM NOT defined
CONFIG_STM32_CCMEXCLUDE NOT defined
Configuration 3. System SRAM and FSMC SRAM
Configuration 3. System SRAM and FMC SDRAM
CONFIG_MM_REGIONS == 2
CONFIG_STM32_FSMC_SRAM defined
CONFIG_STM32_EXTERNAL_RAM defined
CONFIG_STM32_CCMEXCLUDE defined
Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
Configuration 4. System SRAM, CCM SRAM, and FMC SDRAM
CONFIG_MM_REGIONS == 3
CONFIG_STM32_FSMC_SRAM defined
CONFIG_STM32_EXTERNAL_RAM defined
CONFIG_STM32_CCMEXCLUDE NOT defined
STM32F429I-DISCO-specific Configuration Options
@ -427,16 +427,16 @@ STM32F429I-DISCO-specific Configuration Options
CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
In addition to internal SRAM, SRAM may also be available through the FSMC.
In order to use FSMC SRAM, the following additional things need to be
In addition to internal SRAM, SDRAM may also be available through the FMC.
In order to use FMC SDRAM, the following additional things need to be
present in the NuttX configuration file:
CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
FSMC (as opposed to an LCD or FLASH).
CONFIG_STM32_EXTERNAL_RAM - Indicates that SDRAM is available via the
FMC (as opposed to an LCD or FLASH).
CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
CONFIG_HEAP2_BASE - The base address of the SDRAM in the FMC address space (hex)
CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
CONFIG_HEAP2_SIZE - The size of the SDRAM in the FMC address space (decimal)
CONFIG_ARCH_FPU - The STM32F429I-DISCO supports a floating point unit (FPU)
@ -476,7 +476,7 @@ STM32F429I-DISCO-specific Configuration Options
AHB3
----
CONFIG_STM32_FSMC
CONFIG_STM32_FMC
APB1
----

4
configs/stm32f429i-disco/adc/defconfig
View File

@ -56,8 +56,8 @@ CONFIG_STM32_ADC3=y
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_DMA1=y
CONFIG_STM32_DMA2=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_TIM1=y

4
configs/stm32f429i-disco/extflash/defconfig
View File

@ -58,8 +58,8 @@ CONFIG_STM32F429I_DISCO_FLASH_PART=y
CONFIG_STM32F429I_DISCO_RAMMTD=y
CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_RNG=y

4
configs/stm32f429i-disco/fb/defconfig
View File

@ -66,8 +66,8 @@ CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000
CONFIG_STM32_DMA2D_FB_SIZE=307200
CONFIG_STM32_DMA2D_LAYER_PPLINE=240
CONFIG_STM32_DMA2D_NLAYERS=2
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_I2C3=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_LTDC=y

4
configs/stm32f429i-disco/highpri/defconfig
View File

@ -53,8 +53,8 @@ CONFIG_STM32_ADC_NOIRQ=y
CONFIG_STM32_CCMEXCLUDE=y
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_DMA2=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWM_LL_OPS=y
CONFIG_STM32_PWR=y

8
configs/stm32f429i-disco/include/board.h
View File

@ -248,11 +248,11 @@
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1
/* FSMC - SDRAM */
/* FMC - SDRAM */
#define GPIO_FSMC_SDCKE1 GPIO_FSMC_SDCKE1_1
#define GPIO_FSMC_SDNE1 GPIO_FSMC_SDNE1_1
#define GPIO_FSMC_SDNWE GPIO_FSMC_SDNWE_1
#define GPIO_FMC_SDCKE1 GPIO_FMC_SDCKE1_1
#define GPIO_FMC_SDNE1 GPIO_FMC_SDNE1_1
#define GPIO_FMC_SDNWE GPIO_FMC_SDNWE_1
/* Timer Inputs/Outputs (see the README.txt file for options) */

4
configs/stm32f429i-disco/lcd/defconfig
View File

@ -62,8 +62,8 @@ CONFIG_STM32F429I_DISCO_ILI9341=y
CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y
CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART1=y

4
configs/stm32f429i-disco/lvgl/defconfig
View File

@ -64,8 +64,8 @@ CONFIG_START_YEAR=2017
CONFIG_STM32F429I_DISCO_ILI9341=y
CONFIG_STM32_CCMEXCLUDE=y
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_I2C3=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_LTDC=y

4
configs/stm32f429i-disco/nsh/defconfig
View File

@ -46,8 +46,8 @@ CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART1=y

4
configs/stm32f429i-disco/nxhello/defconfig
View File

@ -67,8 +67,8 @@ CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000
CONFIG_STM32_DMA2D_FB_SIZE=307200
CONFIG_STM32_DMA2D_LAYER_PPLINE=240
CONFIG_STM32_DMA2D_NLAYERS=2
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_LTDC=y
CONFIG_STM32_LTDC_FB_BASE=0xD076A000

4
configs/stm32f429i-disco/nxwm/defconfig
View File

@ -98,8 +98,8 @@ CONFIG_START_MONTH=11
CONFIG_STM32F429I_DISCO_ILI9341=y
CONFIG_STM32_CCMEXCLUDE=y
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_I2C3=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_LTDC=y

2
configs/stm32f429i-disco/src/Makefile
View File

@ -56,7 +56,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CSRCS += stm32_idle.c
endif
ifeq ($(CONFIG_STM32_FSMC),y)
ifeq ($(CONFIG_STM32_FMC),y)
CSRCS += stm32_extmem.c
endif

4
configs/stm32f429i-disco/src/stm32_boot.c
View File

@ -96,8 +96,8 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_STM32_FSMC
stm32_enablefsmc();
#ifdef CONFIG_STM32_FMC
stm32_sdram_initialize();
#endif
#ifdef HAVE_CCM_HEAP

222
configs/stm32f429i-disco/src/stm32_extmem.c
View File

@ -43,69 +43,67 @@
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "stm32_fsmc.h"
#include "stm32_gpio.h"
#include "stm32.h"
#include "stm32f429i-disco.h"
#include <arch/board/board.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifndef CONFIG_STM32_FSMC
# warning "FSMC is not enabled"
#ifndef CONFIG_STM32_FMC
#warning "FMC is not enabled"
#endif
#if STM32_NGPIO_PORTS < 6
# error "Required GPIO ports not enabled"
#error "Required GPIO ports not enabled"
#endif
#define STM32_FSMC_NADDRCONFIGS 22
#define STM32_FSMC_NDATACONFIGS 16
#define STM32_SDRAM_CLKEN FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2
#define STM32_SDRAM_CLKEN FSMC_SDRAM_MODE_CMD_CLK_ENABLE | FSMC_SDRAM_CMD_BANK_2
#define STM32_SDRAM_PALL FSMC_SDRAM_MODE_CMD_PALL | FSMC_SDRAM_CMD_BANK_2
#define STM32_SDRAM_REFRESH FSMC_SDRAM_MODE_CMD_AUTO_REFRESH | FSMC_SDRAM_CMD_BANK_2 |\
(3 << FSMC_SDRAM_AUTO_REFRESH_SHIFT)
#define STM32_SDRAM_MODEREG FSMC_SDRAM_MODE_CMD_LOAD_MODE | FSMC_SDRAM_CMD_BANK_2 |\
FSMC_SDRAM_MODEREG_BURST_LENGTH_2 | \
FSMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
FSMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
FSMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
#define STM32_SDRAM_PALL FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2
#define STM32_SDRAM_REFRESH FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\
FMC_SDCMR_NRFS(4)
#define STM32_SDRAM_MODEREG FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\
FMC_SDCMR_MDR_BURST_LENGTH_2 | \
FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\
FMC_SDCMR_MDR_CAS_LATENCY_3 |\
FMC_SDCMR_MDR_WBL_SINGLE
/************************************************************************************
* Public Data
************************************************************************************/
/* GPIO configurations common to most external memories */
static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] =
{
GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5,
GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11,
GPIO_FSMC_SDCKE1, GPIO_FSMC_SDNE1, GPIO_FSMC_SDNWE, GPIO_FSMC_NBL0,
GPIO_FSMC_SDNRAS, GPIO_FSMC_NBL1, GPIO_FSMC_BA0, GPIO_FSMC_BA1,
GPIO_FSMC_SDCLK, GPIO_FSMC_SDNCAS
};
static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] =
{
GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5,
GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11,
GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15
};
/************************************************************************************
* Private Data
************************************************************************************/
/* GPIO configurations common to most external memories */
static const uint32_t g_sdram_config[] = {
/* 16 data lines */
GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3,
GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7,
GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11,
GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15,
/* 12 address lines */
GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3,
GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7,
GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11,
/* control lines */
GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0,
GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS,
};
#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t))
/************************************************************************************
* Private Functions
************************************************************************************/
@ -115,75 +113,27 @@ static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] =
************************************************************************************/
/************************************************************************************
* Name: stm32_extmemgpios
* Name: stm32_sdram_initialize
*
* Description:
* Initialize GPIOs for external memory usage
* Called from stm32_bringup to initialize external SDRAM access.
*
************************************************************************************/
static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
void stm32_sdram_initialize(void)
{
uint32_t val;
int i;
/* Configure GPIOs */
for (i = 0; i < ngpios; i++)
{
stm32_configgpio(gpios[i]);
}
}
/************************************************************************************
* Name: stm32_sdramcommand
*
* Description:
* Initialize data line GPIOs for external memory access
*
************************************************************************************/
static void stm32_sdramcommand(uint32_t command)
{
uint32_t regval;
volatile uint32_t timeout = 0xFFFF;
regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
while ((regval != 0) && timeout-- > 0)
{
regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
}
putreg32(command, STM32_FSMC_SDCMR);
timeout = 0xFFFF;
regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
while ((regval != 0) && timeout-- > 0)
{
regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
}
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
volatile int count;
/* Enable GPIOs as FSMC / memory pins */
/* Enable GPIOs as FMC / memory pins */
for (i = 0; i < NUM_SDRAM_GPIOS; i++)
{
stm32_configgpio(g_sdram_config[i]);
}
stm32_extmemgpios(g_addressconfig, STM32_FSMC_NADDRCONFIGS);
stm32_extmemgpios(g_dataconfig, STM32_FSMC_NDATACONFIGS);
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
/* Enable AHB clocking to the FMC */
stm32_fmc_enable();
/* Configure and enable the SDRAM bank1
*
@ -191,41 +141,31 @@ void stm32_enablefsmc(void)
* 90MHz = 11,11 ns
* All timings from the datasheet for Speedgrade -7 (=7ns)
*/
val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */
FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */
FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */
FMC_SDCR_NBANKS_4 | /* 4 internal banks */
FMC_SDCR_WIDTH_16 | /* width = 16 bits */
FMC_SDCR_ROWS_12 | /* numrows = 12 */
FMC_SDCR_COLS_8; /* numcols = 8 bits */
stm32_fmc_sdram_set_control(1, val);
stm32_fmc_sdram_set_control(2, val);
putreg32(FSMC_SDRAM_CR_RPIPE_1 |
FSMC_SDRAM_CR_SDCLK_2X |
FSMC_SDRAM_CR_CASLAT_3 |
FSMC_SDRAM_CR_BANKS_4 |
FSMC_SDRAM_CR_WIDTH_16 |
FSMC_SDRAM_CR_ROWBITS_12 |
FSMC_SDRAM_CR_COLBITS_8,
STM32_FSMC_SDCR1);
putreg32(FSMC_SDRAM_CR_RPIPE_1 |
FSMC_SDRAM_CR_SDCLK_2X |
FSMC_SDRAM_CR_CASLAT_3 |
FSMC_SDRAM_CR_BANKS_4 |
FSMC_SDRAM_CR_WIDTH_16 |
FSMC_SDRAM_CR_ROWBITS_12 |
FSMC_SDRAM_CR_COLBITS_8,
STM32_FSMC_SDCR2);
putreg32((2 << FSMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 15ns */
(2 << FSMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 15ns */
(2 << FSMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */
(7 << FSMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 63ns */
(4 << FSMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 42ns */
(7 << FSMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 70ns */
(2 << FSMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */
STM32_FSMC_SDTR2);
val = FMC_SDTR_TRCD(3) | /* tRCD min = 15ns */
FMC_SDTR_TRP(3) | /* tRP min = 15ns */
FMC_SDTR_TWR(3) | /* tWR = 2CLK */
FMC_SDTR_TRC(8) | /* tRC min = 63ns */
FMC_SDTR_TRAS(5) | /* tRAS min = 42ns */
FMC_SDTR_TXSR(8) | /* tXSR min = 70ns */
FMC_SDTR_TMRD(3); /* tMRD = 2CLK */
stm32_fmc_sdram_set_timing(2, val);
/* SDRAM Initialization sequence */
stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
for (count = 0; count < 10000; count++) ; /* Delay */
stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */
for (count = 0; count < 10000; count++); /* Delay */
stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */
stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */
stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */
/* Set refresh count
*
@ -233,30 +173,8 @@ void stm32_enablefsmc(void)
* Refresh_Rate = 7.81us
* Counter = (FMC_CLK * Refresh_Rate) - 20
*/
putreg32(683 << 1, STM32_FSMC_SDRTR);
stm32_fmc_sdram_set_refresh_rate(683);
/* Disable write protection */
// regval = getreg32(STM32_FSMC_SDCR2);
// putreg32(regval & 0xFFFFFDFF, STM32_FSMC_SDCR2);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Disable AHB clocking to the FSMC */
regval = getreg32(STM32_RCC_AHB3ENR);
regval &= ~RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
// stm32_fmc_sdram_write_protect(2, false);
}

26
configs/stm32f429i-disco/src/stm32f429i-disco.h
View File

@ -274,30 +274,16 @@ int stm32_usbhost_initialize(void);
int stm32_tsc_setup(int minor);
#endif
/****************************************************************************
* Name: stm32_enablefsmc
/************************************************************************************
* Name: stm32_sdram_initialize
*
* Description:
* enable clocking to the FSMC module
* Called from stm32_bringup to initialize external SDRAM access.
*
****************************************************************************/
************************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_enablefsmc(void);
#endif
/****************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_disablefsmc(void);
#ifdef CONFIG_STM32_FMC
void stm32_sdram_initialize(void);
#endif
/****************************************************************************

4
configs/stm32f429i-disco/usbmsc/defconfig
View File

@ -50,8 +50,8 @@ CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_OTGHS=y
CONFIG_STM32_PWR=y

4
configs/stm32f429i-disco/usbnsh/defconfig
View File

@ -57,8 +57,8 @@ CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
CONFIG_STM32_FSMC=y
CONFIG_STM32_FSMC_SRAM=y
CONFIG_STM32_FMC=y
CONFIG_STM32_EXTERNAL_RAM=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_OTGHS=y
CONFIG_STM32_PWR=y

38
configs/stm32f4discovery/src/stm32_extmem.c
View File

@ -145,41 +145,3 @@ void stm32_extmemdata(int ndata)
{
stm32_extmemgpios(g_dataconfig, ndata);
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHB3ENR);
regval |= RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
/************************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
void stm32_disablefsmc(void)
{
uint32_t regval;
/* Disable AHB clocking to the FSMC */
regval = getreg32(STM32_RCC_AHB3ENR);
regval &= ~RCC_AHB3ENR_FSMCEN;
putreg32(regval, STM32_RCC_AHB3ENR);
}

2
configs/stm32f4discovery/src/stm32_ssd1289.c
View File

@ -280,7 +280,7 @@ void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Color LCD configuration (LCD configured as follow):
*

24
configs/stm32f4discovery/src/stm32f4discovery.h
View File

@ -594,30 +594,6 @@ void stm32_extmemaddr(int naddrs);
void stm32_extmemdata(int ndata);
#endif
/****************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_enablefsmc(void);
#endif
/****************************************************************************
* Name: stm32_disablefsmc
*
* Description:
* enable clocking to the FSMC module
*
****************************************************************************/
#ifdef CONFIG_STM32_FSMC
void stm32_disablefsmc(void);
#endif
/****************************************************************************
* Name: stm32_led_pminitialize
*

22
configs/viewtool-stm32f107/src/stm32_ssd1289.c
View File

@ -102,7 +102,6 @@ static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data);
static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power);
static void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
static void stm32_enablefsmc(void);
/**************************************************************************************
* Private Data
@ -435,7 +434,7 @@ static void stm32_selectlcd(void)
/* Enable AHB clocking to the FSMC */
stm32_enablefsmc();
stm32_fsmc_enable();
/* Bank1 NOR/SRAM control register configuration */
@ -481,25 +480,6 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
}
}
/************************************************************************************
* Name: stm32_enablefsmc
*
* Description:
* enable clocking to the FSMC module
*
************************************************************************************/
static void stm32_enablefsmc(void)
{
uint32_t regval;
/* Enable AHB clocking to the FSMC */
regval = getreg32( STM32_RCC_AHBENR);
regval |= RCC_AHBENR_FSMCEN;
putreg32(regval, STM32_RCC_AHBENR);
}
/**************************************************************************************
* Public Functions
**************************************************************************************/