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STM32 L4: I2C4 was writing to wrong RCC registers

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This commit is contained in:
Juha Niskanen 2017-06-20 08:04:09 -06:00 committed by Gregory Nutt
parent 47ad81b3e5
commit 2c548a4e58
5 changed files with 29 additions and 9 deletions
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2
arch/arm/src/stm32l4/chip/stm32l4_i2c.h
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@ -259,5 +259,5 @@
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32F30XXX_I2C_H */
#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_I2C_H */

2
arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
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@ -109,7 +109,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

2
arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h
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@ -107,7 +107,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

2
arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
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@ -109,7 +109,7 @@
#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET)
#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET)
#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR)
#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET)
#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET)
#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET)
#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET)

30
arch/arm/src/stm32l4/stm32l4_i2c.c
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@ -1273,7 +1273,7 @@ static inline void stm32l4_i2c_sendstop(FAR struct stm32l4_i2c_priv_s *priv)
* Name: stm32l4_i2c_getstatus
*
* Description:
* Get 32-bit status (SR1 and SR2 combined)
* Get 32-bit status (ISR register)
*
************************************************************************************/
@ -1556,9 +1556,20 @@ static int stm32l4_i2c_init(FAR struct stm32l4_i2c_priv_s *priv)
/* Enable power and reset the peripheral */
modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0);
#ifdef CONFIG_STM32L4_I2C4
if (priv->config->base == STM32L4_I2C4_BASE)
{
modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0);
}
else
#endif
{
modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit);
modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0);
}
/* Configure pins */
@ -1631,7 +1642,16 @@ static int stm32l4_i2c_deinit(FAR struct stm32l4_i2c_priv_s *priv)
/* Disable clocking */
modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0);
#ifdef CONFIG_STM32L4_I2C4
if (priv->config->base == STM32L4_I2C4_BASE)
{
modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0);
}
else
#endif
{
modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0);
}
return OK;
}