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Remove the tail spaces from all files except Documentation

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-02-26 02:14:11 +08:00 committed by Brennan Ashton
parent 528dce4f7f
commit 2c5f653bfd
163 changed files with 634 additions and 651 deletions
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4
CONTRIBUTING.md
View File

@ -14,10 +14,10 @@ it is very important you follow these guidelines:
<first line (up to ~80 characters)>
<more paragraphs here>
* The first line should have a prefix to give context
(unless context is really clear), such as:
<keyword>: <message>
i.e sched: Fixed compiler warning

4
LICENSE
View File

@ -3018,7 +3018,7 @@ arch/arm/src/lc823450/lc823450_sddrv_dep.c
arch/arm/src/lc823450/lc823450_sddrv_if.h
arch/arm/src/lc823450/lc823450_sddrv_type.h
arch/arm/src/lc823450/lc823450_symbols.ld
============================================
============================================
Copyright (C) 2014-2015 ON Semiconductor. All rights reserved.
Copyright 2014,2015,2016,2017 Sony Video & Sound Products Inc.
@ -7199,7 +7199,7 @@ include/sys/queue.h
$NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $
Copyright (c) 1991, 1993
The Regents of the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:

20
ReleaseNotes
View File

@ -30421,7 +30421,7 @@ USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT
```
Change:
```
$(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC)
```
@ -31802,7 +31802,7 @@ NuttX-11.0.0 Release Notes
* [#5966](https://github.com/apache/nuttx/pull/5966) arch:tcbinfo: update tcbinfo as xcpcontext update
* [#5865](https://github.com/apache/nuttx/pull/5865) arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y
* [#5864](https://github.com/apache/nuttx/pull/5864) arch/Toolchain.defs: add wildcard for EXTRA_LIBS
* [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration
* [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration
* [#6105](https://github.com/apache/nuttx/pull/6105) arch/clang: add support for Clang LTO
* [#6089](https://github.com/apache/nuttx/pull/6089) arch: Move group_addrenv to common place
* [#6183](https://github.com/apache/nuttx/pull/6183) arch: Remvoe the error message when toolchain can't find
@ -31815,7 +31815,7 @@ NuttX-11.0.0 Release Notes
* [#6254](https://github.com/apache/nuttx/pull/6254) arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup
* [#6276](https://github.com/apache/nuttx/pull/6276) arch: Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs
* [#6351](https://github.com/apache/nuttx/pull/6351) arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h
* [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context()
* [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context()
* [#6284](https://github.com/apache/nuttx/pull/6284) arch/addrenv: Add missing FAR qualifier to addrenv_mprot
* [#6277](https://github.com/apache/nuttx/pull/6277) arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks
* [#6416](https://github.com/apache/nuttx/pull/6416) Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496
@ -31870,7 +31870,7 @@ NuttX-11.0.0 Release Notes
* [#5983](https://github.com/apache/nuttx/pull/5983) arch/risc-v: Remove the unnecessary inclusion of board header files
* [#5754](https://github.com/apache/nuttx/pull/5754) arch/risc-v: Correct stack coloration in riscv_cpu_boot
* [#5758](https://github.com/apache/nuttx/pull/5758) RISC-V: Prepare CONFIG_BUILD_KERNEL part 1
* [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0
* [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0
* [#5766](https://github.com/apache/nuttx/pull/5766) arch/risc-v: Rework riscv_get_newintctx
* [#5773](https://github.com/apache/nuttx/pull/5773) risc-v/esp32c3: Remove deprecated option for disabling atomics support
* [#5775](https://github.com/apache/nuttx/pull/5775) arch/risc-v: Merge riscv_getnewintctx into common
@ -31934,7 +31934,7 @@ NuttX-11.0.0 Release Notes
* [#6069](https://github.com/apache/nuttx/pull/6069) RISC-V: Add support for CONFIG_BUILD_KERNEL
* [#6005](https://github.com/apache/nuttx/pull/6005) ESP32C3 TWAI (CAN) controller support.
* [#5740](https://github.com/apache/nuttx/pull/5740) Add ethernet support for risc-v/MPFS
* [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
* [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads
* [#5783](https://github.com/apache/nuttx/pull/5783) risc-v/mpfs: usb: fix ep0 read done
* [#5881](https://github.com/apache/nuttx/pull/5881) MPFS: Fix issue with external interrupt detection
* [#5875](https://github.com/apache/nuttx/pull/5875) MPFS: Fix error in flat build linker script
@ -31961,7 +31961,7 @@ NuttX-11.0.0 Release Notes
* [#6530](https://github.com/apache/nuttx/pull/6530) mpfs: Fix IHC memory locations to native width type
* [#6490](https://github.com/apache/nuttx/pull/6490) mpfs: Allow mapping of RAM/ROM regions from different memory areas
* [#6602](https://github.com/apache/nuttx/pull/6602) risc-v/mpfs: usb: fix illegal reads
* [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically
* [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically
* [#6361](https://github.com/apache/nuttx/pull/6361) arch/risc-v: re-add missing riscv_udelay source
* [#6343](https://github.com/apache/nuttx/pull/6343) Some cleanup for risc-v
* [#6342](https://github.com/apache/nuttx/pull/6342) arch/risc-v: Unify common source include
@ -32081,7 +32081,7 @@ NuttX-11.0.0 Release Notes
* [#6379](https://github.com/apache/nuttx/pull/6379) arm/tlsr82: gpio driver bug fix and optimize
* [#6334](https://github.com/apache/nuttx/pull/6334) arm/tlsr82: ble performance optimize and problems solve
* [#6238](https://github.com/apache/nuttx/pull/6238) tlsr82/tc32: optimize the irq process
* [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp
* [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp
* [#6429](https://github.com/apache/nuttx/pull/6429) arch: imx6: Enable imx_idle.c to reduce CPU load
* [#6234](https://github.com/apache/nuttx/pull/6234) arm/tc32/Make.defs: filter-out arm_udelay.c
* [#6736](https://github.com/apache/nuttx/pull/6736) arm/allocateheap: fix multiple definition of 'up_allocate_heap'
@ -32100,9 +32100,9 @@ NuttX-11.0.0 Release Notes
* [#6775](https://github.com/apache/nuttx/pull/6775) arch/stm32/stm32_foc.c: fix some ADC and PWM ifdefs
* [#6769](https://github.com/apache/nuttx/pull/6769) arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips)
* [#6218](https://github.com/apache/nuttx/pull/6218) STM32F746G-Disco, Audiosupport, Bugfix
* [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support
* [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support
* [#6729](https://github.com/apache/nuttx/pull/6729) stm32f7: add showprogress in __start
* [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio
* [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio
* [#6413](https://github.com/apache/nuttx/pull/6413) stm32wl5: add gpio exti support
* [#6426](https://github.com/apache/nuttx/pull/6426) stm32wl5: add flash progmem driver support
* [#6788](https://github.com/apache/nuttx/pull/6788) LPC17xx_40xx PWM multichannel support
@ -32289,7 +32289,7 @@ NuttX-11.0.0 Release Notes
* [#6138](https://github.com/apache/nuttx/pull/6138) boards/boardctl: correct boarctl return value
* [#6141](https://github.com/apache/nuttx/pull/6141) boards/risc-v: Remove "MAXOPTIMIZATION = -Os" from Make.defs
* [#6143](https://github.com/apache/nuttx/pull/6143) boards: Move -fno-common from Make.defs to Toolchain.defs
* [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs
* [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs
* [#6146](https://github.com/apache/nuttx/pull/6146) boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs
* [#6155](https://github.com/apache/nuttx/pull/6155) boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs
* [#6195](https://github.com/apache/nuttx/pull/6195) boards: rv-virt: Add support ELF to nsh and nsh64 defconfigs

2
arch/arm/include/gd32f4/gd32f4xx_irq.h
View File

@ -219,7 +219,7 @@
#elif defined(CONFIG_GD32F4_GD32F405)
# define GD32_IRQ_NEXTINT (82)
# define NR_IRQS (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT)
#else
#else
# error "Unknown GD32F4xx chip!"
#endif

154
arch/arm/src/gd32f4/Kconfig
View File

@ -645,7 +645,7 @@ config GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG
default n
---help---
In debug configuration, disables the WFI instruction in the IDLE loop
to prevent the JTAG from disconnecting.
to prevent the JTAG from disconnecting.
config GD32F4_FORCEPOWER
bool "Force power"
@ -774,8 +774,8 @@ config GD32F4_TIMER0_FDTS
range 0 2
depends on GD32F4_TIMER0_PWM
---help---
The CKDIV bits can be configured by software to specify division ratio
between the timer clock (TIMER_CK) and the dead-time and sampling clock (DTS),
The CKDIV bits can be configured by software to specify division ratio
between the timer clock (TIMER_CK) and the dead-time and sampling clock (DTS),
which is used by the dead-time generators and the digital filters.
config GD32F4_TIMER0_DEADTIME
@ -784,7 +784,7 @@ config GD32F4_TIMER0_DEADTIME
range 0 255
depends on GD32F4_TIMER0_PWM
---help---
This controls the value of the dead-time, which is inserted before the
This controls the value of the dead-time, which is inserted before the
output transitions.
@ -801,7 +801,7 @@ config GD32F4_TIMER0_CH1MODE
range 0 7
depends on GD32F4_TIMER0_CHANNEL0
---help---
This controls the behavior of the output reference signal O0CPRE
This controls the behavior of the output reference signal O0CPRE
which drives CH0_O and CH0_ON.
config GD32F4_TIMER0_CH0O
@ -831,7 +831,7 @@ config GD32F4_TIMER0_CH1MODE
range 0 7
depends on GD32F4_TIMER0_CHANNEL1
---help---
This controls the behavior of the output reference signal O1CPRE
This controls the behavior of the output reference signal O1CPRE
which drives CH1_O and CH1_ON.
config GD32F4_TIMER0_CH1O
@ -861,7 +861,7 @@ config GD32F4_TIMER0_CH2MODE
range 0 7
depends on GD32F4_TIMER0_CHANNEL2
---help---
This controls the behavior of the output reference signal O2CPRE
This controls the behavior of the output reference signal O2CPRE
which drives CH2_O and CH2_ON.
config GD32F4_TIMER0_CH2O
@ -891,7 +891,7 @@ config GD32F4_TIMER0_CH3MODE
range 0 7
depends on GD32F4_TIMER0_CHANNEL3
---help---
This controls the behavior of the output reference signal O3CPRE
This controls the behavior of the output reference signal O3CPRE
which drives CH3_O and CH3_ON.
config GD32F4_TIMER0_CH3O
@ -917,9 +917,9 @@ config GD32F4_TIMER0_ADC
Reserve timer 0 for use by ADC
Timer can be used for different purposes. When the timer0
is intended to be used for ADC conversion, the GD32F4_TIMER0
is intended to be used for ADC conversion, the GD32F4_TIMER0
and GD32F4_ADC should be defined before. There requires two
definition for ADC usage: First, assign which timer is used to
definition for ADC usage: First, assign which timer is used to
trigger the ADC. Second, and configure which ADC to sample.
choice
@ -1020,9 +1020,9 @@ config GD32F4_TIMER0_DAC
Reserve timer 0 for use by DAC
Timer can be used for different purposes. When the timer0
is intended to be used for DAC conversion, the GD32F4_TIMER0
is intended to be used for DAC conversion, the GD32F4_TIMER0
and GD32F4_DAC should be defined before. There requires two
definition for DAC usage: First, assign which timer is used to
definition for DAC usage: First, assign which timer is used to
trigger the DAC. Second, and configure which DAC channel to work.
choice
@ -1050,7 +1050,7 @@ config GD32F4_TIMER0_CAP
---help---
Reserve timer 0 for use by Capture
Timer can be used for different purposes. To capture input is
Timer can be used for different purposes. To capture input is
one of the usual purpose.
@ -1102,7 +1102,7 @@ config GD32F4_ADC0_RESOLUTION
default 0
range 0 3
---help---
ADC0 data resolution. 0: 12 bit, 1: 10 bit,
ADC0 data resolution. 0: 12 bit, 1: 10 bit,
2: 8 bit, 3: 6 bit
config GD32F4_ADC1_RESOLUTION
@ -1111,7 +1111,7 @@ config GD32F4_ADC1_RESOLUTION
default 0
range 0 3
---help---
ADC1 data resolution. 0: 12 bit, 1: 10 bit,
ADC1 data resolution. 0: 12 bit, 1: 10 bit,
2: 8 bit, 3: 6 bit
config GD32F4_ADC2_RESOLUTION
@ -1120,7 +1120,7 @@ config GD32F4_ADC2_RESOLUTION
default 0
range 0 3
---help---
ADC2 data resolution. 0: 12 bit, 1: 10 bit,
ADC2 data resolution. 0: 12 bit, 1: 10 bit,
2: 8 bit, 3: 6 bit
config GD32F4_ADC_MAX_SAMPLES
@ -1128,9 +1128,9 @@ config GD32F4_ADC_MAX_SAMPLES
default 16
---help---
The ADC supports 19 multiplexed channels and two groups: regular and inserted channel group.
The maximum number of samples for regular group can be 16, for inserted channel group
The maximum number of samples for regular group can be 16, for inserted channel group
can be 4.
User can change the default value according to the board initialize. The user should
User can change the default value according to the board initialize. The user should
correctly configure this value.
config GD32F4_ADC_NOINT
@ -1331,7 +1331,7 @@ config GD32F4_DAC0_OUTPUT_BUFFER
depends on GD32F4_DAC0
default y
---help---
DAC0 output buffer configuration
DAC0 output buffer configuration
config GD32F4_DAC0_DATA
int "DAC0 data configuration"
@ -1348,7 +1348,7 @@ config GD32F4_DAC0_TRIG
depends on GD32F4_DAC0
default y
---help---
DAC0 trigger configuration
DAC0 trigger configuration
config GD32F4_DAC0_TRIG_MODE
int "DAC0 trigger source select"
@ -1365,7 +1365,7 @@ config GD32F4_DAC0_TIMER_FREQUENCY
depends on GD32F4_DAC0 && GD32F4_DAC0_TRIG
default 1000
---help---
DAC0 output frequency, only in timer triggrer mode is useful.
DAC0 output frequency, only in timer triggrer mode is useful.
Default: 1000Hz
config GD32F4_DAC0_DMA
@ -1375,10 +1375,10 @@ config GD32F4_DAC0_DMA
---help---
When the external trigger is enabled, the DMA request can be enabled by setting the
DDMAENx bits of the DAC_CTL register. A DMA request will be generated by DAC when an
external hardware trigger (not a software trigger) occurs. The user should note that
external hardware trigger (not a software trigger) occurs. The user should note that
when use DMA.
The timer and output frequency must also be provided to support the DMA transfer,
when the timer is selected to trigger DAC DMA.
when the timer is selected to trigger DAC DMA.
config GD32F4_DAC0_DMA_BUFFER_SIZE
int "DAC0 DMA buffer size"
@ -1390,7 +1390,7 @@ config GD32F4_DAC1_OUTPUT_BUFFER
depends on GD32F4_DAC1
default y
---help---
DAC0 output buffer configuration
DAC0 output buffer configuration
config GD32F4_DAC1_DATA
int "DAC1 data configuration"
@ -1407,7 +1407,7 @@ config GD32F4_DAC1_TRIG
depends on GD32F4_DAC1
default y
---help---
DAC1 trigger configuration
DAC1 trigger configuration
config GD32F4_DAC1_TRIG_MODE
int "DAC1 trigger source select"
@ -1424,7 +1424,7 @@ config GD32F4_DAC1_TIMER_FREQUENCY
depends on GD32F4_DAC1 && GD32F4_DAC1_TRIG
default 1000
---help---
DAC1 output frequency, only in timer triggrer mode is useful.
DAC1 output frequency, only in timer triggrer mode is useful.
Default: 1000Hz
config GD32F4_DAC1_DMA
@ -1434,10 +1434,10 @@ config GD32F4_DAC1_DMA
---help---
When the external trigger is enabled, the DMA request can be enabled by setting the
DDMAENx bits of the DAC_CTL register. A DMA request will be generated by DAC when an
external hardware trigger (not a software trigger) occurs. The user should note that
external hardware trigger (not a software trigger) occurs. The user should note that
when use DMA.
The timer and output frequency must also be provided to support the DMA transfer,
when the timer is selected to trigger DAC DMA.
when the timer is selected to trigger DAC DMA.
config GD32F4_DAC1_DMA_BUFFER_SIZE
int "DAC1 DMA buffer size"
@ -1487,8 +1487,8 @@ config USART0_RS485
default n
---help---
USART0 RS-485 function configuration. If the user configure the RS-485 on
USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition
in board initialization.
USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition
in board initialization.
And it cannot be used with GD32F4_USART0_RXDMA currently.
config USART0_RS485_DIR_POLARITY
@ -1497,7 +1497,7 @@ config USART0_RS485_DIR_POLARITY
range 0 1
depends on USART0_RS485
---help---
Polarity of GPIO_USART0_RS485_DIR pin for RS-485 on USART0.
Polarity of GPIO_USART0_RS485_DIR pin for RS-485 on USART0.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_USART0_RXDMA
@ -1507,7 +1507,7 @@ config GD32F4_USART0_RXDMA
select GD32F4_USART_RXDMA
select USART0_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_USART0_TXDMA
@ -1517,7 +1517,7 @@ config GD32F4_USART0_TXDMA
select GD32F4_USART_TXDMA
select USART0_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmitting data buffer.
endif # GD32F4_USART0_SERIALDRIVER
@ -1546,8 +1546,8 @@ config USART1_RS485
default n
---help---
USART1 RS-485 function configuration. If the user configure the RS-485 on
USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition
in board initialization.
USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition
in board initialization.
And it cannot be used with GD32F4_USART1_RXDMA currently.
config USART1_RS485_DIR_POLARITY
@ -1556,7 +1556,7 @@ config USART1_RS485_DIR_POLARITY
range 0 1
depends on USART1_RS485
---help---
Polarity of GPIO_USART1_RS485_DIR pin for RS-485 on USART1.
Polarity of GPIO_USART1_RS485_DIR pin for RS-485 on USART1.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_USART1_RXDMA
@ -1566,7 +1566,7 @@ config GD32F4_USART1_RXDMA
select GD32F4_USART_RXDMA
select USART1_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_USART1_TXDMA
@ -1576,7 +1576,7 @@ config GD32F4_USART1_TXDMA
select GD32F4_USART_TXDMA
select USART1_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmitting data buffer.
endif # GD32F4_USART1_SERIALDRIVER
@ -1605,8 +1605,8 @@ config USART2_RS485
default n
---help---
USART2 RS-485 function configuration. If the user configure the RS-485 on
USART, the user's should to provide GPIO_USART2_RS485_DIR pin definition
in board initialization.
USART, the user's should to provide GPIO_USART2_RS485_DIR pin definition
in board initialization.
And it cannot be used with GD32F4_USART2_RXDMA currently.
config USART2_RS485_DIR_POLARITY
@ -1615,7 +1615,7 @@ config USART2_RS485_DIR_POLARITY
range 0 1
depends on USART1_RS485
---help---
Polarity of GPIO_USART2_RS485_DIR pin for RS-485 on USART2.
Polarity of GPIO_USART2_RS485_DIR pin for RS-485 on USART2.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_USART2_RXDMA
@ -1625,7 +1625,7 @@ config GD32F4_USART2_RXDMA
select GD32F4_USART_RXDMA
select USART2_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_USART2_TXDMA
@ -1635,7 +1635,7 @@ config GD32F4_USART2_TXDMA
select GD32F4_USART_TXDMA
select USART2_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmitting data buffer.
endif # GD32F4_USART2_SERIALDRIVER
@ -1664,8 +1664,8 @@ config UART3_RS485
default n
---help---
UART3 RS-485 function configuration. If the user configure the RS-485 on
UART, the user's should to provide UART3_RS485_DIR_POLARITY pin definition
in board initialization.
UART, the user's should to provide UART3_RS485_DIR_POLARITY pin definition
in board initialization.
And it cannot be used with GD32F4_UART3_RXDMA currently.
config UART3_RS485_DIR_POLARITY
@ -1674,7 +1674,7 @@ config UART3_RS485_DIR_POLARITY
range 0 1
depends on UART3_RS485
---help---
Polarity of GPIO_UART3_RS485_DIR pin for RS-485 on UART3.
Polarity of GPIO_UART3_RS485_DIR pin for RS-485 on UART3.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_UART3_RXDMA
@ -1684,7 +1684,7 @@ config GD32F4_UART3_RXDMA
select GD32F4_USART_RXDMA
select UART3_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_UART3_TXDMA
@ -1694,7 +1694,7 @@ config GD32F4_UART3_TXDMA
select GD32F4_USART_TXDMA
select UART3_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmit data buffer.
endif # GD32F4_UART3_SERIALDRIVER
@ -1723,8 +1723,8 @@ config UART4_RS485
default n
---help---
UART4 RS-485 function configuration. If the user configure the RS-485 on
UART, the user's should to provide UART4_RS485_DIR_POLARITY pin definition
in board initialization.
UART, the user's should to provide UART4_RS485_DIR_POLARITY pin definition
in board initialization.
And it cannot be used with GD32F4_UART4_RXDMA currently.
config UART4_RS485_DIR_POLARITY
@ -1733,7 +1733,7 @@ config UART4_RS485_DIR_POLARITY
range 0 1
depends on UART4_RS485
---help---
Polarity of GPIO_UART4_RS485_DIR pin for RS-485 on UART4.
Polarity of GPIO_UART4_RS485_DIR pin for RS-485 on UART4.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_UART4_RXDMA
@ -1743,7 +1743,7 @@ config GD32F4_UART4_RXDMA
select GD32F4_USART_RXDMA
select UART4_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_UART4_TXDMA
@ -1753,7 +1753,7 @@ config GD32F4_UART4_TXDMA
select GD32F4_USART_TXDMA
select UART4_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmit data buffer.
endif # GD32F4_UART4_SERIALDRIVER
@ -1782,8 +1782,8 @@ config USART5_RS485
default n
---help---
USART5 RS-485 function configuration. If the user configure the RS-485 on
USART, the user's should to provide GPIO_USART5_RS485_DIR pin definition
in board initialization.
USART, the user's should to provide GPIO_USART5_RS485_DIR pin definition
in board initialization.
And it cannot be used with GD32F4_USART5_RXDMA currently.
config USART5_RS485_DIR_POLARITY
@ -1792,7 +1792,7 @@ config USART5_RS485_DIR_POLARITY
range 0 1
depends on USART1_RS485
---help---
Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5.
Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_USART5_RXDMA
@ -1802,7 +1802,7 @@ config GD32F4_USART5_RXDMA
select GD32F4_USART_RXDMA
select USART5_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_USART5_TXDMA
@ -1812,7 +1812,7 @@ config GD32F4_USART5_TXDMA
select GD32F4_USART_TXDMA
select USART5_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmitting data buffer.
endif # GD32F4_USART5_SERIALDRIVER
@ -1842,8 +1842,8 @@ config UART6_RS485
default n
---help---
UART6 RS-485 function configuration. If the user configure the RS-485 on
UART, the user's should to provide UART6_RS485_DIR_POLARITY pin definition
in board initialization.
UART, the user's should to provide UART6_RS485_DIR_POLARITY pin definition
in board initialization.
And it cannot be used with GD32F4_UART6_RXDMA currently.
config UART6_RS485_DIR_POLARITY
@ -1852,7 +1852,7 @@ config UART6_RS485_DIR_POLARITY
range 0 1
depends on UART6_RS485
---help---
Polarity of GPIO_UART6_RS485_DIR pin for RS-485 on UART6.
Polarity of GPIO_UART6_RS485_DIR pin for RS-485 on UART6.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_UART6_RXDMA
@ -1862,7 +1862,7 @@ config GD32F4_UART6_RXDMA
select GD32F4_USART_RXDMA
select UART6_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_UART6_TXDMA
@ -1872,7 +1872,7 @@ config GD32F4_UART6_TXDMA
select GD32F4_USART_TXDMA
select UART6_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmit data buffer.
endif # GD32F4_UART6_SERIALDRIVER
@ -1902,8 +1902,8 @@ config UART7_RS485
default n
---help---
UART7 RS-485 function configuration. If the user configure the RS-485 on
UART, the user's should to provide UART7_RS485_DIR_POLARITY pin definition
in board initialization.
UART, the user's should to provide UART7_RS485_DIR_POLARITY pin definition
in board initialization.
And it cannot be used with GD32F4_UART7_RXDMA currently.
config UART7_RS485_DIR_POLARITY
@ -1912,7 +1912,7 @@ config UART7_RS485_DIR_POLARITY
range 0 1
depends on UART7_RS485
---help---
Polarity of GPIO_UART7_RS485_DIR pin for RS-485 on UART7.
Polarity of GPIO_UART7_RS485_DIR pin for RS-485 on UART7.
The state on DIR pin: 0 - receive , 1 - transmit.
config GD32F4_UART7_RXDMA
@ -1922,7 +1922,7 @@ config GD32F4_UART7_RXDMA
select GD32F4_USART_RXDMA
select UART7_RXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the receiving data buffer.
config GD32F4_UART7_TXDMA
@ -1932,7 +1932,7 @@ config GD32F4_UART7_TXDMA
select GD32F4_USART_TXDMA
select UART7_TXDMA
---help---
To reduce the burden of the processor in fast data transmit, DMA can be used to
To reduce the burden of the processor in fast data transmit, DMA can be used to
access the transmit data buffer.
endif # GD32F4_UART7_SERIALDRIVER
@ -2003,7 +2003,7 @@ config GD32F4_USART_INVERT
default n
depends on GD32F4_USART0 || GD32F4_USART1 || GD32F4_USART1 || GD32F4_USART5
---help---
Enable signal inversion support for USART RX/TX pin . The option enables
Enable signal inversion support for USART RX/TX pin . The option enables
support for the TIOCSINVERT ioctl in the gd32f4 serial driver.
RX/TX inversion only support for USART0, 1, 2, 5
@ -2161,8 +2161,8 @@ config GD32F4_SPI_DMATHRESHOLD
default 4
depends on GD32F4_SPI_DMA
---help---
When SPI DMA is enabled, if transfers size is less than GD32F4_SPI_DMATHRESHOLD,
the data transfer will still be performed by polling logic.
When SPI DMA is enabled, if transfers size is less than GD32F4_SPI_DMATHRESHOLD,
the data transfer will still be performed by polling logic.
config GD32F4_SPI0_DMA
bool "SPI0 DMA"
@ -2307,7 +2307,7 @@ config GD32F4_MII
bool "Use the media-independent interface (MII) interface"
default n
---help---
Select Ethernet MII interface. The application can only select one of
Select Ethernet MII interface. The application can only select one of
the MII or RMII mode.
choice
@ -2360,9 +2360,9 @@ config GD32F4_PHY_SR
int "PHY Status Register Address (decimal)"
depends on GD32F4_AUTO_NEGOTIATION
---help---
This must be provided if GD32F4_AUTO_NEGOTIATION is defined. Because of the
PHY status register address may different from PHY to PHY, the user should set
the address of the PHY status register according to the PHY on board.
This must be provided if GD32F4_AUTO_NEGOTIATION is defined. Because of the
PHY status register address may different from PHY to PHY, the user should set
the address of the PHY status register according to the PHY on board.
config GD32F4_PHY_SR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
@ -2450,7 +2450,7 @@ config GD32F4_RMII
bool "Use the reduced media-independent interface (RMII) interface"
default y if !GD32F4_MII
---help---
Select Ethernet MII interface. The application can only select one of
Select Ethernet MII interface. The application can only select one of
the MII or RMII mode.
choice
@ -2471,7 +2471,7 @@ config GD32F4_RMII_CKOUT1
config GD32F4_RMII_EXTCLK
bool "External RMII clock"
---help---
Clocking is provided by external clock. And not use CKOUT for
Clocking is provided by external clock. And not use CKOUT for
RMII clock.
endchoice # RMII clock configuration

4
arch/arm/src/gd32f4/gd32f4xx_allocateheap.c
View File

@ -144,9 +144,9 @@
/* Two memory regions. Case 1 or 2 */
# if !defined(CONFIG_GD32F4_TCMEXCLUDE) && defined(CONFIG_GD32F4_EXTERNAL_RAM)
# error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 "
# error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 "
# undef CONFIG_GD32F4_TCMEXCLUDE
# define CONFIG_GD32F4_TCMEXCLUDE 1
# define CONFIG_GD32F4_TCMEXCLUDE 1
# endif
/* Case 1, TCMSRAM is used. In this case, DMA should not be used */

2
arch/arm/src/gd32f4/gd32f4xx_irq.c
View File

@ -129,7 +129,7 @@ static void gd32_dumpnvic(const char *msg, int irq)
getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY),
getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#endif
leave_critical_section(flags);
}

4
arch/arm/src/gd32f4/gd32f4xx_rcu.c
View File

@ -83,7 +83,7 @@
* Pravite Functions
****************************************************************************/
#ifdef GD32_BOARD_SYSCLK_IRC16MEN
#ifdef GD32_BOARD_SYSCLK_IRC16MEN
/****************************************************************************
* Name: gd32_system_clock_irc16m
*
@ -512,7 +512,7 @@ static void gd32_system_clock_pll_hxtal(void)
static void gd32_system_clock_config(void)
{
#ifdef GD32_BOARD_SYSCLK_IRC16MEN
#ifdef GD32_BOARD_SYSCLK_IRC16MEN
/* Select IRC16M as SYSCLK based on board.h setting. */

2
arch/arm/src/gd32f4/gd32f4xx_serial.c
View File

@ -80,7 +80,7 @@
/* USART DMA priority */
#if defined(CONFIG_GD32F4_USART_PRIQ)
# define USART_DMA_PRIO CONFIG_GD32F4_USART_PRIQ
#else
#else
# define USART_DMA_PRIO DMA_PRIO_MEDIUM_SELECT
#endif
#endif

2
arch/arm/src/gd32f4/gd32f4xx_spi.c
View File

@ -99,7 +99,7 @@
#if defined(CONFIG_GD32F4_SPI_PRIQ)
# define SPI_DMA_PRIO CONFIG_GD32F4_SPI_PRIQ
#else
#else
# define SPI_DMA_PRIO DMA_PRIO_MEDIUM_SELECT
#endif

2
arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h
View File

@ -84,7 +84,7 @@
/* Peripheral Base Addresses ************************************************/
#define GD32_APB1_BUS_BASE 0x40000000 /* APB1 base address */
#define GD32_APB1_BUS_BASE 0x40000000 /* APB1 base address */
#define GD32_APB2_BUS_BASE 0x40010000 /* APB2 base address */
#define GD32_AHB1_BUS_BASE 0x40020000 /* AHB1 base address */
#define GD32_AHB2_BUS_BASE 0x50000000 /* AHB2 base address */

2
arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h
View File

@ -530,7 +530,7 @@
#define GPIO_SPI3_SCK_4 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_G|GPIO_CFG_PIN_11)
#define GPIO_SPI4_MISO_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_12)
#define GPIO_SPI4_MISO_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13)
#define GPIO_SPI4_MISO_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13)
#define GPIO_SPI4_MISO_3 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_F|GPIO_CFG_PIN_8)
#define GPIO_SPI4_MISO_4 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_H|GPIO_CFG_PIN_7)
#define GPIO_SPI4_MOSI_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_10)

4
arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h
View File

@ -196,7 +196,7 @@
#define DMA_CHXCTL_TM(n) ((n) << DMA_CHXCTL_TM_SHIFT)
# define DMA_PERIPH_TO_MEMORY DMA_CHXCTL_TM(0) /* 00: read from peripheral and write to memory */
# define DMA_MEMORY_TO_PERIPH DMA_CHXCTL_TM(1) /* 01: read from peripheral and write to memory */
# define DMA_MEMORY_TO_MEMORY DMA_CHXCTL_TM(2) /* 02: read from peripheral and write to memory */
# define DMA_MEMORY_TO_MEMORY DMA_CHXCTL_TM(2) /* 02: read from peripheral and write to memory */
#define DMA_CHXCTL_CMEN (1 << 8) /* Bit 8: circulation mode */
#define DMA_CHXCTL_PNAGA (1 << 9) /* Bit 9: next address generation algorithm of peripheral */
@ -229,7 +229,7 @@
#define DMA_CHXCTL_MBS (1 << 19) /* Bit19: memory buffer select */
#define DMA_CHXCTL_PBURST_SHIFT (21) /* Bit 21-22: transfer burst type of peripheral */
#define DMA_CHXCTL_PBURST_MASK (3 << DMA_CHXCTL_PBURST_SHIFT)
#define DMA_CHXCTL_PBURST_MASK (3 << DMA_CHXCTL_PBURST_SHIFT)
#define DMA_CHXCTL_PBURST(n) ((n) << DMA_CHXCTL_PBURST_SHIFT)
# define DMA_PERIPH_BURST_SINGLE DMA_CHXCTL_PBURST(0) /* single burst */
# define DMA_PERIPH_BURST_4_BEAT DMA_CHXCTL_PBURST(1) /* 4-beat burst */

2
arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h
View File

@ -125,7 +125,7 @@
#define EXTI_17 GD32_EXTI_BIT(17) /* EXTI line 17 */
#define EXTI_18 GD32_EXTI_BIT(18) /* EXTI line 18 */
#define EXTI_19 GD32_EXTI_BIT(19) /* EXTI line 19 */
#define EXTI_20 GD32_EXTI_BIT(20) /* EXTI line 20 */
#define EXTI_20 GD32_EXTI_BIT(20) /* EXTI line 20 */
#define EXTI_21 GD32_EXTI_BIT(21) /* EXTI line 21 */
#define EXTI_22 GD32_EXTI_BIT(22) /* EXTI line 22 */

2
arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h
View File

@ -153,7 +153,7 @@
#define FMC_CTL_SN_SHIFT (3) /* Bits 3-7: select which sector number to be erased */
#define FMC_CTL_SN_MASK (31 << FMC_CTL_SN_SHIFT)
#define FMC_CTL_SN(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */
#define FMC_CTL_SN(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */
#define FMC_CTL_SN_0_11(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */
#define FMC_CTL_SN_12_23(n) ((n+4) << FMC_CTL_SN_SHIFT)) /* Sector n, n=12..23 */
#define FMC_CTL_SN_24_27(n) ((n-12) << FMC_CTL_SN_SHIFT)) /* Sector n, n=24..27 */

8
arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h
View File

@ -297,7 +297,7 @@
#define RCU_AHB1RST_PGRST (1 << 6) /* Bit 6: GPIO port G reset */
#define RCU_AHB1RST_PHRST (1 << 7) /* Bit 7: GPIO port H reset */
#define RCU_AHB1RST_PIRST (1 << 8) /* Bit 8: GPIO port I reset */
#define RCU_AHB1RST_CRCRST (1 << 12) /* Bit 12: CRC reset */
#define RCU_AHB1RST_CRCRST (1 << 12) /* Bit 12: CRC reset */
#define RCU_AHB1RST_DMA0RST (1 << 21) /* Bit 21: DMA0 reset */
#define RCU_AHB1RST_DMA1RST (1 << 22) /* Bit 22: DMA1 reset */
#define RCU_AHB1RST_IPARST (1 << 23) /* Bit 23: IPA reset */
@ -562,13 +562,13 @@
/* PLL clock spread spectrum control register */
#define RCU_PLLSSCTL_MODCNT_SHIFT (0) /* Bit 0-12: These bits configure PLL spread spectrum modulation
#define RCU_PLLSSCTL_MODCNT_SHIFT (0) /* Bit 0-12: These bits configure PLL spread spectrum modulation
* profile amplitude and frequency. The following criteria
* must be met: MODSTEP*MODCNT<=2^15-1 */
#define RCU_PLLSSCTL_MODCNT_MASK (0x1fff << RCU_PLLSSCTL_MODCNT_SHIFT)
# define RCU_PLLSSCTL_MODCNT(n) ((n) << RCU_PLLSSCTL_MODCNT_SHIFT)
#define RCU_PLLSSCTL_MODSTEP_SHIFT (13) /* Bit 13-27: These bits configure PLL spread spectrum modulation
#define RCU_PLLSSCTL_MODSTEP_SHIFT (13) /* Bit 13-27: These bits configure PLL spread spectrum modulation
* profile amplitude and frequency. The following criteria
* must be met: MODSTEP*MODCNT<=2^15-1 */
#define RCU_PLLSSCTL_MODSTEP_MASK (0x7fff << RCU_PLLSSCTL_MODSTEP_SHIFT)
@ -603,7 +603,7 @@
# define RCU_PLLSAI_PLLSAIP_DIV_6 RCU_PLLSAI_PLLSAIP(6)
# define RCU_PLLSAI_PLLSAIP_DIV_8 RCU_PLLSAI_PLLSAIP(8)
#define RCU_PLLSAI_PLLSAIR_SHIFT (28) /* Bits 28-30: The PLLSAI R output frequency division factor
#define RCU_PLLSAI_PLLSAIR_SHIFT (28) /* Bits 28-30: The PLLSAI R output frequency division factor
* from PLLSAI VCO clock */
#define RCU_PLLSAI_PLLSAIR_MASK (7 << RCU_PLLSAI_PLLSAIR_SHIFT)
# define RCU_PLLSAI_PLLSAIR(n) ((n) << RCU_PLLSAI_PLLSAIR_SHIFT) /* n=2..7 */

2
arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h
View File

@ -98,7 +98,7 @@
#define SPI_CTL0_CKPH (1 << 0) /* Bit 0: clock phase selection*/
#define SPI_CTL0_CKPL (1 << 1) /* Bit 1: clock polarity selection */
#define SPI_CTL0_MSTMOD (1 << 2) /* Bit 2: master mode enable */
#define SPI_CTL0_PSC_SHIFT (3) /* Bit 3-5: master clock prescaler selection */
#define SPI_CTL0_PSC_SHIFT (3) /* Bit 3-5: master clock prescaler selection */
#define SPI_CTL0_PSC_MASK (7 << SPI_CTL0_PSC_SHIFT)
#define SPI_CTL0_PSC(n) ((n) << SPI_CTL0_PSC_SHIFT)
# define SPI_CTL0_PSC_2 SPI_CTL0_PSC(0) /* 000: SPI clock prescale factor is 2 */

2
arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h
View File

@ -150,7 +150,7 @@
# define USART_CTL0_PM_ODD USART_CTL0_PMEN(3)
#define USART_WL_9BIT USART_CTL0_WL
#define USART_WL_8BIT (0)
#define USART_WL_8BIT (0)
#define USART_CTL0_INT_SHIFT (4)
#define USART_CTL0_INT_MASK (0x1f << USART_CTL0_INT_SHIFT)

2
arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c
View File

@ -386,7 +386,7 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
LPC17_40_PWM1_MR6); /* Set PWM cycle */
break;
#endif
#endif
default:
{

2
arch/arm/src/nrf52/Kconfig
View File

@ -667,7 +667,7 @@ menuconfig NRF52_SOFTDEVICE_CONTROLLER
depends on NRF52_LFCLK_XTAL
---help---
This enables use of Nordic SoftDevice controller
(SDC). It is a library version of a subset of
(SDC). It is a library version of a subset of
full SoftDevice, which only includes the BLE
controller implementation.

22
arch/arm/src/phy62xx/Make.defs
View File

@ -30,9 +30,9 @@ CHIP_CSRCS += phy62xx_ble.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += phyplus_tim.c
CHIP_CSRCS += phyplus_tim.c
CHIP_CSRCS += phyplus_timer_lowerhalf.c
CHIP_CSRCS += phyplus_timerisr.c
CHIP_CSRCS += phyplus_timerisr.c
endif
ifeq ($(CONFIG_DEV_GPIO),y)
@ -53,15 +53,15 @@ INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble)
CFLAGS += -ffunction-sections
CFLAGS += -DCFG_CP
CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
CFLAGS += -DHOST_CONFIG=4
CFLAGS += -DHCI_TL_NONE=1
CFLAGS += -DMTU_SIZE=247
CFLAGS += -DENABLE_LOG_ROMx=0
CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP
CFLAGS += -DDEBUG_INFO=1
CFLAGS += -DUSE_SYS_TICK
CFLAGS += -DHUGE_MODE=0
CFLAGS += -DHOST_CONFIG=4
CFLAGS += -DHCI_TL_NONE=1
CFLAGS += -DMTU_SIZE=247
CFLAGS += -DENABLE_LOG_ROMx=0
CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP
CFLAGS += -DDEBUG_INFO=1
CFLAGS += -DUSE_SYS_TICK
CFLAGS += -DHUGE_MODE=0
CFLAGS += -DMAX_NUM_LL_CONN=1
CFLAGS += -DUSE_ROMSYM_ALIAS
CFLAGS += -Wno-unused-but-set-variable

6
arch/arm/src/phy62xx/phyplus_gpio.c
View File

@ -38,7 +38,7 @@
#include "phyplus_gpio.h"
#include "errno.h"
#if defined(CONFIG_DEV_GPIO)
#if defined(CONFIG_DEV_GPIO)
/****************************************************************************
* phy6222 internal used functions..
@ -171,7 +171,7 @@ static int phyplus_gpin_read(struct gpio_dev_s *dev, bool *value)
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpioinputs[stm32gpio->id]);
#endif
#endif
struct phyplus_gpio_dev_s *phyplus_gpin =
(struct phyplus_gpio_dev_s *)dev;
@ -195,7 +195,7 @@ static int phyplus_gpout_read(struct gpio_dev_s *dev, bool *value)
gpioinfo("Reading...\n");
*value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]);
#endif
#endif
struct phyplus_gpio_dev_s *phyplus_gpout =
(struct phyplus_gpio_dev_s *)dev;

2
arch/arm/src/phy62xx/phyplus_stub.c
View File

@ -520,7 +520,7 @@ static int phyplus_parse_params_and_action(char *buff)
return -1;
}
}
#if 0
#if 0
else if (0 == strncmp(buff, "reg_timer", 9))
{
p += 10;

2
arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c
View File

@ -114,7 +114,7 @@ static const struct timer_ops_s g_timer_ops =
.getstatus = phyplus_getstatus,
#else
.getstatus = NULL,
#endif
#endif
.settimeout = phyplus_settimeout,
.setcallback = phyplus_setcallback,
#if 1

4
arch/arm/src/rp2040/rp2040_ws2812.pio
View File

@ -13,10 +13,10 @@
;
; clock +-----+-----+-----+-----+-----+-----+-----+-----+-----+
| | T1 | T2 | T3 |
;
;
; +-----------+
; zero-bit | | |
; +-----------------------------------------+
; +-----------------------------------------+
;
; +-----------------------------------+
; one-bit | | |

8
arch/arm/src/s32k1xx/Kconfig
View File

@ -630,15 +630,15 @@ endmenu # eDMA Global Configuration
menu "LPUART Configuration"
depends on S32K1XX_LPUART
config S32K1XX_LPUART_INVERT
bool "Signal Invert Support"
default n
endmenu
endmenu
menu "LPSPI Configuration"
depends on S32K1XX_LPSPI
config S32K1XX_LPSPI_DWORD
bool "DWORD up to 64 bit transfer support"
default n
@ -684,7 +684,7 @@ config S32K1XX_LPSPI_DMATHRESHOLD
config S32K1XX_LPSPI_HWPCS
bool "Use native hardware peripheral chip selects instead of GPIO pins"
default n
endmenu # LPSPI Configuration
menu "LPI2C Configuration"

10
arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h
View File

@ -329,7 +329,7 @@
#define FLEXIO_TIMCTL_PINPOL (1 << 7) /* Bit 7: Timer Pin Polarity (PINPOL) */
# define FLEXIO_TIMCTL_PINPOL_HI (0 << 7) /* Pin is active high */
# define FLEXIO_TIMCTL_PINPOL_LO (1 << 7) /* Pin is active low */
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-10: Timer Pin Select (PINSEL) */
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-10: Timer Pin Select (PINSEL) */
#define FLEXIO_TIMCTL_PINSEL_MASK (0x07 << FLEXIO_TIMCTL_PINSEL_SHIFT)
# define FLEXIO_TIMCTL_PINSEL(n) (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK)
/* Bits 11-15: Reserved */
@ -363,7 +363,7 @@
# define FLEXIO_TIMCFG_TSTART_DIS (0 << 1) /* Start bit disabled */
# define FLEXIO_TIMCFG_TSTART_ENA (1 << 1) /* Start bit enabled */
/* Bits 2-3: Reserved */
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */
#define FLEXIO_TIMCFG_TSTOP_MASK (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT)
# define FLEXIO_TIMCFG_TSTOP_DIS (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */
# define FLEXIO_TIMCFG_TSTOP_TIMCMP (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */
@ -371,7 +371,7 @@
# define FLEXIO_TIMCFG_TSTOP_BOTH (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */
/* Bits 6-7: Reserved */
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */
#define FLEXIO_TIMCFG_TIMENA_MASK (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT)
# define FLEXIO_TIMCFG_TIMENA_ALWAYS (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */
# define FLEXIO_TIMCFG_TIMENA_TIMENA (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */
@ -404,7 +404,7 @@
# define FLEXIO_TIMCFG_TIMRST_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */
/* Bit 19: Reserved */
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-21: Timer Decrement (TIMDEC) */
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-21: Timer Decrement (TIMDEC) */
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT)
# define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */
@ -412,7 +412,7 @@
# define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTRGIN (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Trigger input */
/* Bit 23: Reserved */
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT)
# define FLEXIO_TIMCFG_TIMOUT_ONE (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */
# define FLEXIO_TIMCFG_TIMOUT_ZERO (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */

4
arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h
View File

@ -72,9 +72,9 @@
/* SMC Power Mode Protection register */
#define SMC_PMPROT_AVLP_SHIFT (5) /* Bit 5: Allow Very-Low-Power Modes */
#define SMC_PMPROT_AVLP (1 << SMC_PMPROT_AVLP_SHIFT)
#define SMC_PMPROT_AVLP (1 << SMC_PMPROT_AVLP_SHIFT)
#define SMC_PMPROT_AHSRUN_SHIFT (7) /* Bit 7: Allow High Speed Run mode */
#define SMC_PMPROT_AHSRUN (1 << SMC_PMPROT_AHSRUN_SHIFT)
#define SMC_PMPROT_AHSRUN (1 << SMC_PMPROT_AHSRUN_SHIFT)
/* SMC Power Mode Control register */

31
arch/arm/src/s32k3xx/Kconfig
View File

@ -376,7 +376,7 @@ config S32K3XX_QSPI
default n
select ARCH_USE_MPU
depends on S32K3XX_HAVE_QSPI
menu "FlexCAN"
config S32K3XX_FLEXCAN0
@ -591,7 +591,7 @@ endmenu # LPUART
config S32K3XX_RTC
bool "RTC"
default n
config S32K3XX_FS26
bool "FS26 SBC Disable watchdog"
default n
@ -1085,11 +1085,11 @@ endmenu # eDMA Global Configuration
menu "LPSPI Configuration"
depends on S32K3XX_LPSPI
config S32K3XX_LPSPI_DWORD
bool "DWORD up to 64 bit transfer support"
default n
config S32K3XX_LPSPI_DMA
bool "SPI DMA"
depends on S32K3XX_EDMA
@ -1131,7 +1131,6 @@ config S32K3XX_LPSPI4_DMA
depends on S32K3XX_LPSPI4 && S32K3XX_LPSPI_DMA
---help---
Use DMA to improve LPSPI4 transfer performance.
config S32K3XX_LPSPI5_DMA
bool "LPSPI5 DMA"
@ -1149,13 +1148,13 @@ config S32K3XX_LPSPI_DMATHRESHOLD
When SPI DMA is enabled, small DMA transfers will still be performed
by polling logic. But we need a threshold value to determine what
is small.
config S32K3XX_LPSPI0_PINCFG
int "LPSPI0 input & data pin config"
depends on S32K3XX_LPSPI0
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@ -1166,7 +1165,7 @@ config S32K3XX_LPSPI1_PINCFG
depends on S32K3XX_LPSPI1
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@ -1177,7 +1176,7 @@ config S32K3XX_LPSPI2_PINCFG
depends on S32K3XX_LPSPI2
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@ -1188,7 +1187,7 @@ config S32K3XX_LPSPI3_PINCFG
depends on S32K3XX_LPSPI3
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@ -1199,7 +1198,7 @@ config S32K3XX_LPSPI4_PINCFG
depends on S32K3XX_LPSPI4
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
@ -1210,12 +1209,12 @@ config S32K3XX_LPSPI5_PINCFG
depends on S32K3XX_LPSPI5
default 0
---help---
Configures which pins are used for input and output data during serial transfers.
Configures which pins are used for input and output data during serial transfers.
0 - SIN is used for input data and SOUT is used for output data
1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
3 - SOUT is used for input data and SIN is used for output data
endmenu # LPSPI Configuration
menu "LPI2C Configuration"
@ -1317,15 +1316,15 @@ endmenu # LPI2C Configuration
menu "LPUART Configuration"
depends on S32K3XX_LPUART
config S32K3XX_LPUART_INVERT
bool "Signal Invert Support"
default n
config S32K3XX_LPUART_SINGLEWIRE
bool "Signal Wire Support"
default n
config S32K3XX_SERIAL_RXDMA_BUFFER_SIZE
int "RX DMA buffer size"
default 64

2
arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h
View File

@ -170,7 +170,7 @@
#define S32K3XX_ADC_STAW2R_OFFSET (0x038c) /* Self-Test Analog Watchdog S2 Register (STAW2R) */
#define S32K3XX_ADC_STAW4R_OFFSET (0x0394) /* Self-Test Analog Watchdog C0 Register (STAW4R) */
#define S32K3XX_ADC_STAW5R_OFFSET (0x0398) /* Self-Test Analog Watchdog C Register (STAW5R) */
#define S32K3XX_ADC_AMSIO_OFFSET (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */
#define S32K3XX_ADC_AMSIO_OFFSET (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */
#define S32K3XX_ADC_CALBISTREG_OFFSET (0x03a0) /* Control and Calibration Status Register (CALBISTREG) */
#define S32K3XX_ADC_OFSGNUSR_OFFSET (0x03a8) /* Offset and Gain User Register (OFSGNUSR) */
#define S32K3XX_ADC_CAL2_OFFSET (0x03b4) /* Calibration Value 2 (CAL2) */

14
arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
View File

@ -548,12 +548,12 @@
#define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM1 (PRAM1_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM0 (PRAM0_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
/* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
@ -809,7 +809,7 @@
# define DCM_GPR_DCMRWF5_BOOT_MODE_FAST (1 << 0) /* Fast Standby */
#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT (1) /* Bits 1-31: Cortex-M7_0 base address of vector table to be used after exiting (fast) standby mode (BOOT_ADDRESS) */
#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)
#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)
/* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */

2
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
View File

@ -312,7 +312,7 @@
/* Bits 5-13: Reserved */
#define EMIOS_C2_UCPRECLK (1 << 14) /* Bit 14: Prescaler Clock Source (UCPRECLK) */
/* Bit 15: Reserved */
#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
#define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
#define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
/* Bits 20-31: Reserved */

12
arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
View File

@ -548,7 +548,7 @@
#define S32K3XX_CAN0_ERFIER (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN0_ERFSR (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN0_HR_TIME_STAMP(n) (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN0_HR_TIME_STAMP(n) (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN0_HR_TIME_STAMP0 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN0_HR_TIME_STAMP1 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN0_HR_TIME_STAMP2 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@ -916,7 +916,7 @@
#define S32K3XX_CAN1_ERFIER (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN1_ERFSR (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN1_HR_TIME_STAMP(n) (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN1_HR_TIME_STAMP(n) (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN1_HR_TIME_STAMP0 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN1_HR_TIME_STAMP1 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN1_HR_TIME_STAMP2 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@ -1284,7 +1284,7 @@
#define S32K3XX_CAN2_ERFIER (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN2_ERFSR (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN2_HR_TIME_STAMP(n) (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN2_HR_TIME_STAMP(n) (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN2_HR_TIME_STAMP0 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN2_HR_TIME_STAMP1 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN2_HR_TIME_STAMP2 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@ -1652,7 +1652,7 @@
#define S32K3XX_CAN3_ERFIER (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN3_ERFSR (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN3_HR_TIME_STAMP(n) (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN3_HR_TIME_STAMP(n) (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN3_HR_TIME_STAMP0 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN3_HR_TIME_STAMP1 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN3_HR_TIME_STAMP2 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@ -2020,7 +2020,7 @@
#define S32K3XX_CAN4_ERFIER (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN4_ERFSR (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN4_HR_TIME_STAMP(n) (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN4_HR_TIME_STAMP(n) (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN4_HR_TIME_STAMP0 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN4_HR_TIME_STAMP1 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN4_HR_TIME_STAMP2 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)
@ -2388,7 +2388,7 @@
#define S32K3XX_CAN5_ERFIER (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFIER_OFFSET)
#define S32K3XX_CAN5_ERFSR (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFSR_OFFSET)
#define S32K3XX_CAN5_HR_TIME_STAMP(n) (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
#define S32K3XX_CAN5_HR_TIME_STAMP(n) (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n))
# define S32K3XX_CAN5_HR_TIME_STAMP0 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET)
# define S32K3XX_CAN5_HR_TIME_STAMP1 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET)
# define S32K3XX_CAN5_HR_TIME_STAMP2 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET)

10
arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h
View File

@ -637,7 +637,7 @@
#define FLEXIO_TIMCTL_PINPOL (1 << 7) /* Bit 7: Timer Pin Polarity (PINPOL) */
# define FLEXIO_TIMCTL_PINPOL_HI (0 << 7) /* Pin is active high */
# define FLEXIO_TIMCTL_PINPOL_LO (1 << 7) /* Pin is active low */
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-12: Timer Pin Select (PINSEL) */
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-12: Timer Pin Select (PINSEL) */
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1f << FLEXIO_TIMCTL_PINSEL_SHIFT)
# define FLEXIO_TIMCTL_PINSEL(n) (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK)
/* Bits 13-15: Reserved */
@ -671,7 +671,7 @@
# define FLEXIO_TIMCFG_TSTART_DIS (0 << 1) /* Start bit disabled */
# define FLEXIO_TIMCFG_TSTART_ENA (1 << 1) /* Start bit enabled */
/* Bits 2-3: Reserved */
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */
#define FLEXIO_TIMCFG_TSTOP_MASK (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT)
# define FLEXIO_TIMCFG_TSTOP_DIS (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */
# define FLEXIO_TIMCFG_TSTOP_TIMCMP (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */
@ -679,7 +679,7 @@
# define FLEXIO_TIMCFG_TSTOP_BOTH (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */
/* Bits 6-7: Reserved */
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */
#define FLEXIO_TIMCFG_TIMENA_MASK (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT)
# define FLEXIO_TIMCFG_TIMENA_ALWAYS (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */
# define FLEXIO_TIMCFG_TIMENA_TIMENA (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */
@ -713,7 +713,7 @@
# define FLEXIO_TIMCFG_TIMRST_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */
/* Bit 19: Reserved */
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-22: Timer Decrement (TIMDEC) */
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-22: Timer Decrement (TIMDEC) */
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT)
# define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */
# define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */
@ -725,7 +725,7 @@
# define FLEXIO_TIMCFG_TIMDEC_TRGINRISTRGIN (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input */
/* Bit 23: Reserved */
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT)
# define FLEXIO_TIMCFG_TIMOUT_ONE (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */
# define FLEXIO_TIMCFG_TIMOUT_ZERO (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */

14
arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h
View File

@ -74,7 +74,7 @@
#define S32K3XX_LPI2C0_MDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDER_OFFSET)
#define S32K3XX_LPI2C0_MCFGR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
#define S32K3XX_LPI2C0_MCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
#define S32K3XX_LPI2C0_MCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C0_MCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C0_MCFGR3 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
#define S32K3XX_LPI2C0_MDMR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
#define S32K3XX_LPI2C0_MCCR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
@ -85,7 +85,7 @@
#define S32K3XX_LPI2C0_MRDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
#define S32K3XX_LPI2C0_SCR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCR_OFFSET)
#define S32K3XX_LPI2C0_SSR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SSR_OFFSET)
#define S32K3XX_LPI2C0_SIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C0_SIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C0_SDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SDER_OFFSET)
#define S32K3XX_LPI2C0_SCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
#define S32K3XX_LPI2C0_SCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
@ -103,7 +103,7 @@
#define S32K3XX_LPI2C1_MDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDER_OFFSET)
#define S32K3XX_LPI2C1_MCFGR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET)
#define S32K3XX_LPI2C1_MCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET)
#define S32K3XX_LPI2C1_MCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C1_MCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET)
#define S32K3XX_LPI2C1_MCFGR3 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET)
#define S32K3XX_LPI2C1_MDMR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDMR_OFFSET)
#define S32K3XX_LPI2C1_MCCR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCCR0_OFFSET)
@ -114,7 +114,7 @@
#define S32K3XX_LPI2C1_MRDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MRDR_OFFSET)
#define S32K3XX_LPI2C1_SCR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCR_OFFSET)
#define S32K3XX_LPI2C1_SSR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SSR_OFFSET)
#define S32K3XX_LPI2C1_SIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C1_SIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET)
#define S32K3XX_LPI2C1_SDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SDER_OFFSET)
#define S32K3XX_LPI2C1_SCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET)
#define S32K3XX_LPI2C1_SCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET)
@ -141,7 +141,7 @@
/* Parameter Register (PARAM) */
#define LPI2C_PARAM_MTXFIFO_SHIFT (0) /* Bits 0-3: Master Transmit FIFO Size (MTXFIFO) */
#define LPI2C_PARAM_MTXFIFO_MASK (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)
#define LPI2C_PARAM_MTXFIFO_MASK (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_1_WORDS (0x00 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_2_WORDS (0x01 << LPI2C_PARAM_MTXFIFO_SHIFT)
# define LPI2C_PARAM_MTXFIFO_4_WORDS (0x02 << LPI2C_PARAM_MTXFIFO_SHIFT)
@ -287,7 +287,7 @@
/* Master Config Register 2 (MCFGR2) */
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0) /* Bits 0-11: Bus Idle Timeout (BUSIDLE) */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT)
#define LPI2C_MCFGR2_BUSIDLE_MASK (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT)
#define LPI2C_MCFGR2_BUSIDLE_DISABLE (0x0000 << LPI2C_MCFGR2_BUSIDLE_SHIFT)
# define LPI2C_MCFGR2_BUSIDLE(n) (((n) << LPI2C_MCFGR2_BUSIDLE_SHIFT) & LPI2C_MCFGR2_BUSIDLE_MASK)
/* Bits 12-15: Reserved */
@ -306,7 +306,7 @@
/* Bits 0-7: Reserved */
#define LPI2C_MCFGR3_PINLOW_SHIFT (8) /* Bits 8-19: Pin Low Timeout (PINLOW) */
#define LPI2C_MCFGR3_PINLOW_MASK (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT)
#define LPI2C_MCFGR3_PINLOW_MASK (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT)
# define LPI2C_MCFGR3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFGR3_PINLOW_SHIFT) & LPI2C_MCFGR3_PINLOW_MASK)
/* Bits 20-31: Reserved */

2
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h
View File

@ -173,7 +173,7 @@
#define MC_RGM_FRENTC_FRET_EN (1 << 0) /* Bit 0: Functional Reset Entry Timer Enable (FRET_EN) */
#define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1) /* Bits 1-31: Functional Reset Entry Timer Value (FRET_TIMEOUT) */
#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)
#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)
/* Low Power Debug Control Register (LPDEBUG) */

12
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
View File

@ -418,9 +418,9 @@
#define QSPI_LUT_OPRND0(n) (((n) << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */
#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
@ -431,9 +431,9 @@
#define QSPI_LUT_OPRND1(n) (((n) << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */
# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */
#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)

2
arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h
View File

@ -95,7 +95,7 @@
#define WKPU_NCR_NFEE0 (1 << 25) /* Bit 25: NMI Falling-edge Events Enable 0 (NFEE0) */
#define WKPU_NCR_NREE0 (1 << 26) /* Bit 26: NMI Rising-Edge Events Enable 0 (NREE0) */
/* Bit 27: Reserved */
#define WKPU_NCR_NWRE0 (1 << 28) /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */
#define WKPU_NCR_NWRE0 (1 << 28) /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */
#define WKPU_NCR_NDSS0_SHIFT (29) /* Bits 29-30: NMI Destination Source Select 0 (NDSS0) */
#define WKPU_NCR_NDSS0_MASK (0x03 << WKPU_NCR_NDSS0_SHIFT)
# define WKPU_NCR_NDSS0_NMI (0x00 << WKPU_NCR_NDSS0_SHIFT) /* Non-maskable interrupt */

2
arch/arm/src/s32k3xx/s32k3xx_emac.c
View File

@ -73,7 +73,7 @@
/* Memory synchronization */
#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0)
#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0)
/* If processing is not done at the interrupt level, then work queue support
* is required.

2
arch/arm/src/sama5/sam_flexcom_spi.c
View File

@ -681,7 +681,7 @@ static inline struct sam_flex_spidev_s *flex_spi_dev(struct sam_flex_spics_s
case 4:
return &g_flexcom4dev;
break;
#endif
#endif
default:
/* shouldn't get here */

4
arch/arm/src/sama5/sam_mcan.c
View File

@ -78,7 +78,7 @@
# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_PLLA
# define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_PLLA_FREQUENCY
#elif defined(CONFIG_SAMA5_MCAN_CLKSRC_UPLL)
# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_UPLL
# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_UPLL
# define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_UPLL_FREQUENCY
#elif defined(CONFIG_SAMA5_MCAN_CLKSRC_MCK)
# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_MCK
@ -1016,7 +1016,7 @@ static const struct sam_config_s g_mcan0const =
.pid = SAM_PID_MCAN00,
.irq0 = SAM_IRQ_MCAN00,
.irq1 = SAM_IRQ_MCAN01,
#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1)
#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1)
.mode = MCAN_ISO11898_1_MODE,
#elif defined(CONFIG_SAMA5_MCAN0_FD)
.mode = MCAN_FD_MODE,

2
arch/arm/src/sama5/sam_serial.c
View File

@ -151,7 +151,7 @@
# elif defined(CONFIG_SAMA5_UART4)
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_SAMA5_USART0)
# elif defined(CONFIG_SAMA5_USART0)
# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
# define USART0_ASSIGNED 1
# elif defined(CONFIG_SAMA5_USART1)

2
arch/arm/src/sama5/sam_tsd.c
View File

@ -1564,7 +1564,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv)
* been initialised. It's the only option allowed and that works.
*/
#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED
#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED
/* if we're allowed to use pendet trigger no need to do this */
regval = sam_adc_getreg(priv, SAM_ADC_TRGR);

2
arch/arm/src/sama5/sama5d2x_pio.c
View File

@ -214,7 +214,7 @@ static uint32_t sam_configcommon(pio_pinset_t cfgset)
{
if ((cfgset & PIO_CFG_SLOWCLK) != 0)
{
regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK);
regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK);
}
else
{

2
arch/arm/src/stm32f7/Kconfig
View File

@ -2689,7 +2689,7 @@ config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED
This option configures the stm32_dmacapable to not disqualify
DMA operations on memory that is not dcache aligned based solely
on the starting address and byte count.
Use this when ALL buffer extents are known to be aligned, but the
the count does not use the complete buffer.

2
arch/arm/src/stm32h7/Kconfig
View File

@ -432,7 +432,7 @@ config STM32_APP_FORMAT_MCUBOOT
select STM32_HAVE_OTA_PARTITION
depends on EXPERIMENTAL
---help---
The MCUboot support of loading the firmware images.
The MCUboot support of loading the firmware images.
comment "MCUboot support depends on CONFIG_EXPERIMENTAL"
depends on !EXPERIMENTAL

12
arch/arm/src/stm32l4/stm32l4_adc.h
View File

@ -338,7 +338,7 @@
# if CONFIG_STM32L4_ADC1_EXTTRIG > 0
# define ADC1_EXTCFG_VALUE \
ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL)
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */
@ -352,7 +352,7 @@
# if CONFIG_STM32L4_ADC2_EXTTRIG > 0
# define ADC2_EXTCFG_VALUE \
ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL)
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */
@ -366,7 +366,7 @@
# if CONFIG_STM32L4_ADC3_EXTTRIG > 0
# define ADC3_EXTCFG_VALUE \
ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL)
ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */
@ -387,7 +387,7 @@
# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0
# define ADC1_JEXTCFG_VALUE \
ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL)
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */
@ -399,7 +399,7 @@
# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0
# define ADC2_JEXTCFG_VALUE \
ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL)
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */
@ -411,7 +411,7 @@
# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0
# define ADC3_JEXTCFG_VALUE \
ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL)
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL)
# endif
#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */

2
arch/arm/src/stm32l5/hardware/stm32l5_pwr.h
View File

@ -141,7 +141,7 @@
# define PWR_CR3_RRS_4K_ON (2 << PWE_CR3_RRS_SHIFT) /* 10: Upper 4KB of SRAM2 powered on in Standby-mode */
#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
#define PWR_CR3_ULPMEN (1 << 11) /* Bit 11: Ultra-low-power mode enable */
#define PWR_CR3_UCPD_STBY (1 << 13) /* Bit 13: USB Type-C power delivery Standby-mode */
#define PWR_CR3_UCPD_STBY (1 << 13) /* Bit 13: USB Type-C power delivery Standby-mode */
#define PWR_CR3_UCPD_DBDIS (1 << 14) /* Bit 14: USB Type-C power delivery dead battery disable */
/* Power control register 4 */

2
arch/arm/src/stm32u5/hardware/stm32_flash.h
View File

@ -228,7 +228,7 @@
#define FLASH_NSCR_PNB_MASK (0x7F << FLASH_NSCR_PNB_SHIFT)
#define FLASH_NSCR_PNB(n) ((n) << FLASH_NSCR_PNB_SHIFT) /* Page n, n = 0..127 */
#define FLASH_NSCR_BKER (1 << 11) /* Bit 11: Non-secure bank selection for page erase */
#define FLASH_NSCR_BWR (1 << 14) /* Bit 14: Non-secure burst write programming mode */
#define FLASH_NSCR_BWR (1 << 14) /* Bit 14: Non-secure burst write programming mode */
#define FLASH_NSCR_MER2 (1 << 15) /* Bit 15: Non-secure bank 2 mass erase */
#define FLASH_NSCR_STRT (1 << 16) /* Bit 16: Non-secure start */
#define FLASH_NSCR_OPTSTRT (1 << 17) /* Bit 17: Options modification start */

2
arch/arm/src/stm32u5/hardware/stm32_pwr.h
View File

@ -180,7 +180,7 @@
/* PWR Disable backup domain register */
#define PWR_DBPR_DBP (1 << 0) /* Bit 0: Disable Backup domain write protection. */
#define PWR_DBPR_DBP (1 << 0) /* Bit 0: Disable Backup domain write protection. */
/* PWR Supply voltage monitoring status register */

12
arch/arm/src/stm32wb/Kconfig
View File

@ -348,7 +348,7 @@ config STM32WB_SRAM2A_INIT
memory can trigger parity faults from the random data. This can be
avoided by first writing to all locations to force the parity into a valid
state.
However, if the SRAM2a is being retained in Standby mode, this may be
However, if the SRAM2a is being retained in Standby mode, this may be
undesirable (because it will destroy the contents). In that case, the board
should handle the initialization itself at the appropriate time.
@ -359,7 +359,7 @@ config STM32WB_SRAM2B_HEAP
config STM32WB_SRAM2B_USER_SIZE
int "SRAM2b user application size"
default 32768
range 0 32768
range 0 32768
depends on STM32WB_SRAM2B_HEAP
---help---
For any CPU2 firmware supporting the BLE protocol the ending part of
@ -1013,7 +1013,7 @@ config STM32WB_BLE_SLAVE_SCA
---help---
Sleep clock accuracy (ppm value) in slave mode.
choice
choice
prompt "Sleep clock accuracy in master mode"
default STM32WB_BLE_MASTER_SCA_0
---help---
@ -1056,7 +1056,7 @@ config STM32WB_BLE_MASTER_SCA
default 1 if STM32WB_BLE_MASTER_SCA_1
default 0
choice
choice
prompt "Low speed clock source"
default STM32WB_BLE_LS_CLK_SRC_LSE
---help---
@ -1112,7 +1112,7 @@ config STM32WB_BLE_CHAN_SEL_ALG2
bool "Enable channel selection algorithm 2"
default n
choice
choice
prompt "Power class"
default STM32WB_BLE_POWER_CLASS_2_3
@ -1134,7 +1134,7 @@ config STM32WB_BLE_MAX_TX_POWER
range -127 20
default 0
choice
choice
prompt "AGC RSSI model"
default STM32WB_BLE_AGC_RSSI_LEGACY

10
arch/arm/src/tiva/Kconfig
View File

@ -1522,17 +1522,17 @@ menu "CAN Driver Configuration"
choice
prompt "CAN bus driver selection"
default TIVA_SOCKET_CAN
config TIVA_SOCKET_CAN
bool "Use SocketCAN driver"
depends on (TIVA_CAN0 || TIVA_CAN1) && NET_CAN
select NET_CAN_HAVE_ERRORS
config TIVA_CHAR_DEV_CAN
bool "Character device driver"
depends on (TIVA_CAN0 || TIVA_CAN1) && !NET_CAN
select ARCH_HAVE_CAN_ERRORS
endchoice # CAN driver selection
config TIVA_CAN0_PRIO
@ -1544,12 +1544,12 @@ config TIVA_CAN0_PRIO
than in the ISR or using a work queue. The ISR signals the
kthread, but the kthread can be preempted if needed. This
option sets the thread priority for CAN module 0.
config TIVA_CAN0_BAUD
int "CAN0 baud rate kb/s"
default 125
depends on TIVA_CAN0 && TIVA_SOCKET_CAN
config TIVA_CAN1_BAUD
int "CAN1 baud rate kb/s"
default 125

2
arch/arm64/src/common/arm64_gic.h
View File

@ -110,7 +110,7 @@
#define GICD_TYPER_RSS BIT(26)
#define GICD_TYPER_LPIS BIT(17)
#define GICD_TYPER_MBIS BIT(16)
#define GICD_TYPER_ESPI BIT(8)
#define GICD_TYPER_ESPI BIT(8)
#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
#define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)

2
arch/avr/src/at32uc3/Make.defs
View File

@ -29,7 +29,7 @@ CMN_CSRCS = avr_allocateheap.c avr_copystate.c avr_createstack.c avr_exit.c
CMN_CSRCS += avr_mdelay.c avr_udelay.c avr_initialize.c avr_initialstate.c avr_idle.c
CMN_CSRCS += avr_modifyreg8.c avr_modifyreg16.c avr_modifyreg32.c avr_releasestack.c
CMN_CSRCS += avr_schedulesigaction.c avr_sigdeliver.c avr_stackframe.c avr_switchcontext.c
CMN_CSRCS += avr_usestack.c avr_doirq.c avr_nputs.c avr_registerdump.c avr_getintstack.c
CMN_CSRCS += avr_usestack.c avr_doirq.c avr_nputs.c avr_registerdump.c avr_getintstack.c
# Required AT32UC3 files

2
arch/renesas/src/rx65n/rx65n_usbhost.c
View File

@ -2856,7 +2856,7 @@ void usb_hstd_brdy_pipe_process(uint16_t bitsts)
(NULL == g_rx65n_edlist[i].xfrinfo->callback))
#else
if (i == g_kbdpipe)
#endif
#endif
{
usb_cstd_clr_stall(i);
}

2
arch/renesas/src/sh1/Make.defs
View File

@ -24,7 +24,7 @@ CMN_CSRCS = renesas_allocateheap.c renesas_createstack.c renesas_doirq.c
CMN_CSRCS += renesas_exit.c renesas_getintstack.c renesas_initialize.c
CMN_CSRCS += renesas_idle.c renesas_initialstate.c renesas_lowputs.c
CMN_CSRCS += renesas_mdelay.c renesas_nputs.c renesas_releasestack.c
CMN_CSRCS += renesas_stackframe.c renesas_switchcontext.c renesas_udelay.c
CMN_CSRCS += renesas_stackframe.c renesas_switchcontext.c renesas_udelay.c
CMN_CSRCS += renesas_usestack.c sh1_schedulesigaction.c sh1_sigdeliver.c
CHIP_ASRCS = sh1_vector.S sh1_saveusercontext.S

6
arch/risc-v/include/esp32c6/irq.h
View File

@ -107,9 +107,9 @@
#define ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH 59 /* interrupt of system timer 2, EDGE */
#define ESP32C6_APB_ADC_PERIPH 60 /* interrupt of APB ADC, level */
#define ESP32C6_MCPWM0_PERIPH 61 /* interrupt of MCPWM0, level */
#define ESP32C6_PCNT_PERIPH 62
#define ESP32C6_PCNT_PERIPH 62
#define ESP32C6_PARL_IO_PERIPH 63
#define ESP32C6_SLC0_PERIPH 64
#define ESP32C6_SLC0_PERIPH 64
#define ESP32C6_SLC_PERIPH 65
#define ESP32C6_DMA_IN_CH0_PERIPH 66 /* interrupt of general DMA IN channel 0, level */
#define ESP32C6_DMA_IN_CH1_PERIPH 67 /* interrupt of general DMA IN channel 1, level */
@ -117,7 +117,7 @@
#define ESP32C6_DMA_OUT_CH0_PERIPH 69 /* interrupt of general DMA OUT channel 0, level */
#define ESP32C6_DMA_OUT_CH1_PERIPH 70 /* interrupt of general DMA OUT channel 1, level */
#define ESP32C6_DMA_OUT_CH2_PERIPH 71 /* interrupt of general DMA OUT channel 2, level */
#define ESP32C6_GSPI2_PERIPH 72
#define ESP32C6_GSPI2_PERIPH 72
#define ESP32C6_AES_PERIPH 73 /* interrupt of AES accelerator, level */
#define ESP32C6_SHA_PERIPH 74 /* interrupt of SHA accelerator, level */
#define ESP32C6_RSA_PERIPH 75 /* interrupt of RSA accelerator, level */

2
arch/risc-v/src/bl602/bl602_lowputc.c
View File

@ -52,7 +52,7 @@
****************************************************************************/
#define UART_PARITY_NONE (0)
#define UART_PARITY_ODD (1)
#define UART_PARITY_ODD (1)
#define UART_PARITY_EVEN (2)
/* Select UART parameters for the selected console */

68
arch/risc-v/src/bl602/hardware/bl602_uart.h
View File

@ -76,41 +76,41 @@
#define BL602_UART_FIFO_WDATA(n) (BL602_UART_BASE(n) + BL602_UART_FIFO_WDATA_OFFSET)
#define BL602_UART_FIFO_RDATA(n) (BL602_UART_BASE(n) + BL602_UART_FIFO_RDATA_OFFSET)
#define BL602_UART0_UTX_CONFIG (BL602_UART_UTX_CONFIG(0))
#define BL602_UART0_URX_CONFIG (BL602_UART_URX_CONFIG(0))
#define BL602_UART0_UART_BIT_PRD (BL602_UART_BIT_PRD(0))
#define BL602_UART0_DATA_CONFIG (BL602_UART_DATA_CONFIG(0))
#define BL602_UART0_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(0))
#define BL602_UART0_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(0))
#define BL602_UART0_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(0))
#define BL602_UART0_UART_INT_STS (BL602_UART_INT_STS(0))
#define BL602_UART0_UART_INT_MASK (BL602_UART_INT_MASK(0))
#define BL602_UART0_UART_INT_CLEAR (BL602_UART_INT_CLEAR(0))
#define BL602_UART0_UART_INT_EN (BL602_UART_INT_EN(0))
#define BL602_UART0_UART_STATUS (BL602_UART_STATUS(0))
#define BL602_UART0_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(0))
#define BL602_UART0_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(0))
#define BL602_UART0_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(0))
#define BL602_UART0_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(0))
#define BL602_UART0_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(0))
#define BL602_UART0_UTX_CONFIG (BL602_UART_UTX_CONFIG(0))
#define BL602_UART0_URX_CONFIG (BL602_UART_URX_CONFIG(0))
#define BL602_UART0_UART_BIT_PRD (BL602_UART_BIT_PRD(0))
#define BL602_UART0_DATA_CONFIG (BL602_UART_DATA_CONFIG(0))
#define BL602_UART0_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(0))
#define BL602_UART0_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(0))
#define BL602_UART0_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(0))
#define BL602_UART0_UART_INT_STS (BL602_UART_INT_STS(0))
#define BL602_UART0_UART_INT_MASK (BL602_UART_INT_MASK(0))
#define BL602_UART0_UART_INT_CLEAR (BL602_UART_INT_CLEAR(0))
#define BL602_UART0_UART_INT_EN (BL602_UART_INT_EN(0))
#define BL602_UART0_UART_STATUS (BL602_UART_STATUS(0))
#define BL602_UART0_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(0))
#define BL602_UART0_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(0))
#define BL602_UART0_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(0))
#define BL602_UART0_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(0))
#define BL602_UART0_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(0))
#define BL602_UART1_UTX_CONFIG (BL602_UART_UTX_CONFIG(1))
#define BL602_UART1_URX_CONFIG (BL602_UART_URX_CONFIG(1))
#define BL602_UART1_UART_BIT_PRD (BL602_UART_BIT_PRD(1))
#define BL602_UART1_DATA_CONFIG (BL602_UART_DATA_CONFIG(1))
#define BL602_UART1_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(1))
#define BL602_UART1_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(1))
#define BL602_UART1_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(1))
#define BL602_UART1_UART_INT_STS (BL602_UART_INT_STS(1))
#define BL602_UART1_UART_INT_MASK (BL602_UART_INT_MASK(1))
#define BL602_UART1_UART_INT_CLEAR (BL602_UART_INT_CLEAR(1))
#define BL602_UART1_UART_INT_EN (BL602_UART_INT_EN(1))
#define BL602_UART1_UART_STATUS (BL602_UART_STATUS(1))
#define BL602_UART1_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(1))
#define BL602_UART1_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(1))
#define BL602_UART1_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(1))
#define BL602_UART1_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(1))
#define BL602_UART1_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(1))
#define BL602_UART1_UTX_CONFIG (BL602_UART_UTX_CONFIG(1))
#define BL602_UART1_URX_CONFIG (BL602_UART_URX_CONFIG(1))
#define BL602_UART1_UART_BIT_PRD (BL602_UART_BIT_PRD(1))
#define BL602_UART1_DATA_CONFIG (BL602_UART_DATA_CONFIG(1))
#define BL602_UART1_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(1))
#define BL602_UART1_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(1))
#define BL602_UART1_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(1))
#define BL602_UART1_UART_INT_STS (BL602_UART_INT_STS(1))
#define BL602_UART1_UART_INT_MASK (BL602_UART_INT_MASK(1))
#define BL602_UART1_UART_INT_CLEAR (BL602_UART_INT_CLEAR(1))
#define BL602_UART1_UART_INT_EN (BL602_UART_INT_EN(1))
#define BL602_UART1_UART_STATUS (BL602_UART_STATUS(1))
#define BL602_UART1_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(1))
#define BL602_UART1_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(1))
#define BL602_UART1_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(1))
#define BL602_UART1_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(1))
#define BL602_UART1_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(1))
/* Register bit definitions *************************************************/

4
arch/risc-v/src/common/Make.defs
View File

@ -28,12 +28,12 @@ CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_mhartid.S
# Specify C code within the common directory to be included
CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c
CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_copystate.c
CMN_CSRCS += riscv_cpuidlestack.c riscv_doirq.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_cpuidlestack.c riscv_doirq.c riscv_exit.c riscv_exception.c
CMN_CSRCS += riscv_getnewintctx.c riscv_getintstack.c riscv_initialstate.c
CMN_CSRCS += riscv_idle.c riscv_modifyreg32.c riscv_nputs.c riscv_releasestack.c
CMN_CSRCS += riscv_registerdump.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_switchcontext.c riscv_saveusercontext.c
CMN_CSRCS += riscv_usestack.c riscv_tcbinfo.c
CMN_CSRCS += riscv_usestack.c riscv_tcbinfo.c
ifneq ($(CONFIG_ALARM_ARCH),y)
ifneq ($(CONFIG_TIMER_ARCH),y)

2
arch/risc-v/src/common/Toolchain.defs
View File

@ -133,7 +133,7 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
ARCHRVISAA = a
ZARCHRVISAA := +a
endif
ifeq ($(CONFIG_ARCH_RV_ISA_C),y)
ARCHRVISAC = c
ZARCHRVISAC := +c

8
arch/risc-v/src/esp32c3/esp32c3_ledc.c
View File

@ -62,9 +62,9 @@
# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
# define LEDC_TIM0_CHANS CONFIG_ESP32C3_LEDC_TIM0_CHANNELS
# else
# define LEDC_TIM0_CHANS (1)
# define LEDC_TIM0_CHANS (1)
# endif
# define LEDC_TIM0_CHANS_OFF (0)
# define LEDC_TIM0_CHANS_OFF (0)
#endif
/* LEDC timer1 channels and offset */
@ -75,7 +75,7 @@
# else
# define LEDC_TIM1_CHANS (1)
# endif
# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS)
# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS)
#endif
/* LEDC timer2 channels and offset */
@ -100,7 +100,7 @@
/* LEDC timer max clock divider parameter */
#define LEDC_CLKDIV_MAX (1024) /* 2^10 */
#define LEDC_CLKDIV_MAX (1024) /* 2^10 */
/* LEDC timer registers mapping */

2
arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c
View File

@ -46,7 +46,7 @@
#define ESP_IW_EVENT_SIZE(field) \
(offsetof(struct iw_event, u) + sizeof(((union iwreq_data *)0)->field))
#ifdef CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE
#ifdef CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE
# define WIFI_SCAN_RESULT_SIZE CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE
#else
# define WIFI_SCAN_RESULT_SIZE (4096)

2
arch/risc-v/src/k210/k210_head.S
View File

@ -75,7 +75,7 @@ __start:
/*
* sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE
*
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/

2
arch/risc-v/src/litex/Kconfig
View File

@ -41,7 +41,7 @@ config LITEX_USE_CUSTOM_IRQ_DEFINITIONS
---help---
Use custom definitions for risc-v IRQ numbers and sequence.
Allowing for the definitions in arch/risc-v/include/litex/irq.h to be overridden.
if LITEX_USE_CUSTOM_IRQ_DEFINITIONS
config LITEX_CUSTOM_IRQ_DEFINITIONS_PATH

2
arch/risc-v/src/litex/litex_pwm.c
View File

@ -45,7 +45,7 @@
#error PWM puslecount not supported for Litex.
#endif
#ifdef CONFIG_PWM_MULTICHAN
#error PWM multichannel not supported for Litex.
#error PWM multichannel not supported for Litex.
#endif
/* Control register offsets from peripheral base address */

2
arch/risc-v/src/mpfs/Kconfig
View File

@ -130,7 +130,7 @@ choice
prompt "Choose DDR type"
depends on MPFS_DDR_INIT
default MPFS_DDR_TYPE_LPDDR4
config MPFS_DDR_TYPE_DDR3
bool "Use DDR3"

2
arch/risc-v/src/qemu-rv/qemu_rv_head.S
View File

@ -86,7 +86,7 @@ __start:
/*
* sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE
*
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/

2
arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h
View File

@ -156,7 +156,7 @@
#define LPUART_CTRL_RIE (1 << 21) /* Bit21: Receiver Interrupt Enable */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit20: Idle Line Interrupt Enable */
#define LPUART_CTRL_TE (1 << 19) /* Bit19: Transmitter Enable */
#define LPUART_CTRL_RE (1 << 18) /* Bit18: Receiver Enable */
#define LPUART_CTRL_RE (1 << 18) /* Bit18: Receiver Enable */
#define LPUART_CTRL_RWU (1 << 17) /* Bit17: Receiver Wakeup Control */
#define LPUART_CTRL_SBK (1 << 16) /* Bit16: Send Break */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit15: Match 1 Interrupt Enable */

2
arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h
View File

@ -92,7 +92,7 @@
/* Register Bitfield Definitions ********************************************/
#define PCC_CLKCFG_PCD_SHIFT (0)
#define PCC_CLKCFG_PCD_MASK (7 << PCC_CLKCFG_PCD_SHIFT)
#define PCC_CLKCFG_PCD_MASK (7 << PCC_CLKCFG_PCD_SHIFT)
#define PCC_CLKCFG_PCD_DIV1 (0 << PCC_CLKCFG_PCD_SHIFT)
#define PCC_CLKCFG_PCD_DIV2 (1 << PCC_CLKCFG_PCD_SHIFT)
#define PCC_CLKCFG_PCD_DIV3 (2 << PCC_CLKCFG_PCD_SHIFT)

2
arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h
View File

@ -44,7 +44,7 @@
# define RV32M1_WDOG_BASE RV32M1_WDOG0_BASE
#elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY)
# define RV32M1_WDOG_BASE RV32M1_WDOG1_BASE
#else
#else
# error "Unsupported RV32M1 Watch dog"
#endif

2
arch/risc-v/src/rv32m1/rv32m1_linker.h
View File

@ -52,7 +52,7 @@
# define LOCATE_ITCM locate_code(SECTION_ITCM) /* System ITCM */
# define LOCATE_UITCM locate_code(SECTION_UITCM) /* User ITCM */
#else
# define LOCATE_ITCM
# define LOCATE_ITCM
# define LOCATE_UITCM
#endif

2
arch/risc-v/src/rv32m1/rv32m1_serial.c
View File

@ -64,7 +64,7 @@ struct rv32m1_tty_s
#ifdef USE_SERIALDRIVER
#ifdef HAVE_UART
#ifdef HAVE_UART
#if defined(CONFIG_RV32M1_LPUART0)
# define RV32M1_LPUART0_DEV g_uart0dev

14
arch/sparc/src/bm3803/bm3803-uart.h
View File

@ -128,17 +128,17 @@
: (UART_CONTROL &= ~(MSK_UART_ENABLE_RXIT | MSK_UART_ENABLE_TXIT))\
) \
) \
)
)
#define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON \
? (BM3803_REG.uart_ctrl1 |= MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl1 &= ~MSK_UART_ENABLE_FLOW) \
)
)
#define uart1_loopback_config(uart_loopb) ( uart_loopb == ON \
? (BM3803_REG.uart_ctrl1 |= MSK_UART_LOOPBACK) \
: (BM3803_REG.uart_ctrl1 &= ~MSK_UART_LOOPBACK) \
)
)
#define uart1_enable() (BM3803_REG.uart_ctrl1 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
#define uart1_disable() (BM3803_REG.uart_ctrl1 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
@ -161,12 +161,12 @@
#define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON \
? (BM3803_REG.uart_ctrl2 |= MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl2 &= ~MSK_UART_ENABLE_FLOW) \
)
)
#define uart2_loopback_config(uart_loopb) ( uart_loopb == ON \
? (BM3803_REG.uart_ctrl2 |= MSK_UART_LOOPBACK) \
: (BM3803_REG.uart_ctrl2 &= ~MSK_UART_LOOPBACK) \
)
)
#define uart2_enable() (BM3803_REG.uart_ctrl2 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
#define uart2_disable() (BM3803_REG.uart_ctrl2 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
@ -189,12 +189,12 @@
#define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON \
? (BM3803_REG.uart_ctrl3 |= MSK_UART_ENABLE_FLOW) \
: (BM3803_REG.uart_ctrl3 &= ~MSK_UART_ENABLE_FLOW) \
)
)
#define uart3_loopback_config(uart_loopb) ( uart_loopb == ON \
? (BM3803_REG.uart_ctrl3 |= MSK_UART_LOOPBACK) \
: (BM3803_REG.uart_ctrl3 &= ~MSK_UART_LOOPBACK) \
)
)
#define uart3_enable() (BM3803_REG.uart_ctrl3 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
#define uart3_disable() (BM3803_REG.uart_ctrl3 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))

6
arch/sparc/src/s698pm/s698pm-uart.h
View File

@ -144,17 +144,17 @@
(reg &= ~(MSK_UART_ENABLE_RXIT | MSK_UART_ENABLE_TXIT)) \
) \
) \
)
)
#define uart_flow_ctrl_config(reg, uart_flow) ((uart_flow == ON) ? \
(reg |= MSK_UART_ENABLE_FLOW) : \
(reg &= ~MSK_UART_ENABLE_FLOW) \
)
)
#define uart_loopback_config(reg, uart_loopb) ((uart_loopb == ON) ? \
(reg |= MSK_UART_LOOPBACK) : \
(reg &= ~MSK_UART_LOOPBACK) \
)
)
#define uart_enable(reg) (reg |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))
#define uart_disable(reg) (reg &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX))

2
arch/sparc/src/s698pm/s698pm_exceptions.S
View File

@ -242,7 +242,7 @@ fix_pil:
cmp %l4, %g0
be do_irq
nop
add %l4, 240, %l3 ! l3 = extended vector number
add %l4, 240, %l3 ! l3 = extended vector number
do_irq:
! o1 = 2nd arg = address of the ISF
! WAS LOADED WHEN ISF WAS SAVED!!!

6
arch/sparc/src/sparc_v8/sparc_v8_syscall.S
View File

@ -164,9 +164,9 @@ sys_call5: /* %o0 holds the syscall number, arguments in %o1, %o2, %o3, %o4 and
/* Issue the ECALL opcode to perform a SW interrupt to the OS */
ta 8; ! syscall 8
nop;
nop;
nop;
nop;
nop;
nop;
jmp %o7 + 8
nop

2
arch/xtensa/src/common/xtensa_panic.S
View File

@ -132,7 +132,7 @@ _xtensa_panic:
ps_setup XCHAL_EXCM_LEVEL a0
/* Call C panic handler:
/* Call C panic handler:
* Arg1 = Exception code.
* Arg2 = Start of the register save area.
*/

2
arch/xtensa/src/esp32/esp32_wifi_utils.c
View File

@ -46,7 +46,7 @@
#define ESP_IW_EVENT_SIZE(field) \
(offsetof(struct iw_event, u) + sizeof(((union iwreq_data *)0)->field))
#ifdef CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE
#ifdef CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE
# define WIFI_SCAN_RESULT_SIZE CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE
#else
# define WIFI_SCAN_RESULT_SIZE (4096)

2
arch/xtensa/src/esp32s2/esp32s2_freerun.c
View File

@ -46,7 +46,7 @@
****************************************************************************/
#define MAX_TIMERS 4
#define MAX_US_RESOLUTION 819 /* MAX_US = (PREmax * USEC_PER_SEC) / CLKmin */
#define MAX_US_RESOLUTION 819 /* MAX_US = (PREmax * USEC_PER_SEC) / CLKmin */
#define TIMER_WIDTH 64
/****************************************************************************

2
arch/z80/src/ez80/Toolchain.defs
View File

@ -52,7 +52,7 @@ ARCHSTDINCLUDES =
ARCHCPUFLAGS = -Dinterrupt="__attribute__((__interrupt__))" -ffreestanding
ARCHCPUFLAGS += -Wa,-march=ez80
ARCHLIST =
ARCHLIST =
ARCHWARNINGS = -Wall -Wextra -Wno-incompatible-library-redeclaration
ARCHWARNINGS += -Wno-main-return-type -Wno-unused-parameter
ARCHWARNINGS += -Wno-invalid-noreturn -Wimplicit-int-conversion

8
boards/arm/gd32f4/gd32f450zk-eval/include/board.h
View File

@ -65,7 +65,7 @@
#ifndef CONFIG_GD32F4_BOARD_HXTAL_VALUE
# define GD32_BOARD_HXTAL 25000000ul
#else
#else
# define GD32_BOARD_HXTAL CONFIG_GD32F4_BOARD_HXTAL_VALUE
#endif
@ -270,7 +270,7 @@ typedef enum
# define DMA_CHANNEL_USART0_RX DMA_REQ_USART0_RX_1
#endif
#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA)
#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA)
# define USART_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE)
#endif
@ -319,12 +319,12 @@ typedef enum
# define GPIO_SPI0_SCK_PIN ((GPIO_SPI0_SCK_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ)
#endif
#ifdef CONFIG_GD32F4_SPI0_DMA
#ifdef CONFIG_GD32F4_SPI0_DMA
# define DMA_CHANNEL_SPI0_TX DMA_REQ_SPI0_TX_1
# define DMA_CHANNEL_SPI0_RX DMA_REQ_SPI0_RX_1
#endif
#ifdef CONFIG_GD32F4_SPI_DMA
#ifdef CONFIG_GD32F4_SPI_DMA
# define SPI_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE)
#endif

2
boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c
View File

@ -69,7 +69,7 @@
* Private Functions
****************************************************************************/
#if defined (CONFIG_IMXRT_USDHC) && (CONFIG_TEENSY_41)
#if defined (CONFIG_IMXRT_USDHC) && (CONFIG_TEENSY_41)
static int nsh_sdmmc_initialize(void)
{
struct sdio_dev_s *sdmmc;

48
boards/arm/phy62xx/phy6222/scripts/flash.ld
View File

@ -37,17 +37,16 @@ SECTIONS
} > flash
__exidx_end = ABSOLUTE(.);
._sjtblsstore : {
_sjtblss = ABSOLUTE(.);
} > flash
} > flash
.jumptbls : {
_sjtbls = ABSOLUTE(.);
*jump_table*(.jumptbls)
_ejtbls = ABSOLUTE(.);
} > jumptbl AT >flash
.gcfgtbls : {
_sgtbls = ABSOLUTE(.);
*jump_table*(.gcfgtbls)
@ -56,7 +55,7 @@ SECTIONS
._eronlystore : {
_eronly = ABSOLUTE(.);
} > flash
} > flash
.data : {
_sdata = ABSOLUTE(.);
@ -87,7 +86,6 @@ SECTIONS
//*libarch.a:phy62xx_ble_patch.o(.text.ll_processBasicIRQ_ScanTRX0)
//*libarch.a:phy62xx_ble_patch.o(.text.ll_processBasicIRQ_SRX0)
//*libarch.a:phy62xx_ble_patch.o(.text.ll_hw_read_rfifo1)
*libphy6222_rf.a:patch.o(.text.ll_hw_go1)
*libphy6222_rf.a:patch.o(.text.TIM1_IRQHandler1)
@ -110,7 +108,6 @@ SECTIONS
*libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_ScanTRX0)
*libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_SRX0)
*libphy6222_rf.a:patch.o(.text.ll_hw_read_rfifo1)
*libphy6222_rf.a:patch.o(.text.LL_set_default_conn_params1)
*libphy6222_rf.a:patch.o(.text.llConnTerminate1)
*libphy6222_rf.a:patch.o(.text.config_RTC1)
@ -125,17 +122,17 @@ SECTIONS
*libphy6222_rf.a:patch.o(.text.llSetupSecAdvEvt1)
*libphy6222_rf.a:patch.o(.text.ll_scheduler2)
*libphy6222_rf.a:patch.o(.text.llSetupNextSlaveEvent1)
*libapps.a:flash.c.*.o(.text .text.*)
*libapps.a:*.o(.text.drv_disable_irq1)
*libapps.a:*.o(.text.drv_enable_irq1)
*libapps.a:flash.c.*.o(.text .text.*)
*libapps.a:*.o(.text.drv_disable_irq1)
*libapps.a:*.o(.text.drv_enable_irq1)
*rf_phy_driver.o(.text.rf_phy_get_pktFoot)
*rf_phy_driver.o(.text.rf_phy_change_cfg0 )
*libphy6222_host.a:l2cap_util.o(.text.L2CAP_Fragment_SendDataPkt)
*libphy6222_host.a:l2cap_util.o(.text.l2capSegmentBuffToLinkLayer)
*libphy6222_host.a:l2cap_util.o(.text.l2capPocessFragmentTxData)
*libarch.a:phy62xx_ble_hcitl.o(.text.phy62xx_ble_init)
*libarch.a:phy62xx_ble_hcitl.o(.text.HCI_ProcessEvent1)
*libarch.a:up_idle.o(.text .text.*)
@ -149,7 +146,6 @@ SECTIONS
*libarch.a:arm_doirq.o(.text.arm_doirq )
*libarch.a:phy62xx_hardfault.o(.text.arm_hardfault )
*libsched.a:irq_dispatch.o(.text.irq_dispatch )
*libsched.a:clock_initialize.o(.text.clock_timer)
*libsched.a:sched_processtimer.o(.text.nxsched_process_timer)
*libsched.a:sem_wait.o(.text .text.*)
@ -157,28 +153,27 @@ SECTIONS
*libsched.a:sched_yield.o(.text .text.*)
*libsched.a:sched_lock.o(.text .text.*)
*libsched.a:sched_unlock.o(.text .text.*)
*libdrivers.a:uart_bth4.o(.text.uart_bth4_pollnotify)
*libdrivers.a:uart_bth4.o(.text.uart_bth4_post)
*libdrivers.a:uart_bth4.o(.text.uart_bth4_receive)
*libarch.a:uart.o(.text .text.*)
*libarch.a:uart.o(.text .text.*)
*libmm.a:circbuf.o(.text .text.*)
*libc.a:lib_libvsprintf.o(.text .text.*)
*libc.a:lib_printf.o(.text .text.*)
*libc.a:lib_vfprintf.o(.text .text.*)
*libc.a:lib_skipspace.o(.text .text.*)
*libc.a:lib_libvsprintf.o(.text .text.*)
*libc.a:lib_printf.o(.text .text.*)
*libc.a:lib_vfprintf.o(.text .text.*)
*libc.a:lib_skipspace.o(.text .text.*)
*libc.a:lib_sprintf.o(.text .text.*)
*libc.a:lib_strlen.o(.text .text.*)
*libc.a:lib_memcmp.o(.text .text.*)
*libc.a:lib_memcpy.o(.text .text.*)
*libc.a:lib_memset.o(.text .text.*)
*libc.a:lib_memmove.o(.text .text.*)
*libapps.a:zblue.o(.text.k_yield .text.k_sleep .text.z_tick_get)
*libapps.a:zblue.o(.text.k_yield .text.k_sleep .text.z_tick_get)
_etextram = ABSOLUTE(.);
@ -197,7 +192,7 @@ SECTIONS
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
.common_text : {
*(.text .text.*)
*(.rodata .rodata.*)
@ -211,9 +206,8 @@ SECTIONS
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
_etext = ABSOLUTE(.);
} > flash
} > flash
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }

10
boards/arm/rp2040/adafruit-feather-rp2040/README.txt
View File

@ -83,7 +83,7 @@ Defconfigs
- nshsram
Load NuttX binary to SRAM
- smp
Enable SMP mode. Both Core 0 and Core 1 are used by NuttX.
@ -95,8 +95,8 @@ Defconfigs
VCC ----- 3V3 OUT (Pin 36)
SDA ----- GP4 (I2C0 SDA) (Pin 6)
SCL ----- GP5 (I2C0 SCL) (Pin 7)
- lcd1602
- lcd1602
LCD 1602 Segment LCD Disaply (I2C)
Connection:
PCF8574 BackPack Raspberry Pi Pico
@ -119,7 +119,7 @@ Defconfigs
* Card hot swapping is not supported.
- st7735
st7735 SPI LCD support
st7735 SPI LCD support
Connection:
st7735 Raspberry Pi Pico
GND ----- GND (Pin 3 or 38 or ...)
@ -129,7 +129,7 @@ Defconfigs
CS ----- GP13 (SPI1 CSn) (Pin 17)
AO(D/C) ----- GP12 (SPI1 RX) (Pin 16)
BL ----- GP11 (Pin 15)
RESET ----- GP10 (Pin 14)
RESET ----- GP10 (Pin 14)
- enc28j60
ENC28J60 SPI ethernet controller support

4
boards/arm/rp2040/adafruit-feather-rp2040/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
@ -81,7 +81,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

10
boards/arm/rp2040/adafruit-kb2040/README.txt
View File

@ -82,7 +82,7 @@ Defconfigs
- nshsram
Load NuttX binary to SRAM
- smp
Enable SMP mode. Both Core 0 and Core 1 are used by NuttX.
@ -94,8 +94,8 @@ Defconfigs
VCC ----- 3V3 OUT (Pin 36)
SDA ----- GP4 (I2C0 SDA) (Pin 6)
SCL ----- GP5 (I2C0 SCL) (Pin 7)
- lcd1602
- lcd1602
LCD 1602 Segment LCD Disaply (I2C)
Connection:
PCF8574 BackPack Raspberry Pi Pico
@ -118,7 +118,7 @@ Defconfigs
* Card hot swapping is not supported.
- st7735
st7735 SPI LCD support
st7735 SPI LCD support
Connection:
st7735 Raspberry Pi Pico
GND ----- GND (Pin 3 or 38 or ...)
@ -128,7 +128,7 @@ Defconfigs
CS ----- GP13 (SPI1 CSn) (Pin 17)
AO(D/C) ----- GP12 (SPI1 RX) (Pin 16)
BL ----- GP11 (Pin 15)
RESET ----- GP10 (Pin 14)
RESET ----- GP10 (Pin 14)
- enc28j60
ENC28J60 SPI ethernet controller support

4
boards/arm/rp2040/adafruit-kb2040/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
}
@ -75,7 +75,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

4
boards/arm/rp2040/adafruit-qt-py-rp2040/README.txt
View File

@ -2,7 +2,7 @@ README
======
This directory contains the port of NuttX to the Adafruit QT Py RP2040.
See https://learn.adafruit.com/adafruit-qt-py-2040 for information
See https://learn.adafruit.com/adafruit-qt-py-2040 for information
about Adafruit QT Py RP2040.
NuttX supports the following RP2040 capabilities:
@ -77,7 +77,7 @@ Defconfigs
- nshsram
Load NuttX binary to SRAM
- smp
Enable SMP mode. Both Core 0 and Core 1 are used by NuttX.

4
boards/arm/rp2040/adafruit-qt-py-rp2040/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
}
@ -75,7 +75,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

2
boards/arm/rp2040/pimoroni-tiny2040/README.txt
View File

@ -81,7 +81,7 @@ Defconfigs
- nshsram
Load NuttX binary to SRAM
- smp
Enable SMP mode. Both Core 0 and Core 1 are used by NuttX.

4
boards/arm/rp2040/pimoroni-tiny2040/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
@ -91,7 +91,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

2
boards/arm/rp2040/raspberrypi-pico-w/include/board.h
View File

@ -62,7 +62,7 @@
/* GPIO definitions *********************************************************/
#undef BOARD_GPIO_LED_PIN
#undef BOARD_GPIO_LED_PIN
#define BOARD_NGPIOOUT 1
#define BOARD_NGPIOIN 1
#define BOARD_NGPIOINT 1

6
boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs
View File

@ -63,11 +63,11 @@ $(FIRMWARE_SRC):
$(FIRMWARE): $(FIRMWARE_SRC)
$(call CATFILE, $(FIRMWARE), $(FIRMWARE_SRC))
src$(DELIM)rp2040_firmware.c: $(FIRMWARE)
src$(DELIM)rp2040_firmware.c: $(FIRMWARE)
#depend: $(FIRMWARE)
#depend: $(FIRMWARE)
distclean::
distclean::
$(call DELFILE, src$(DELIM)cyw43439.firmware.image)
endif

4
boards/arm/rp2040/raspberrypi-pico-w/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
}
@ -75,7 +75,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

10
boards/arm/rp2040/raspberrypi-pico/README.txt
View File

@ -83,7 +83,7 @@ Defconfigs
- nshsram
Load NuttX binary to SRAM
- smp
Enable SMP mode. Both Core 0 and Core 1 are used by NuttX.
@ -95,8 +95,8 @@ Defconfigs
VCC ----- 3V3 OUT (Pin 36)
SDA ----- GP4 (I2C0 SDA) (Pin 6)
SCL ----- GP5 (I2C0 SCL) (Pin 7)
- lcd1602
- lcd1602
LCD 1602 Segment LCD Disaply (I2C)
Connection:
PCF8574 BackPack Raspberry Pi Pico
@ -119,7 +119,7 @@ Defconfigs
* Card hot swapping is not supported.
- st7735
st7735 SPI LCD support
st7735 SPI LCD support
Connection:
st7735 Raspberry Pi Pico
GND ----- GND (Pin 3 or 38 or ...)
@ -129,7 +129,7 @@ Defconfigs
CS ----- GP13 (SPI1 CSn) (Pin 17)
AO(D/C) ----- GP12 (SPI1 RX) (Pin 16)
BL ----- GP11 (Pin 15)
RESET ----- GP10 (Pin 14)
RESET ----- GP10 (Pin 14)
- enc28j60
ENC28J60 SPI ethernet controller support

4
boards/arm/rp2040/raspberrypi-pico/src/rp2040_boardinitialize.c
View File

@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_earlyinitialize();
#endif
#endif
/* --- Place any board specific early initialization here --- */
@ -81,7 +81,7 @@ void rp2040_boardinitialize(void)
{
#ifdef CONFIG_ARCH_BOARD_COMMON
rp2040_common_initialize();
#endif
#endif
/* --- Place any board specific initialization here --- */
}

4
boards/arm/s32k1xx/rddrone-bms772/README.txt
View File

@ -9,7 +9,7 @@ available. It contains additional drivers and example software to use
most features of the battery management system.
This application is currently published in a separate repository, but
(parts) may eventually be upstreamed to Apache NuttX:
(parts) may eventually be upstreamed to Apache NuttX:
https://github.com/NXPHoverGames/RDDRONE-BMS772
@ -87,7 +87,7 @@ Thread-Aware Debugging with Eclipse
Thread-aware debugging is possible with openocd-nuttx
( https://github.com/sony/openocd-nuttx ) and was tested together with the
Eclipse-based S32 Design Studio for Arm:
Eclipse-based S32 Design Studio for Arm:
https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM
NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1.

2
boards/arm/s32k1xx/rddrone-bms772/scripts/rddrone-bms772.jlink
View File

@ -4,7 +4,7 @@
// J-Link Command File for connecting to RDDRONE-BMS772 with a J-Link debugger and flashing a compiled NuttX binary.
//
// The script can be executed by entering the command: JLinkExe -CommandFile rddrone-bms772.jlink
// Note that the current working directory needs to be /boards/arm/s32k1xx/rddrone-bms772/scripts/
// Note that the current working directory needs to be /boards/arm/s32k1xx/rddrone-bms772/scripts/
//
usb

2
boards/arm/s32k1xx/s32k144evb/README.txt
View File

@ -102,7 +102,7 @@ Thread-Aware Debugging with Eclipse
Thread-aware debugging is possible with openocd-nuttx
( https://github.com/sony/openocd-nuttx ) and was tested together with the
Eclipse-based S32 Design Studio for Arm:
Eclipse-based S32 Design Studio for Arm:
https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM
NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1.

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