diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 3825b4f675..0f2da53386 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -14,10 +14,10 @@ it is very important you follow these guidelines: - + * The first line should have a prefix to give context (unless context is really clear), such as: - + : i.e sched: Fixed compiler warning diff --git a/LICENSE b/LICENSE index 2309023a0c..6e8377a163 100644 --- a/LICENSE +++ b/LICENSE @@ -3018,7 +3018,7 @@ arch/arm/src/lc823450/lc823450_sddrv_dep.c arch/arm/src/lc823450/lc823450_sddrv_if.h arch/arm/src/lc823450/lc823450_sddrv_type.h arch/arm/src/lc823450/lc823450_symbols.ld -============================================ +============================================ Copyright (C) 2014-2015 ON Semiconductor. All rights reserved. Copyright 2014,2015,2016,2017 Sony Video & Sound Products Inc. @@ -7199,7 +7199,7 @@ include/sys/queue.h $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ Copyright (c) 1991, 1993 The Regents of the University of California. All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/ReleaseNotes b/ReleaseNotes index c1af9b1c00..07e4732e4f 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -30421,7 +30421,7 @@ USER_LDFLAGS = -Wl,--undefined=$(ENTRYPT) -Wl,--entry=$(ENTRYPT) $(USER_LDSCRIPT ``` Change: - + ``` $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) ``` @@ -31802,7 +31802,7 @@ NuttX-11.0.0 Release Notes * [#5966](https://github.com/apache/nuttx/pull/5966) arch:tcbinfo: update tcbinfo as xcpcontext update * [#5865](https://github.com/apache/nuttx/pull/5865) arch: Add -fsanitize=kernel-address to ARCHCPUFLAGS if CONFIG_MM_KASAN=y * [#5864](https://github.com/apache/nuttx/pull/5864) arch/Toolchain.defs: add wildcard for EXTRA_LIBS - * [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration + * [#5920](https://github.com/apache/nuttx/pull/5920) ARCH_ADDRENV: Add guard against mis-configuration * [#6105](https://github.com/apache/nuttx/pull/6105) arch/clang: add support for Clang LTO * [#6089](https://github.com/apache/nuttx/pull/6089) arch: Move group_addrenv to common place * [#6183](https://github.com/apache/nuttx/pull/6183) arch: Remvoe the error message when toolchain can't find @@ -31815,7 +31815,7 @@ NuttX-11.0.0 Release Notes * [#6254](https://github.com/apache/nuttx/pull/6254) arch: Remove board/libboard$(LIBEXT) from the rerequest of export_startup * [#6276](https://github.com/apache/nuttx/pull/6276) arch: Move "-nostartfiles -nodefaultlibs" from Make.defs to Toolchian.defs * [#6351](https://github.com/apache/nuttx/pull/6351) arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h - * [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context() + * [#6286](https://github.com/apache/nuttx/pull/6286) arch: inline up_interrupt_context() * [#6284](https://github.com/apache/nuttx/pull/6284) arch/addrenv: Add missing FAR qualifier to addrenv_mprot * [#6277](https://github.com/apache/nuttx/pull/6277) arch/i2c: Change xxx_i2c_tousecs to xxx_i2c_toticks * [#6416](https://github.com/apache/nuttx/pull/6416) Fix CONFIG_ALLSYMS for arm, risc-v and xtensa after #5496 @@ -31870,7 +31870,7 @@ NuttX-11.0.0 Release Notes * [#5983](https://github.com/apache/nuttx/pull/5983) arch/risc-v: Remove the unnecessary inclusion of board header files * [#5754](https://github.com/apache/nuttx/pull/5754) arch/risc-v: Correct stack coloration in riscv_cpu_boot * [#5758](https://github.com/apache/nuttx/pull/5758) RISC-V: Prepare CONFIG_BUILD_KERNEL part 1 - * [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0 + * [#5760](https://github.com/apache/nuttx/pull/5760) ESP32-S3: Fix UART IRQ setup hardcoded to CPU 0 * [#5766](https://github.com/apache/nuttx/pull/5766) arch/risc-v: Rework riscv_get_newintctx * [#5773](https://github.com/apache/nuttx/pull/5773) risc-v/esp32c3: Remove deprecated option for disabling atomics support * [#5775](https://github.com/apache/nuttx/pull/5775) arch/risc-v: Merge riscv_getnewintctx into common @@ -31934,7 +31934,7 @@ NuttX-11.0.0 Release Notes * [#6069](https://github.com/apache/nuttx/pull/6069) RISC-V: Add support for CONFIG_BUILD_KERNEL * [#6005](https://github.com/apache/nuttx/pull/6005) ESP32C3 TWAI (CAN) controller support. * [#5740](https://github.com/apache/nuttx/pull/5740) Add ethernet support for risc-v/MPFS - * [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads + * [#5749](https://github.com/apache/nuttx/pull/5749) risc-v/mpfs: usb: fix ep0 stall/resume and rx reads * [#5783](https://github.com/apache/nuttx/pull/5783) risc-v/mpfs: usb: fix ep0 read done * [#5881](https://github.com/apache/nuttx/pull/5881) MPFS: Fix issue with external interrupt detection * [#5875](https://github.com/apache/nuttx/pull/5875) MPFS: Fix error in flat build linker script @@ -31961,7 +31961,7 @@ NuttX-11.0.0 Release Notes * [#6530](https://github.com/apache/nuttx/pull/6530) mpfs: Fix IHC memory locations to native width type * [#6490](https://github.com/apache/nuttx/pull/6490) mpfs: Allow mapping of RAM/ROM regions from different memory areas * [#6602](https://github.com/apache/nuttx/pull/6602) risc-v/mpfs: usb: fix illegal reads - * [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically + * [#6535](https://github.com/apache/nuttx/pull/6535) risc-v/mpfs: ihc: don't start rptun automatically * [#6361](https://github.com/apache/nuttx/pull/6361) arch/risc-v: re-add missing riscv_udelay source * [#6343](https://github.com/apache/nuttx/pull/6343) Some cleanup for risc-v * [#6342](https://github.com/apache/nuttx/pull/6342) arch/risc-v: Unify common source include @@ -32081,7 +32081,7 @@ NuttX-11.0.0 Release Notes * [#6379](https://github.com/apache/nuttx/pull/6379) arm/tlsr82: gpio driver bug fix and optimize * [#6334](https://github.com/apache/nuttx/pull/6334) arm/tlsr82: ble performance optimize and problems solve * [#6238](https://github.com/apache/nuttx/pull/6238) tlsr82/tc32: optimize the irq process - * [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp + * [#6332](https://github.com/apache/nuttx/pull/6332) arch: imx6: add support kernel build and smp * [#6429](https://github.com/apache/nuttx/pull/6429) arch: imx6: Enable imx_idle.c to reduce CPU load * [#6234](https://github.com/apache/nuttx/pull/6234) arm/tc32/Make.defs: filter-out arm_udelay.c * [#6736](https://github.com/apache/nuttx/pull/6736) arm/allocateheap: fix multiple definition of 'up_allocate_heap' @@ -32100,9 +32100,9 @@ NuttX-11.0.0 Release Notes * [#6775](https://github.com/apache/nuttx/pull/6775) arch/stm32/stm32_foc.c: fix some ADC and PWM ifdefs * [#6769](https://github.com/apache/nuttx/pull/6769) arch/stm32f0l0g0: add SPI3 support (STM32G0B0 chips) * [#6218](https://github.com/apache/nuttx/pull/6218) STM32F746G-Disco, Audiosupport, Bugfix - * [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support + * [#6715](https://github.com/apache/nuttx/pull/6715) stm32wb: adding BLE support * [#6729](https://github.com/apache/nuttx/pull/6729) stm32f7: add showprogress in __start - * [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio + * [#6078](https://github.com/apache/nuttx/pull/6078) Stm32f746 audio * [#6413](https://github.com/apache/nuttx/pull/6413) stm32wl5: add gpio exti support * [#6426](https://github.com/apache/nuttx/pull/6426) stm32wl5: add flash progmem driver support * [#6788](https://github.com/apache/nuttx/pull/6788) LPC17xx_40xx PWM multichannel support @@ -32289,7 +32289,7 @@ NuttX-11.0.0 Release Notes * [#6138](https://github.com/apache/nuttx/pull/6138) boards/boardctl: correct boarctl return value * [#6141](https://github.com/apache/nuttx/pull/6141) boards/risc-v: Remove "MAXOPTIMIZATION = -Os" from Make.defs * [#6143](https://github.com/apache/nuttx/pull/6143) boards: Move -fno-common from Make.defs to Toolchain.defs - * [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs + * [#6144](https://github.com/apache/nuttx/pull/6144) boards: Move -g from Make.defs to Toolchain.defs * [#6146](https://github.com/apache/nuttx/pull/6146) boards: Move "-fno-exceptions -fcheck-new" from Make.defs to Toolchain.defs * [#6155](https://github.com/apache/nuttx/pull/6155) boards: Move -fno-strict-aliasing from Make.defs to Toolchain.defs * [#6195](https://github.com/apache/nuttx/pull/6195) boards: rv-virt: Add support ELF to nsh and nsh64 defconfigs diff --git a/arch/arm/include/gd32f4/gd32f4xx_irq.h b/arch/arm/include/gd32f4/gd32f4xx_irq.h index 19b3324b13..7a2bf3ff67 100644 --- a/arch/arm/include/gd32f4/gd32f4xx_irq.h +++ b/arch/arm/include/gd32f4/gd32f4xx_irq.h @@ -219,7 +219,7 @@ #elif defined(CONFIG_GD32F4_GD32F405) # define GD32_IRQ_NEXTINT (82) # define NR_IRQS (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT) -#else +#else # error "Unknown GD32F4xx chip!" #endif diff --git a/arch/arm/src/gd32f4/Kconfig b/arch/arm/src/gd32f4/Kconfig index 439a14e22e..91f3eb2680 100644 --- a/arch/arm/src/gd32f4/Kconfig +++ b/arch/arm/src/gd32f4/Kconfig @@ -645,7 +645,7 @@ config GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG default n ---help--- In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. + to prevent the JTAG from disconnecting. config GD32F4_FORCEPOWER bool "Force power" @@ -774,8 +774,8 @@ config GD32F4_TIMER0_FDTS range 0 2 depends on GD32F4_TIMER0_PWM ---help--- - The CKDIV bits can be configured by software to specify division ratio - between the timer clock (TIMER_CK) and the dead-time and sampling clock (DTS), + The CKDIV bits can be configured by software to specify division ratio + between the timer clock (TIMER_CK) and the dead-time and sampling clock (DTS), which is used by the dead-time generators and the digital filters. config GD32F4_TIMER0_DEADTIME @@ -784,7 +784,7 @@ config GD32F4_TIMER0_DEADTIME range 0 255 depends on GD32F4_TIMER0_PWM ---help--- - This controls the value of the dead-time, which is inserted before the + This controls the value of the dead-time, which is inserted before the output transitions. @@ -801,7 +801,7 @@ config GD32F4_TIMER0_CH1MODE range 0 7 depends on GD32F4_TIMER0_CHANNEL0 ---help--- - This controls the behavior of the output reference signal O0CPRE + This controls the behavior of the output reference signal O0CPRE which drives CH0_O and CH0_ON. config GD32F4_TIMER0_CH0O @@ -831,7 +831,7 @@ config GD32F4_TIMER0_CH1MODE range 0 7 depends on GD32F4_TIMER0_CHANNEL1 ---help--- - This controls the behavior of the output reference signal O1CPRE + This controls the behavior of the output reference signal O1CPRE which drives CH1_O and CH1_ON. config GD32F4_TIMER0_CH1O @@ -861,7 +861,7 @@ config GD32F4_TIMER0_CH2MODE range 0 7 depends on GD32F4_TIMER0_CHANNEL2 ---help--- - This controls the behavior of the output reference signal O2CPRE + This controls the behavior of the output reference signal O2CPRE which drives CH2_O and CH2_ON. config GD32F4_TIMER0_CH2O @@ -891,7 +891,7 @@ config GD32F4_TIMER0_CH3MODE range 0 7 depends on GD32F4_TIMER0_CHANNEL3 ---help--- - This controls the behavior of the output reference signal O3CPRE + This controls the behavior of the output reference signal O3CPRE which drives CH3_O and CH3_ON. config GD32F4_TIMER0_CH3O @@ -917,9 +917,9 @@ config GD32F4_TIMER0_ADC Reserve timer 0 for use by ADC Timer can be used for different purposes. When the timer0 - is intended to be used for ADC conversion, the GD32F4_TIMER0 + is intended to be used for ADC conversion, the GD32F4_TIMER0 and GD32F4_ADC should be defined before. There requires two - definition for ADC usage: First, assign which timer is used to + definition for ADC usage: First, assign which timer is used to trigger the ADC. Second, and configure which ADC to sample. choice @@ -1020,9 +1020,9 @@ config GD32F4_TIMER0_DAC Reserve timer 0 for use by DAC Timer can be used for different purposes. When the timer0 - is intended to be used for DAC conversion, the GD32F4_TIMER0 + is intended to be used for DAC conversion, the GD32F4_TIMER0 and GD32F4_DAC should be defined before. There requires two - definition for DAC usage: First, assign which timer is used to + definition for DAC usage: First, assign which timer is used to trigger the DAC. Second, and configure which DAC channel to work. choice @@ -1050,7 +1050,7 @@ config GD32F4_TIMER0_CAP ---help--- Reserve timer 0 for use by Capture - Timer can be used for different purposes. To capture input is + Timer can be used for different purposes. To capture input is one of the usual purpose. @@ -1102,7 +1102,7 @@ config GD32F4_ADC0_RESOLUTION default 0 range 0 3 ---help--- - ADC0 data resolution. 0: 12 bit, 1: 10 bit, + ADC0 data resolution. 0: 12 bit, 1: 10 bit, 2: 8 bit, 3: 6 bit config GD32F4_ADC1_RESOLUTION @@ -1111,7 +1111,7 @@ config GD32F4_ADC1_RESOLUTION default 0 range 0 3 ---help--- - ADC1 data resolution. 0: 12 bit, 1: 10 bit, + ADC1 data resolution. 0: 12 bit, 1: 10 bit, 2: 8 bit, 3: 6 bit config GD32F4_ADC2_RESOLUTION @@ -1120,7 +1120,7 @@ config GD32F4_ADC2_RESOLUTION default 0 range 0 3 ---help--- - ADC2 data resolution. 0: 12 bit, 1: 10 bit, + ADC2 data resolution. 0: 12 bit, 1: 10 bit, 2: 8 bit, 3: 6 bit config GD32F4_ADC_MAX_SAMPLES @@ -1128,9 +1128,9 @@ config GD32F4_ADC_MAX_SAMPLES default 16 ---help--- The ADC supports 19 multiplexed channels and two groups: regular and inserted channel group. - The maximum number of samples for regular group can be 16, for inserted channel group + The maximum number of samples for regular group can be 16, for inserted channel group can be 4. - User can change the default value according to the board initialize. The user should + User can change the default value according to the board initialize. The user should correctly configure this value. config GD32F4_ADC_NOINT @@ -1331,7 +1331,7 @@ config GD32F4_DAC0_OUTPUT_BUFFER depends on GD32F4_DAC0 default y ---help--- - DAC0 output buffer configuration + DAC0 output buffer configuration config GD32F4_DAC0_DATA int "DAC0 data configuration" @@ -1348,7 +1348,7 @@ config GD32F4_DAC0_TRIG depends on GD32F4_DAC0 default y ---help--- - DAC0 trigger configuration + DAC0 trigger configuration config GD32F4_DAC0_TRIG_MODE int "DAC0 trigger source select" @@ -1365,7 +1365,7 @@ config GD32F4_DAC0_TIMER_FREQUENCY depends on GD32F4_DAC0 && GD32F4_DAC0_TRIG default 1000 ---help--- - DAC0 output frequency, only in timer triggrer mode is useful. + DAC0 output frequency, only in timer triggrer mode is useful. Default: 1000Hz config GD32F4_DAC0_DMA @@ -1375,10 +1375,10 @@ config GD32F4_DAC0_DMA ---help--- When the external trigger is enabled, the DMA request can be enabled by setting the DDMAENx bits of the DAC_CTL register. A DMA request will be generated by DAC when an - external hardware trigger (not a software trigger) occurs. The user should note that + external hardware trigger (not a software trigger) occurs. The user should note that when use DMA. The timer and output frequency must also be provided to support the DMA transfer, - when the timer is selected to trigger DAC DMA. + when the timer is selected to trigger DAC DMA. config GD32F4_DAC0_DMA_BUFFER_SIZE int "DAC0 DMA buffer size" @@ -1390,7 +1390,7 @@ config GD32F4_DAC1_OUTPUT_BUFFER depends on GD32F4_DAC1 default y ---help--- - DAC0 output buffer configuration + DAC0 output buffer configuration config GD32F4_DAC1_DATA int "DAC1 data configuration" @@ -1407,7 +1407,7 @@ config GD32F4_DAC1_TRIG depends on GD32F4_DAC1 default y ---help--- - DAC1 trigger configuration + DAC1 trigger configuration config GD32F4_DAC1_TRIG_MODE int "DAC1 trigger source select" @@ -1424,7 +1424,7 @@ config GD32F4_DAC1_TIMER_FREQUENCY depends on GD32F4_DAC1 && GD32F4_DAC1_TRIG default 1000 ---help--- - DAC1 output frequency, only in timer triggrer mode is useful. + DAC1 output frequency, only in timer triggrer mode is useful. Default: 1000Hz config GD32F4_DAC1_DMA @@ -1434,10 +1434,10 @@ config GD32F4_DAC1_DMA ---help--- When the external trigger is enabled, the DMA request can be enabled by setting the DDMAENx bits of the DAC_CTL register. A DMA request will be generated by DAC when an - external hardware trigger (not a software trigger) occurs. The user should note that + external hardware trigger (not a software trigger) occurs. The user should note that when use DMA. The timer and output frequency must also be provided to support the DMA transfer, - when the timer is selected to trigger DAC DMA. + when the timer is selected to trigger DAC DMA. config GD32F4_DAC1_DMA_BUFFER_SIZE int "DAC1 DMA buffer size" @@ -1487,8 +1487,8 @@ config USART0_RS485 default n ---help--- USART0 RS-485 function configuration. If the user configure the RS-485 on - USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition - in board initialization. + USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition + in board initialization. And it cannot be used with GD32F4_USART0_RXDMA currently. config USART0_RS485_DIR_POLARITY @@ -1497,7 +1497,7 @@ config USART0_RS485_DIR_POLARITY range 0 1 depends on USART0_RS485 ---help--- - Polarity of GPIO_USART0_RS485_DIR pin for RS-485 on USART0. + Polarity of GPIO_USART0_RS485_DIR pin for RS-485 on USART0. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_USART0_RXDMA @@ -1507,7 +1507,7 @@ config GD32F4_USART0_RXDMA select GD32F4_USART_RXDMA select USART0_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_USART0_TXDMA @@ -1517,7 +1517,7 @@ config GD32F4_USART0_TXDMA select GD32F4_USART_TXDMA select USART0_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmitting data buffer. endif # GD32F4_USART0_SERIALDRIVER @@ -1546,8 +1546,8 @@ config USART1_RS485 default n ---help--- USART1 RS-485 function configuration. If the user configure the RS-485 on - USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition - in board initialization. + USART, the user's should to provide GPIO_USART0_RS485_DIR pin definition + in board initialization. And it cannot be used with GD32F4_USART1_RXDMA currently. config USART1_RS485_DIR_POLARITY @@ -1556,7 +1556,7 @@ config USART1_RS485_DIR_POLARITY range 0 1 depends on USART1_RS485 ---help--- - Polarity of GPIO_USART1_RS485_DIR pin for RS-485 on USART1. + Polarity of GPIO_USART1_RS485_DIR pin for RS-485 on USART1. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_USART1_RXDMA @@ -1566,7 +1566,7 @@ config GD32F4_USART1_RXDMA select GD32F4_USART_RXDMA select USART1_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_USART1_TXDMA @@ -1576,7 +1576,7 @@ config GD32F4_USART1_TXDMA select GD32F4_USART_TXDMA select USART1_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmitting data buffer. endif # GD32F4_USART1_SERIALDRIVER @@ -1605,8 +1605,8 @@ config USART2_RS485 default n ---help--- USART2 RS-485 function configuration. If the user configure the RS-485 on - USART, the user's should to provide GPIO_USART2_RS485_DIR pin definition - in board initialization. + USART, the user's should to provide GPIO_USART2_RS485_DIR pin definition + in board initialization. And it cannot be used with GD32F4_USART2_RXDMA currently. config USART2_RS485_DIR_POLARITY @@ -1615,7 +1615,7 @@ config USART2_RS485_DIR_POLARITY range 0 1 depends on USART1_RS485 ---help--- - Polarity of GPIO_USART2_RS485_DIR pin for RS-485 on USART2. + Polarity of GPIO_USART2_RS485_DIR pin for RS-485 on USART2. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_USART2_RXDMA @@ -1625,7 +1625,7 @@ config GD32F4_USART2_RXDMA select GD32F4_USART_RXDMA select USART2_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_USART2_TXDMA @@ -1635,7 +1635,7 @@ config GD32F4_USART2_TXDMA select GD32F4_USART_TXDMA select USART2_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmitting data buffer. endif # GD32F4_USART2_SERIALDRIVER @@ -1664,8 +1664,8 @@ config UART3_RS485 default n ---help--- UART3 RS-485 function configuration. If the user configure the RS-485 on - UART, the user's should to provide UART3_RS485_DIR_POLARITY pin definition - in board initialization. + UART, the user's should to provide UART3_RS485_DIR_POLARITY pin definition + in board initialization. And it cannot be used with GD32F4_UART3_RXDMA currently. config UART3_RS485_DIR_POLARITY @@ -1674,7 +1674,7 @@ config UART3_RS485_DIR_POLARITY range 0 1 depends on UART3_RS485 ---help--- - Polarity of GPIO_UART3_RS485_DIR pin for RS-485 on UART3. + Polarity of GPIO_UART3_RS485_DIR pin for RS-485 on UART3. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_UART3_RXDMA @@ -1684,7 +1684,7 @@ config GD32F4_UART3_RXDMA select GD32F4_USART_RXDMA select UART3_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_UART3_TXDMA @@ -1694,7 +1694,7 @@ config GD32F4_UART3_TXDMA select GD32F4_USART_TXDMA select UART3_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmit data buffer. endif # GD32F4_UART3_SERIALDRIVER @@ -1723,8 +1723,8 @@ config UART4_RS485 default n ---help--- UART4 RS-485 function configuration. If the user configure the RS-485 on - UART, the user's should to provide UART4_RS485_DIR_POLARITY pin definition - in board initialization. + UART, the user's should to provide UART4_RS485_DIR_POLARITY pin definition + in board initialization. And it cannot be used with GD32F4_UART4_RXDMA currently. config UART4_RS485_DIR_POLARITY @@ -1733,7 +1733,7 @@ config UART4_RS485_DIR_POLARITY range 0 1 depends on UART4_RS485 ---help--- - Polarity of GPIO_UART4_RS485_DIR pin for RS-485 on UART4. + Polarity of GPIO_UART4_RS485_DIR pin for RS-485 on UART4. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_UART4_RXDMA @@ -1743,7 +1743,7 @@ config GD32F4_UART4_RXDMA select GD32F4_USART_RXDMA select UART4_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_UART4_TXDMA @@ -1753,7 +1753,7 @@ config GD32F4_UART4_TXDMA select GD32F4_USART_TXDMA select UART4_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmit data buffer. endif # GD32F4_UART4_SERIALDRIVER @@ -1782,8 +1782,8 @@ config USART5_RS485 default n ---help--- USART5 RS-485 function configuration. If the user configure the RS-485 on - USART, the user's should to provide GPIO_USART5_RS485_DIR pin definition - in board initialization. + USART, the user's should to provide GPIO_USART5_RS485_DIR pin definition + in board initialization. And it cannot be used with GD32F4_USART5_RXDMA currently. config USART5_RS485_DIR_POLARITY @@ -1792,7 +1792,7 @@ config USART5_RS485_DIR_POLARITY range 0 1 depends on USART1_RS485 ---help--- - Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5. + Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_USART5_RXDMA @@ -1802,7 +1802,7 @@ config GD32F4_USART5_RXDMA select GD32F4_USART_RXDMA select USART5_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_USART5_TXDMA @@ -1812,7 +1812,7 @@ config GD32F4_USART5_TXDMA select GD32F4_USART_TXDMA select USART5_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmitting data buffer. endif # GD32F4_USART5_SERIALDRIVER @@ -1842,8 +1842,8 @@ config UART6_RS485 default n ---help--- UART6 RS-485 function configuration. If the user configure the RS-485 on - UART, the user's should to provide UART6_RS485_DIR_POLARITY pin definition - in board initialization. + UART, the user's should to provide UART6_RS485_DIR_POLARITY pin definition + in board initialization. And it cannot be used with GD32F4_UART6_RXDMA currently. config UART6_RS485_DIR_POLARITY @@ -1852,7 +1852,7 @@ config UART6_RS485_DIR_POLARITY range 0 1 depends on UART6_RS485 ---help--- - Polarity of GPIO_UART6_RS485_DIR pin for RS-485 on UART6. + Polarity of GPIO_UART6_RS485_DIR pin for RS-485 on UART6. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_UART6_RXDMA @@ -1862,7 +1862,7 @@ config GD32F4_UART6_RXDMA select GD32F4_USART_RXDMA select UART6_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_UART6_TXDMA @@ -1872,7 +1872,7 @@ config GD32F4_UART6_TXDMA select GD32F4_USART_TXDMA select UART6_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmit data buffer. endif # GD32F4_UART6_SERIALDRIVER @@ -1902,8 +1902,8 @@ config UART7_RS485 default n ---help--- UART7 RS-485 function configuration. If the user configure the RS-485 on - UART, the user's should to provide UART7_RS485_DIR_POLARITY pin definition - in board initialization. + UART, the user's should to provide UART7_RS485_DIR_POLARITY pin definition + in board initialization. And it cannot be used with GD32F4_UART7_RXDMA currently. config UART7_RS485_DIR_POLARITY @@ -1912,7 +1912,7 @@ config UART7_RS485_DIR_POLARITY range 0 1 depends on UART7_RS485 ---help--- - Polarity of GPIO_UART7_RS485_DIR pin for RS-485 on UART7. + Polarity of GPIO_UART7_RS485_DIR pin for RS-485 on UART7. The state on DIR pin: 0 - receive , 1 - transmit. config GD32F4_UART7_RXDMA @@ -1922,7 +1922,7 @@ config GD32F4_UART7_RXDMA select GD32F4_USART_RXDMA select UART7_RXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the receiving data buffer. config GD32F4_UART7_TXDMA @@ -1932,7 +1932,7 @@ config GD32F4_UART7_TXDMA select GD32F4_USART_TXDMA select UART7_TXDMA ---help--- - To reduce the burden of the processor in fast data transmit, DMA can be used to + To reduce the burden of the processor in fast data transmit, DMA can be used to access the transmit data buffer. endif # GD32F4_UART7_SERIALDRIVER @@ -2003,7 +2003,7 @@ config GD32F4_USART_INVERT default n depends on GD32F4_USART0 || GD32F4_USART1 || GD32F4_USART1 || GD32F4_USART5 ---help--- - Enable signal inversion support for USART RX/TX pin . The option enables + Enable signal inversion support for USART RX/TX pin . The option enables support for the TIOCSINVERT ioctl in the gd32f4 serial driver. RX/TX inversion only support for USART0, 1, 2, 5 @@ -2161,8 +2161,8 @@ config GD32F4_SPI_DMATHRESHOLD default 4 depends on GD32F4_SPI_DMA ---help--- - When SPI DMA is enabled, if transfers size is less than GD32F4_SPI_DMATHRESHOLD, - the data transfer will still be performed by polling logic. + When SPI DMA is enabled, if transfers size is less than GD32F4_SPI_DMATHRESHOLD, + the data transfer will still be performed by polling logic. config GD32F4_SPI0_DMA bool "SPI0 DMA" @@ -2307,7 +2307,7 @@ config GD32F4_MII bool "Use the media-independent interface (MII) interface" default n ---help--- - Select Ethernet MII interface. The application can only select one of + Select Ethernet MII interface. The application can only select one of the MII or RMII mode. choice @@ -2360,9 +2360,9 @@ config GD32F4_PHY_SR int "PHY Status Register Address (decimal)" depends on GD32F4_AUTO_NEGOTIATION ---help--- - This must be provided if GD32F4_AUTO_NEGOTIATION is defined. Because of the - PHY status register address may different from PHY to PHY, the user should set - the address of the PHY status register according to the PHY on board. + This must be provided if GD32F4_AUTO_NEGOTIATION is defined. Because of the + PHY status register address may different from PHY to PHY, the user should set + the address of the PHY status register according to the PHY on board. config GD32F4_PHY_SR_ALTCONFIG bool "PHY Status Alternate Bit Layout" @@ -2450,7 +2450,7 @@ config GD32F4_RMII bool "Use the reduced media-independent interface (RMII) interface" default y if !GD32F4_MII ---help--- - Select Ethernet MII interface. The application can only select one of + Select Ethernet MII interface. The application can only select one of the MII or RMII mode. choice @@ -2471,7 +2471,7 @@ config GD32F4_RMII_CKOUT1 config GD32F4_RMII_EXTCLK bool "External RMII clock" ---help--- - Clocking is provided by external clock. And not use CKOUT for + Clocking is provided by external clock. And not use CKOUT for RMII clock. endchoice # RMII clock configuration diff --git a/arch/arm/src/gd32f4/gd32f4xx_allocateheap.c b/arch/arm/src/gd32f4/gd32f4xx_allocateheap.c index 174eb7b1ad..e9aee1e9c6 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_allocateheap.c +++ b/arch/arm/src/gd32f4/gd32f4xx_allocateheap.c @@ -144,9 +144,9 @@ /* Two memory regions. Case 1 or 2 */ # if !defined(CONFIG_GD32F4_TCMEXCLUDE) && defined(CONFIG_GD32F4_EXTERNAL_RAM) -# error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 " +# error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 " # undef CONFIG_GD32F4_TCMEXCLUDE -# define CONFIG_GD32F4_TCMEXCLUDE 1 +# define CONFIG_GD32F4_TCMEXCLUDE 1 # endif /* Case 1, TCMSRAM is used. In this case, DMA should not be used */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_irq.c b/arch/arm/src/gd32f4/gd32f4xx_irq.c index da323d5152..f8db23cdff 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_irq.c +++ b/arch/arm/src/gd32f4/gd32f4xx_irq.c @@ -129,7 +129,7 @@ static void gd32_dumpnvic(const char *msg, int irq) getreg32(NVIC_IRQ84_87_PRIORITY), getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY)); -#endif +#endif leave_critical_section(flags); } diff --git a/arch/arm/src/gd32f4/gd32f4xx_rcu.c b/arch/arm/src/gd32f4/gd32f4xx_rcu.c index cece3fd6b7..9bebdfc3ff 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_rcu.c +++ b/arch/arm/src/gd32f4/gd32f4xx_rcu.c @@ -83,7 +83,7 @@ * Pravite Functions ****************************************************************************/ -#ifdef GD32_BOARD_SYSCLK_IRC16MEN +#ifdef GD32_BOARD_SYSCLK_IRC16MEN /**************************************************************************** * Name: gd32_system_clock_irc16m * @@ -512,7 +512,7 @@ static void gd32_system_clock_pll_hxtal(void) static void gd32_system_clock_config(void) { -#ifdef GD32_BOARD_SYSCLK_IRC16MEN +#ifdef GD32_BOARD_SYSCLK_IRC16MEN /* Select IRC16M as SYSCLK based on board.h setting. */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 7ac99ee418..753cc0717e 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -80,7 +80,7 @@ /* USART DMA priority */ #if defined(CONFIG_GD32F4_USART_PRIQ) # define USART_DMA_PRIO CONFIG_GD32F4_USART_PRIQ -#else +#else # define USART_DMA_PRIO DMA_PRIO_MEDIUM_SELECT #endif #endif diff --git a/arch/arm/src/gd32f4/gd32f4xx_spi.c b/arch/arm/src/gd32f4/gd32f4xx_spi.c index 198bc7e9dc..8d6049b38f 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_spi.c +++ b/arch/arm/src/gd32f4/gd32f4xx_spi.c @@ -99,7 +99,7 @@ #if defined(CONFIG_GD32F4_SPI_PRIQ) # define SPI_DMA_PRIO CONFIG_GD32F4_SPI_PRIQ -#else +#else # define SPI_DMA_PRIO DMA_PRIO_MEDIUM_SELECT #endif diff --git a/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h b/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h index 769c192616..a6e00ca3c0 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h +++ b/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h @@ -84,7 +84,7 @@ /* Peripheral Base Addresses ************************************************/ -#define GD32_APB1_BUS_BASE 0x40000000 /* APB1 base address */ +#define GD32_APB1_BUS_BASE 0x40000000 /* APB1 base address */ #define GD32_APB2_BUS_BASE 0x40010000 /* APB2 base address */ #define GD32_AHB1_BUS_BASE 0x40020000 /* AHB1 base address */ #define GD32_AHB2_BUS_BASE 0x50000000 /* AHB2 base address */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h b/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h index ccd216021e..5f276d9bdb 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h +++ b/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h @@ -530,7 +530,7 @@ #define GPIO_SPI3_SCK_4 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_G|GPIO_CFG_PIN_11) #define GPIO_SPI4_MISO_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_12) -#define GPIO_SPI4_MISO_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13) +#define GPIO_SPI4_MISO_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_E|GPIO_CFG_PIN_13) #define GPIO_SPI4_MISO_3 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_F|GPIO_CFG_PIN_8) #define GPIO_SPI4_MISO_4 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_5|GPIO_CFG_PORT_H|GPIO_CFG_PIN_7) #define GPIO_SPI4_MOSI_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_NONE|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_6|GPIO_CFG_PORT_A|GPIO_CFG_PIN_10) diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h index 78c2627feb..52dd458c0a 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h @@ -196,7 +196,7 @@ #define DMA_CHXCTL_TM(n) ((n) << DMA_CHXCTL_TM_SHIFT) # define DMA_PERIPH_TO_MEMORY DMA_CHXCTL_TM(0) /* 00: read from peripheral and write to memory */ # define DMA_MEMORY_TO_PERIPH DMA_CHXCTL_TM(1) /* 01: read from peripheral and write to memory */ -# define DMA_MEMORY_TO_MEMORY DMA_CHXCTL_TM(2) /* 02: read from peripheral and write to memory */ +# define DMA_MEMORY_TO_MEMORY DMA_CHXCTL_TM(2) /* 02: read from peripheral and write to memory */ #define DMA_CHXCTL_CMEN (1 << 8) /* Bit 8: circulation mode */ #define DMA_CHXCTL_PNAGA (1 << 9) /* Bit 9: next address generation algorithm of peripheral */ @@ -229,7 +229,7 @@ #define DMA_CHXCTL_MBS (1 << 19) /* Bit19: memory buffer select */ #define DMA_CHXCTL_PBURST_SHIFT (21) /* Bit 21-22: transfer burst type of peripheral */ -#define DMA_CHXCTL_PBURST_MASK (3 << DMA_CHXCTL_PBURST_SHIFT) +#define DMA_CHXCTL_PBURST_MASK (3 << DMA_CHXCTL_PBURST_SHIFT) #define DMA_CHXCTL_PBURST(n) ((n) << DMA_CHXCTL_PBURST_SHIFT) # define DMA_PERIPH_BURST_SINGLE DMA_CHXCTL_PBURST(0) /* single burst */ # define DMA_PERIPH_BURST_4_BEAT DMA_CHXCTL_PBURST(1) /* 4-beat burst */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h index 15510ee18d..e188657a9d 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h @@ -125,7 +125,7 @@ #define EXTI_17 GD32_EXTI_BIT(17) /* EXTI line 17 */ #define EXTI_18 GD32_EXTI_BIT(18) /* EXTI line 18 */ #define EXTI_19 GD32_EXTI_BIT(19) /* EXTI line 19 */ -#define EXTI_20 GD32_EXTI_BIT(20) /* EXTI line 20 */ +#define EXTI_20 GD32_EXTI_BIT(20) /* EXTI line 20 */ #define EXTI_21 GD32_EXTI_BIT(21) /* EXTI line 21 */ #define EXTI_22 GD32_EXTI_BIT(22) /* EXTI line 22 */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h index 4ae58a1bbf..52cfdb85fb 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h @@ -153,7 +153,7 @@ #define FMC_CTL_SN_SHIFT (3) /* Bits 3-7: select which sector number to be erased */ #define FMC_CTL_SN_MASK (31 << FMC_CTL_SN_SHIFT) -#define FMC_CTL_SN(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */ +#define FMC_CTL_SN(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */ #define FMC_CTL_SN_0_11(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */ #define FMC_CTL_SN_12_23(n) ((n+4) << FMC_CTL_SN_SHIFT)) /* Sector n, n=12..23 */ #define FMC_CTL_SN_24_27(n) ((n-12) << FMC_CTL_SN_SHIFT)) /* Sector n, n=24..27 */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h index fc3866c3ac..12db01f252 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h @@ -297,7 +297,7 @@ #define RCU_AHB1RST_PGRST (1 << 6) /* Bit 6: GPIO port G reset */ #define RCU_AHB1RST_PHRST (1 << 7) /* Bit 7: GPIO port H reset */ #define RCU_AHB1RST_PIRST (1 << 8) /* Bit 8: GPIO port I reset */ -#define RCU_AHB1RST_CRCRST (1 << 12) /* Bit 12: CRC reset */ +#define RCU_AHB1RST_CRCRST (1 << 12) /* Bit 12: CRC reset */ #define RCU_AHB1RST_DMA0RST (1 << 21) /* Bit 21: DMA0 reset */ #define RCU_AHB1RST_DMA1RST (1 << 22) /* Bit 22: DMA1 reset */ #define RCU_AHB1RST_IPARST (1 << 23) /* Bit 23: IPA reset */ @@ -562,13 +562,13 @@ /* PLL clock spread spectrum control register */ -#define RCU_PLLSSCTL_MODCNT_SHIFT (0) /* Bit 0-12: These bits configure PLL spread spectrum modulation +#define RCU_PLLSSCTL_MODCNT_SHIFT (0) /* Bit 0-12: These bits configure PLL spread spectrum modulation * profile amplitude and frequency. The following criteria * must be met: MODSTEP*MODCNT<=2^15-1 */ #define RCU_PLLSSCTL_MODCNT_MASK (0x1fff << RCU_PLLSSCTL_MODCNT_SHIFT) # define RCU_PLLSSCTL_MODCNT(n) ((n) << RCU_PLLSSCTL_MODCNT_SHIFT) -#define RCU_PLLSSCTL_MODSTEP_SHIFT (13) /* Bit 13-27: These bits configure PLL spread spectrum modulation +#define RCU_PLLSSCTL_MODSTEP_SHIFT (13) /* Bit 13-27: These bits configure PLL spread spectrum modulation * profile amplitude and frequency. The following criteria * must be met: MODSTEP*MODCNT<=2^15-1 */ #define RCU_PLLSSCTL_MODSTEP_MASK (0x7fff << RCU_PLLSSCTL_MODSTEP_SHIFT) @@ -603,7 +603,7 @@ # define RCU_PLLSAI_PLLSAIP_DIV_6 RCU_PLLSAI_PLLSAIP(6) # define RCU_PLLSAI_PLLSAIP_DIV_8 RCU_PLLSAI_PLLSAIP(8) -#define RCU_PLLSAI_PLLSAIR_SHIFT (28) /* Bits 28-30: The PLLSAI R output frequency division factor +#define RCU_PLLSAI_PLLSAIR_SHIFT (28) /* Bits 28-30: The PLLSAI R output frequency division factor * from PLLSAI VCO clock */ #define RCU_PLLSAI_PLLSAIR_MASK (7 << RCU_PLLSAI_PLLSAIR_SHIFT) # define RCU_PLLSAI_PLLSAIR(n) ((n) << RCU_PLLSAI_PLLSAIR_SHIFT) /* n=2..7 */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h index c21947be06..d86301b4da 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h @@ -98,7 +98,7 @@ #define SPI_CTL0_CKPH (1 << 0) /* Bit 0: clock phase selection*/ #define SPI_CTL0_CKPL (1 << 1) /* Bit 1: clock polarity selection */ #define SPI_CTL0_MSTMOD (1 << 2) /* Bit 2: master mode enable */ -#define SPI_CTL0_PSC_SHIFT (3) /* Bit 3-5: master clock prescaler selection */ +#define SPI_CTL0_PSC_SHIFT (3) /* Bit 3-5: master clock prescaler selection */ #define SPI_CTL0_PSC_MASK (7 << SPI_CTL0_PSC_SHIFT) #define SPI_CTL0_PSC(n) ((n) << SPI_CTL0_PSC_SHIFT) # define SPI_CTL0_PSC_2 SPI_CTL0_PSC(0) /* 000: SPI clock prescale factor is 2 */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h index 0ab4066446..a377f247b1 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_uart.h @@ -150,7 +150,7 @@ # define USART_CTL0_PM_ODD USART_CTL0_PMEN(3) #define USART_WL_9BIT USART_CTL0_WL -#define USART_WL_8BIT (0) +#define USART_WL_8BIT (0) #define USART_CTL0_INT_SHIFT (4) #define USART_CTL0_INT_MASK (0x1f << USART_CTL0_INT_SHIFT) diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c index 66fcb2491b..10fc784d42 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c @@ -386,7 +386,7 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv, putreg32(ub16mulub16(info->channels[i].duty, mr0_freq), LPC17_40_PWM1_MR6); /* Set PWM cycle */ break; -#endif +#endif default: { diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index c193c90858..31c5a169d6 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -667,7 +667,7 @@ menuconfig NRF52_SOFTDEVICE_CONTROLLER depends on NRF52_LFCLK_XTAL ---help--- This enables use of Nordic SoftDevice controller - (SDC). It is a library version of a subset of + (SDC). It is a library version of a subset of full SoftDevice, which only includes the BLE controller implementation. diff --git a/arch/arm/src/phy62xx/Make.defs b/arch/arm/src/phy62xx/Make.defs index ac7023e67e..0895551501 100644 --- a/arch/arm/src/phy62xx/Make.defs +++ b/arch/arm/src/phy62xx/Make.defs @@ -30,9 +30,9 @@ CHIP_CSRCS += phy62xx_ble.c endif ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += phyplus_tim.c +CHIP_CSRCS += phyplus_tim.c CHIP_CSRCS += phyplus_timer_lowerhalf.c -CHIP_CSRCS += phyplus_timerisr.c +CHIP_CSRCS += phyplus_timerisr.c endif ifeq ($(CONFIG_DEV_GPIO),y) @@ -53,15 +53,15 @@ INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble) CFLAGS += -ffunction-sections CFLAGS += -DCFG_CP CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0 -CFLAGS += -DHOST_CONFIG=4 -CFLAGS += -DHCI_TL_NONE=1 -CFLAGS += -DMTU_SIZE=247 -CFLAGS += -DENABLE_LOG_ROMx=0 -CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0 -CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP -CFLAGS += -DDEBUG_INFO=1 -CFLAGS += -DUSE_SYS_TICK -CFLAGS += -DHUGE_MODE=0 +CFLAGS += -DHOST_CONFIG=4 +CFLAGS += -DHCI_TL_NONE=1 +CFLAGS += -DMTU_SIZE=247 +CFLAGS += -DENABLE_LOG_ROMx=0 +CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0 +CFLAGS += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP +CFLAGS += -DDEBUG_INFO=1 +CFLAGS += -DUSE_SYS_TICK +CFLAGS += -DHUGE_MODE=0 CFLAGS += -DMAX_NUM_LL_CONN=1 CFLAGS += -DUSE_ROMSYM_ALIAS CFLAGS += -Wno-unused-but-set-variable diff --git a/arch/arm/src/phy62xx/phyplus_gpio.c b/arch/arm/src/phy62xx/phyplus_gpio.c index 7fee83cee6..03bc9801ab 100644 --- a/arch/arm/src/phy62xx/phyplus_gpio.c +++ b/arch/arm/src/phy62xx/phyplus_gpio.c @@ -38,7 +38,7 @@ #include "phyplus_gpio.h" #include "errno.h" -#if defined(CONFIG_DEV_GPIO) +#if defined(CONFIG_DEV_GPIO) /**************************************************************************** * phy6222 internal used functions.. @@ -171,7 +171,7 @@ static int phyplus_gpin_read(struct gpio_dev_s *dev, bool *value) gpioinfo("Reading...\n"); *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); -#endif +#endif struct phyplus_gpio_dev_s *phyplus_gpin = (struct phyplus_gpio_dev_s *)dev; @@ -195,7 +195,7 @@ static int phyplus_gpout_read(struct gpio_dev_s *dev, bool *value) gpioinfo("Reading...\n"); *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); -#endif +#endif struct phyplus_gpio_dev_s *phyplus_gpout = (struct phyplus_gpio_dev_s *)dev; diff --git a/arch/arm/src/phy62xx/phyplus_stub.c b/arch/arm/src/phy62xx/phyplus_stub.c index acd5e859ce..e5bd53aa66 100644 --- a/arch/arm/src/phy62xx/phyplus_stub.c +++ b/arch/arm/src/phy62xx/phyplus_stub.c @@ -520,7 +520,7 @@ static int phyplus_parse_params_and_action(char *buff) return -1; } } -#if 0 +#if 0 else if (0 == strncmp(buff, "reg_timer", 9)) { p += 10; diff --git a/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c b/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c index b2003fadd0..0cf45d3dd7 100644 --- a/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c +++ b/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c @@ -114,7 +114,7 @@ static const struct timer_ops_s g_timer_ops = .getstatus = phyplus_getstatus, #else .getstatus = NULL, -#endif +#endif .settimeout = phyplus_settimeout, .setcallback = phyplus_setcallback, #if 1 diff --git a/arch/arm/src/rp2040/rp2040_ws2812.pio b/arch/arm/src/rp2040/rp2040_ws2812.pio index 856ea51bc2..dc832d7730 100644 --- a/arch/arm/src/rp2040/rp2040_ws2812.pio +++ b/arch/arm/src/rp2040/rp2040_ws2812.pio @@ -13,10 +13,10 @@ ; ; clock +-----+-----+-----+-----+-----+-----+-----+-----+-----+ | | T1 | T2 | T3 | -; +; ; +-----------+ ; zero-bit | | | -; +-----------------------------------------+ +; +-----------------------------------------+ ; ; +-----------------------------------+ ; one-bit | | | diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig index 9059bc3ff4..2212d4237a 100644 --- a/arch/arm/src/s32k1xx/Kconfig +++ b/arch/arm/src/s32k1xx/Kconfig @@ -630,15 +630,15 @@ endmenu # eDMA Global Configuration menu "LPUART Configuration" depends on S32K1XX_LPUART - + config S32K1XX_LPUART_INVERT bool "Signal Invert Support" default n -endmenu +endmenu menu "LPSPI Configuration" depends on S32K1XX_LPSPI - + config S32K1XX_LPSPI_DWORD bool "DWORD up to 64 bit transfer support" default n @@ -684,7 +684,7 @@ config S32K1XX_LPSPI_DMATHRESHOLD config S32K1XX_LPSPI_HWPCS bool "Use native hardware peripheral chip selects instead of GPIO pins" default n - + endmenu # LPSPI Configuration menu "LPI2C Configuration" diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h index d2dcf39187..ec357423eb 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_flexio.h @@ -329,7 +329,7 @@ #define FLEXIO_TIMCTL_PINPOL (1 << 7) /* Bit 7: Timer Pin Polarity (PINPOL) */ # define FLEXIO_TIMCTL_PINPOL_HI (0 << 7) /* Pin is active high */ # define FLEXIO_TIMCTL_PINPOL_LO (1 << 7) /* Pin is active low */ -#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-10: Timer Pin Select (PINSEL) */ +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-10: Timer Pin Select (PINSEL) */ #define FLEXIO_TIMCTL_PINSEL_MASK (0x07 << FLEXIO_TIMCTL_PINSEL_SHIFT) # define FLEXIO_TIMCTL_PINSEL(n) (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK) /* Bits 11-15: Reserved */ @@ -363,7 +363,7 @@ # define FLEXIO_TIMCFG_TSTART_DIS (0 << 1) /* Start bit disabled */ # define FLEXIO_TIMCFG_TSTART_ENA (1 << 1) /* Start bit enabled */ /* Bits 2-3: Reserved */ -#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */ +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */ #define FLEXIO_TIMCFG_TSTOP_MASK (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) # define FLEXIO_TIMCFG_TSTOP_DIS (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */ # define FLEXIO_TIMCFG_TSTOP_TIMCMP (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */ @@ -371,7 +371,7 @@ # define FLEXIO_TIMCFG_TSTOP_BOTH (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */ /* Bits 6-7: Reserved */ -#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */ +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */ #define FLEXIO_TIMCFG_TIMENA_MASK (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT) # define FLEXIO_TIMCFG_TIMENA_ALWAYS (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */ # define FLEXIO_TIMCFG_TIMENA_TIMENA (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */ @@ -404,7 +404,7 @@ # define FLEXIO_TIMCFG_TIMRST_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */ /* Bit 19: Reserved */ -#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-21: Timer Decrement (TIMDEC) */ +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-21: Timer Decrement (TIMDEC) */ #define FLEXIO_TIMCFG_TIMDEC_MASK (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT) # define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */ # define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */ @@ -412,7 +412,7 @@ # define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTRGIN (0x03 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Trigger input */ /* Bit 23: Reserved */ -#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */ +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */ #define FLEXIO_TIMCFG_TIMOUT_MASK (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT) # define FLEXIO_TIMCFG_TIMOUT_ONE (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */ # define FLEXIO_TIMCFG_TIMOUT_ZERO (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */ diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h index 0d3c7b21ec..df49aa7f72 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_smc.h @@ -72,9 +72,9 @@ /* SMC Power Mode Protection register */ #define SMC_PMPROT_AVLP_SHIFT (5) /* Bit 5: Allow Very-Low-Power Modes */ -#define SMC_PMPROT_AVLP (1 << SMC_PMPROT_AVLP_SHIFT) +#define SMC_PMPROT_AVLP (1 << SMC_PMPROT_AVLP_SHIFT) #define SMC_PMPROT_AHSRUN_SHIFT (7) /* Bit 7: Allow High Speed Run mode */ -#define SMC_PMPROT_AHSRUN (1 << SMC_PMPROT_AHSRUN_SHIFT) +#define SMC_PMPROT_AHSRUN (1 << SMC_PMPROT_AHSRUN_SHIFT) /* SMC Power Mode Control register */ diff --git a/arch/arm/src/s32k3xx/Kconfig b/arch/arm/src/s32k3xx/Kconfig index 384b14cb4b..8f990437c6 100644 --- a/arch/arm/src/s32k3xx/Kconfig +++ b/arch/arm/src/s32k3xx/Kconfig @@ -376,7 +376,7 @@ config S32K3XX_QSPI default n select ARCH_USE_MPU depends on S32K3XX_HAVE_QSPI - + menu "FlexCAN" config S32K3XX_FLEXCAN0 @@ -591,7 +591,7 @@ endmenu # LPUART config S32K3XX_RTC bool "RTC" default n - + config S32K3XX_FS26 bool "FS26 SBC Disable watchdog" default n @@ -1085,11 +1085,11 @@ endmenu # eDMA Global Configuration menu "LPSPI Configuration" depends on S32K3XX_LPSPI - + config S32K3XX_LPSPI_DWORD bool "DWORD up to 64 bit transfer support" default n - + config S32K3XX_LPSPI_DMA bool "SPI DMA" depends on S32K3XX_EDMA @@ -1131,7 +1131,6 @@ config S32K3XX_LPSPI4_DMA depends on S32K3XX_LPSPI4 && S32K3XX_LPSPI_DMA ---help--- Use DMA to improve LPSPI4 transfer performance. - config S32K3XX_LPSPI5_DMA bool "LPSPI5 DMA" @@ -1149,13 +1148,13 @@ config S32K3XX_LPSPI_DMATHRESHOLD When SPI DMA is enabled, small DMA transfers will still be performed by polling logic. But we need a threshold value to determine what is small. - + config S32K3XX_LPSPI0_PINCFG int "LPSPI0 input & data pin config" depends on S32K3XX_LPSPI0 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported @@ -1166,7 +1165,7 @@ config S32K3XX_LPSPI1_PINCFG depends on S32K3XX_LPSPI1 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported @@ -1177,7 +1176,7 @@ config S32K3XX_LPSPI2_PINCFG depends on S32K3XX_LPSPI2 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported @@ -1188,7 +1187,7 @@ config S32K3XX_LPSPI3_PINCFG depends on S32K3XX_LPSPI3 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported @@ -1199,7 +1198,7 @@ config S32K3XX_LPSPI4_PINCFG depends on S32K3XX_LPSPI4 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported @@ -1210,12 +1209,12 @@ config S32K3XX_LPSPI5_PINCFG depends on S32K3XX_LPSPI5 default 0 ---help--- - Configures which pins are used for input and output data during serial transfers. + Configures which pins are used for input and output data during serial transfers. 0 - SIN is used for input data and SOUT is used for output data 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported 3 - SOUT is used for input data and SIN is used for output data - + endmenu # LPSPI Configuration menu "LPI2C Configuration" @@ -1317,15 +1316,15 @@ endmenu # LPI2C Configuration menu "LPUART Configuration" depends on S32K3XX_LPUART - + config S32K3XX_LPUART_INVERT bool "Signal Invert Support" default n - + config S32K3XX_LPUART_SINGLEWIRE bool "Signal Wire Support" default n - + config S32K3XX_SERIAL_RXDMA_BUFFER_SIZE int "RX DMA buffer size" default 64 diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h index 7d9eeec933..4672517d09 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h @@ -170,7 +170,7 @@ #define S32K3XX_ADC_STAW2R_OFFSET (0x038c) /* Self-Test Analog Watchdog S2 Register (STAW2R) */ #define S32K3XX_ADC_STAW4R_OFFSET (0x0394) /* Self-Test Analog Watchdog C0 Register (STAW4R) */ #define S32K3XX_ADC_STAW5R_OFFSET (0x0398) /* Self-Test Analog Watchdog C Register (STAW5R) */ -#define S32K3XX_ADC_AMSIO_OFFSET (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */ +#define S32K3XX_ADC_AMSIO_OFFSET (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */ #define S32K3XX_ADC_CALBISTREG_OFFSET (0x03a0) /* Control and Calibration Status Register (CALBISTREG) */ #define S32K3XX_ADC_OFSGNUSR_OFFSET (0x03a8) /* Offset and Gain User Register (OFSGNUSR) */ #define S32K3XX_ADC_CAL2_OFFSET (0x03b4) /* Calibration Value 2 (CAL2) */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h index b4ee821a4c..a700d4fc6a 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h @@ -548,12 +548,12 @@ #define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM1 (PRAM1_ECC_ERR_EN) */ #define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM0 (PRAM0_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ -#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */ +#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */ /* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */ @@ -809,7 +809,7 @@ # define DCM_GPR_DCMRWF5_BOOT_MODE_FAST (1 << 0) /* Fast Standby */ #define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT (1) /* Bits 1-31: Cortex-M7_0 base address of vector table to be used after exiting (fast) standby mode (BOOT_ADDRESS) */ -#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT) +#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT) /* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h index 4b6e8cd43a..d407798194 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h @@ -312,7 +312,7 @@ /* Bits 5-13: Reserved */ #define EMIOS_C2_UCPRECLK (1 << 14) /* Bit 14: Prescaler Clock Source (UCPRECLK) */ /* Bit 15: Reserved */ -#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */ +#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */ #define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT) #define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK) /* Bits 20-31: Reserved */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h index 5ef603e133..9092acf743 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h @@ -548,7 +548,7 @@ #define S32K3XX_CAN0_ERFIER (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN0_ERFSR (S32K3XX_CAN0_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN0_HR_TIME_STAMP(n) (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN0_HR_TIME_STAMP(n) (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN0_HR_TIME_STAMP0 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN0_HR_TIME_STAMP1 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN0_HR_TIME_STAMP2 (S32K3XX_CAN0_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) @@ -916,7 +916,7 @@ #define S32K3XX_CAN1_ERFIER (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN1_ERFSR (S32K3XX_CAN1_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN1_HR_TIME_STAMP(n) (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN1_HR_TIME_STAMP(n) (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN1_HR_TIME_STAMP0 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN1_HR_TIME_STAMP1 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN1_HR_TIME_STAMP2 (S32K3XX_CAN1_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) @@ -1284,7 +1284,7 @@ #define S32K3XX_CAN2_ERFIER (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN2_ERFSR (S32K3XX_CAN2_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN2_HR_TIME_STAMP(n) (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN2_HR_TIME_STAMP(n) (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN2_HR_TIME_STAMP0 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN2_HR_TIME_STAMP1 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN2_HR_TIME_STAMP2 (S32K3XX_CAN2_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) @@ -1652,7 +1652,7 @@ #define S32K3XX_CAN3_ERFIER (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN3_ERFSR (S32K3XX_CAN3_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN3_HR_TIME_STAMP(n) (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN3_HR_TIME_STAMP(n) (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN3_HR_TIME_STAMP0 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN3_HR_TIME_STAMP1 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN3_HR_TIME_STAMP2 (S32K3XX_CAN3_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) @@ -2020,7 +2020,7 @@ #define S32K3XX_CAN4_ERFIER (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN4_ERFSR (S32K3XX_CAN4_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN4_HR_TIME_STAMP(n) (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN4_HR_TIME_STAMP(n) (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN4_HR_TIME_STAMP0 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN4_HR_TIME_STAMP1 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN4_HR_TIME_STAMP2 (S32K3XX_CAN4_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) @@ -2388,7 +2388,7 @@ #define S32K3XX_CAN5_ERFIER (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFIER_OFFSET) #define S32K3XX_CAN5_ERFSR (S32K3XX_CAN5_BASE + S32K3XX_CAN_ERFSR_OFFSET) -#define S32K3XX_CAN5_HR_TIME_STAMP(n) (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) +#define S32K3XX_CAN5_HR_TIME_STAMP(n) (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP_OFFSET(n)) # define S32K3XX_CAN5_HR_TIME_STAMP0 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP0_OFFSET) # define S32K3XX_CAN5_HR_TIME_STAMP1 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP1_OFFSET) # define S32K3XX_CAN5_HR_TIME_STAMP2 (S32K3XX_CAN5_BASE + S32K3XX_CAN_HR_TIME_STAMP2_OFFSET) diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h index 71b5a41e0a..3e5ce0fdb5 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h @@ -637,7 +637,7 @@ #define FLEXIO_TIMCTL_PINPOL (1 << 7) /* Bit 7: Timer Pin Polarity (PINPOL) */ # define FLEXIO_TIMCTL_PINPOL_HI (0 << 7) /* Pin is active high */ # define FLEXIO_TIMCTL_PINPOL_LO (1 << 7) /* Pin is active low */ -#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-12: Timer Pin Select (PINSEL) */ +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8) /* Bits 8-12: Timer Pin Select (PINSEL) */ #define FLEXIO_TIMCTL_PINSEL_MASK (0x1f << FLEXIO_TIMCTL_PINSEL_SHIFT) # define FLEXIO_TIMCTL_PINSEL(n) (((n) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK) /* Bits 13-15: Reserved */ @@ -671,7 +671,7 @@ # define FLEXIO_TIMCFG_TSTART_DIS (0 << 1) /* Start bit disabled */ # define FLEXIO_TIMCFG_TSTART_ENA (1 << 1) /* Start bit enabled */ /* Bits 2-3: Reserved */ -#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */ +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4) /* Bits 4-5: Timer Stop Bit (TSTOP) */ #define FLEXIO_TIMCFG_TSTOP_MASK (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) # define FLEXIO_TIMCFG_TSTOP_DIS (0x00 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit disabled */ # define FLEXIO_TIMCFG_TSTOP_TIMCMP (0x01 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare */ @@ -679,7 +679,7 @@ # define FLEXIO_TIMCFG_TSTOP_BOTH (0x03 << FLEXIO_TIMCFG_TSTOP_SHIFT) /* Stop bit is enabled on timer compare and timer disable */ /* Bits 6-7: Reserved */ -#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */ +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8) /* Bits 8-10: Timer Enable (TIMENA) */ #define FLEXIO_TIMCFG_TIMENA_MASK (0x07 << FLEXIO_TIMCFG_TIMENA_SHIFT) # define FLEXIO_TIMCFG_TIMENA_ALWAYS (0x00 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer always enabled */ # define FLEXIO_TIMCFG_TIMENA_TIMENA (0x01 << FLEXIO_TIMCFG_TIMENA_SHIFT) /* Timer enabled on Timer N-1 enable */ @@ -713,7 +713,7 @@ # define FLEXIO_TIMCFG_TIMRST_TRGBOTH (0x07 << FLEXIO_TIMCFG_TIMRST_SHIFT) /* Timer reset on Trigger rising or falling edge */ /* Bit 19: Reserved */ -#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-22: Timer Decrement (TIMDEC) */ +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20) /* Bits 20-22: Timer Decrement (TIMDEC) */ #define FLEXIO_TIMCFG_TIMDEC_MASK (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT) # define FLEXIO_TIMCFG_TIMDEC_CLKTIMOUT (0x00 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on FlexIO clock, Shift clock equals Timer output */ # define FLEXIO_TIMCFG_TIMDEC_TRGINBOTHTIMOUT (0x01 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (both edges), Shift clock equals Timer output */ @@ -725,7 +725,7 @@ # define FLEXIO_TIMCFG_TIMDEC_TRGINRISTRGIN (0x07 << FLEXIO_TIMCFG_TIMDEC_SHIFT) /* Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input */ /* Bit 23: Reserved */ -#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */ +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24) /* Bits 24-25: Timer Output (TIMOUT) */ #define FLEXIO_TIMCFG_TIMOUT_MASK (0x03 << FLEXIO_TIMCFG_TIMOUT_SHIFT) # define FLEXIO_TIMCFG_TIMOUT_ONE (0x00 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic one when enabled and is not affected by timer reset */ # define FLEXIO_TIMCFG_TIMOUT_ZERO (0x01 << FLEXIO_TIMCFG_TIMOUT_SHIFT) /* Timer output is logic zero when enabled and is not affected by timer reset */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h index b70839fd9a..47d77803e3 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h @@ -74,7 +74,7 @@ #define S32K3XX_LPI2C0_MDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDER_OFFSET) #define S32K3XX_LPI2C0_MCFGR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET) #define S32K3XX_LPI2C0_MCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET) -#define S32K3XX_LPI2C0_MCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) +#define S32K3XX_LPI2C0_MCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) #define S32K3XX_LPI2C0_MCFGR3 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET) #define S32K3XX_LPI2C0_MDMR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MDMR_OFFSET) #define S32K3XX_LPI2C0_MCCR0 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MCCR0_OFFSET) @@ -85,7 +85,7 @@ #define S32K3XX_LPI2C0_MRDR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_MRDR_OFFSET) #define S32K3XX_LPI2C0_SCR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCR_OFFSET) #define S32K3XX_LPI2C0_SSR (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SSR_OFFSET) -#define S32K3XX_LPI2C0_SIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET) +#define S32K3XX_LPI2C0_SIER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SIER_OFFSET) #define S32K3XX_LPI2C0_SDER (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SDER_OFFSET) #define S32K3XX_LPI2C0_SCFGR1 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET) #define S32K3XX_LPI2C0_SCFGR2 (S32K3XX_LPI2C0_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET) @@ -103,7 +103,7 @@ #define S32K3XX_LPI2C1_MDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDER_OFFSET) #define S32K3XX_LPI2C1_MCFGR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR0_OFFSET) #define S32K3XX_LPI2C1_MCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR1_OFFSET) -#define S32K3XX_LPI2C1_MCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) +#define S32K3XX_LPI2C1_MCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR2_OFFSET) #define S32K3XX_LPI2C1_MCFGR3 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCFGR3_OFFSET) #define S32K3XX_LPI2C1_MDMR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MDMR_OFFSET) #define S32K3XX_LPI2C1_MCCR0 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MCCR0_OFFSET) @@ -114,7 +114,7 @@ #define S32K3XX_LPI2C1_MRDR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_MRDR_OFFSET) #define S32K3XX_LPI2C1_SCR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCR_OFFSET) #define S32K3XX_LPI2C1_SSR (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SSR_OFFSET) -#define S32K3XX_LPI2C1_SIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET) +#define S32K3XX_LPI2C1_SIER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SIER_OFFSET) #define S32K3XX_LPI2C1_SDER (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SDER_OFFSET) #define S32K3XX_LPI2C1_SCFGR1 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR1_OFFSET) #define S32K3XX_LPI2C1_SCFGR2 (S32K3XX_LPI2C1_BASE + S32K3XX_LPI2C_SCFGR2_OFFSET) @@ -141,7 +141,7 @@ /* Parameter Register (PARAM) */ #define LPI2C_PARAM_MTXFIFO_SHIFT (0) /* Bits 0-3: Master Transmit FIFO Size (MTXFIFO) */ -#define LPI2C_PARAM_MTXFIFO_MASK (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT) +#define LPI2C_PARAM_MTXFIFO_MASK (0x0f << LPI2C_PARAM_MTXFIFO_SHIFT) # define LPI2C_PARAM_MTXFIFO_1_WORDS (0x00 << LPI2C_PARAM_MTXFIFO_SHIFT) # define LPI2C_PARAM_MTXFIFO_2_WORDS (0x01 << LPI2C_PARAM_MTXFIFO_SHIFT) # define LPI2C_PARAM_MTXFIFO_4_WORDS (0x02 << LPI2C_PARAM_MTXFIFO_SHIFT) @@ -287,7 +287,7 @@ /* Master Config Register 2 (MCFGR2) */ #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0) /* Bits 0-11: Bus Idle Timeout (BUSIDLE) */ -#define LPI2C_MCFGR2_BUSIDLE_MASK (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT) +#define LPI2C_MCFGR2_BUSIDLE_MASK (0x0fff << LPI2C_MCFGR2_BUSIDLE_SHIFT) #define LPI2C_MCFGR2_BUSIDLE_DISABLE (0x0000 << LPI2C_MCFGR2_BUSIDLE_SHIFT) # define LPI2C_MCFGR2_BUSIDLE(n) (((n) << LPI2C_MCFGR2_BUSIDLE_SHIFT) & LPI2C_MCFGR2_BUSIDLE_MASK) /* Bits 12-15: Reserved */ @@ -306,7 +306,7 @@ /* Bits 0-7: Reserved */ #define LPI2C_MCFGR3_PINLOW_SHIFT (8) /* Bits 8-19: Pin Low Timeout (PINLOW) */ -#define LPI2C_MCFGR3_PINLOW_MASK (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT) +#define LPI2C_MCFGR3_PINLOW_MASK (0x0fff << LPI2C_MCFGR3_PINLOW_SHIFT) # define LPI2C_MCFGR3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFGR3_PINLOW_SHIFT) & LPI2C_MCFGR3_PINLOW_MASK) /* Bits 20-31: Reserved */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h index 65aa0f2a9f..a99bf400b5 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h @@ -173,7 +173,7 @@ #define MC_RGM_FRENTC_FRET_EN (1 << 0) /* Bit 0: Functional Reset Entry Timer Enable (FRET_EN) */ #define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1) /* Bits 1-31: Functional Reset Entry Timer Value (FRET_TIMEOUT) */ -#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT) +#define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0x7fffffff << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT) /* Low Power Debug Control Register (LPDEBUG) */ diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h index 91aa869cd1..86343e7338 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h @@ -418,9 +418,9 @@ #define QSPI_LUT_OPRND0(n) (((n) << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK) #define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */ #define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT) -# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */ -# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */ -# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */ +# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */ +# define QSPI_LUT_PAD0_2 (0x01 << QSPI_LUT_PAD0_SHIFT) /* 2 Pad */ +# define QSPI_LUT_PAD0_4 (0x02 << QSPI_LUT_PAD0_SHIFT) /* 4 Pad */ #define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */ #define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT) @@ -431,9 +431,9 @@ #define QSPI_LUT_OPRND1(n) (((n) << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK) #define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */ #define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT) -# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */ -# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */ -# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */ +# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */ +# define QSPI_LUT_PAD1_2 (0x01 << QSPI_LUT_PAD1_SHIFT) /* 2 Pad */ +# define QSPI_LUT_PAD1_4 (0x02 << QSPI_LUT_PAD1_SHIFT) /* 4 Pad */ #define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */ #define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT) diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h index cf6264db1c..8880855ef9 100644 --- a/arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h +++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h @@ -95,7 +95,7 @@ #define WKPU_NCR_NFEE0 (1 << 25) /* Bit 25: NMI Falling-edge Events Enable 0 (NFEE0) */ #define WKPU_NCR_NREE0 (1 << 26) /* Bit 26: NMI Rising-Edge Events Enable 0 (NREE0) */ /* Bit 27: Reserved */ -#define WKPU_NCR_NWRE0 (1 << 28) /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */ +#define WKPU_NCR_NWRE0 (1 << 28) /* Bit 28: NMI Wakeup Request Enable 0 (NWRE0) */ #define WKPU_NCR_NDSS0_SHIFT (29) /* Bits 29-30: NMI Destination Source Select 0 (NDSS0) */ #define WKPU_NCR_NDSS0_MASK (0x03 << WKPU_NCR_NDSS0_SHIFT) # define WKPU_NCR_NDSS0_NMI (0x00 << WKPU_NCR_NDSS0_SHIFT) /* Non-maskable interrupt */ diff --git a/arch/arm/src/s32k3xx/s32k3xx_emac.c b/arch/arm/src/s32k3xx/s32k3xx_emac.c index 8f4d734154..89a12f3067 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_emac.c +++ b/arch/arm/src/s32k3xx/s32k3xx_emac.c @@ -73,7 +73,7 @@ /* Memory synchronization */ -#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0) +#define MEMORY_SYNC() //do { ARM_DSB(); ARM_ISB(); } while (0) /* If processing is not done at the interrupt level, then work queue support * is required. diff --git a/arch/arm/src/sama5/sam_flexcom_spi.c b/arch/arm/src/sama5/sam_flexcom_spi.c index f13055ab65..a5aaa08a87 100644 --- a/arch/arm/src/sama5/sam_flexcom_spi.c +++ b/arch/arm/src/sama5/sam_flexcom_spi.c @@ -681,7 +681,7 @@ static inline struct sam_flex_spidev_s *flex_spi_dev(struct sam_flex_spics_s case 4: return &g_flexcom4dev; break; -#endif +#endif default: /* shouldn't get here */ diff --git a/arch/arm/src/sama5/sam_mcan.c b/arch/arm/src/sama5/sam_mcan.c index a2327bc53c..ef27094e06 100644 --- a/arch/arm/src/sama5/sam_mcan.c +++ b/arch/arm/src/sama5/sam_mcan.c @@ -78,7 +78,7 @@ # define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_PLLA # define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_PLLA_FREQUENCY #elif defined(CONFIG_SAMA5_MCAN_CLKSRC_UPLL) -# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_UPLL +# define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_UPLL # define SAMA5_MCAN_CLKSRC_FREQUENCY BOARD_UPLL_FREQUENCY #elif defined(CONFIG_SAMA5_MCAN_CLKSRC_MCK) # define SAMA5_MCAN_CLKSRC PMC_PCR_GCKCSS_MCK @@ -1016,7 +1016,7 @@ static const struct sam_config_s g_mcan0const = .pid = SAM_PID_MCAN00, .irq0 = SAM_IRQ_MCAN00, .irq1 = SAM_IRQ_MCAN01, -#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1) +#if defined(CONFIG_SAMA5_MCAN0_ISO11898_1) .mode = MCAN_ISO11898_1_MODE, #elif defined(CONFIG_SAMA5_MCAN0_FD) .mode = MCAN_FD_MODE, diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 76a4daf1c1..6d56c6dd31 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -151,7 +151,7 @@ # elif defined(CONFIG_SAMA5_UART4) # define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */ # define UART4_ASSIGNED 1 -# elif defined(CONFIG_SAMA5_USART0) +# elif defined(CONFIG_SAMA5_USART0) # define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */ # define USART0_ASSIGNED 1 # elif defined(CONFIG_SAMA5_USART1) diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index 5f36fd82ae..8323f43e03 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -1564,7 +1564,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv) * been initialised. It's the only option allowed and that works. */ -#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED /* if we're allowed to use pendet trigger no need to do this */ regval = sam_adc_getreg(priv, SAM_ADC_TRGR); diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c index 237f2f6ebc..951ff45ea9 100644 --- a/arch/arm/src/sama5/sama5d2x_pio.c +++ b/arch/arm/src/sama5/sama5d2x_pio.c @@ -214,7 +214,7 @@ static uint32_t sam_configcommon(pio_pinset_t cfgset) { if ((cfgset & PIO_CFG_SLOWCLK) != 0) { - regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK); + regval |= (PIO_CFGR_IFEN | PIO_CFG_SLOWCLK); } else { diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index e062b5453f..9cf769e8a7 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -2689,7 +2689,7 @@ config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED This option configures the stm32_dmacapable to not disqualify DMA operations on memory that is not dcache aligned based solely on the starting address and byte count. - + Use this when ALL buffer extents are known to be aligned, but the the count does not use the complete buffer. diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index b39ca7dd66..93d1def5db 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -432,7 +432,7 @@ config STM32_APP_FORMAT_MCUBOOT select STM32_HAVE_OTA_PARTITION depends on EXPERIMENTAL ---help--- - The MCUboot support of loading the firmware images. + The MCUboot support of loading the firmware images. comment "MCUboot support depends on CONFIG_EXPERIMENTAL" depends on !EXPERIMENTAL diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index ec8df411e5..372bf7c214 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -338,7 +338,7 @@ # if CONFIG_STM32L4_ADC1_EXTTRIG > 0 # define ADC1_EXTCFG_VALUE \ ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) # endif #endif /* CONFIG_STM32L4_ADC1_EXTTRIG */ @@ -352,7 +352,7 @@ # if CONFIG_STM32L4_ADC2_EXTTRIG > 0 # define ADC2_EXTCFG_VALUE \ ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) # endif #endif /* CONFIG_STM32L4_ADC2_EXTTRIG */ @@ -366,7 +366,7 @@ # if CONFIG_STM32L4_ADC3_EXTTRIG > 0 # define ADC3_EXTCFG_VALUE \ ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) + ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) # endif #endif /* CONFIG_STM32L4_ADC3_EXTTRIG */ @@ -387,7 +387,7 @@ # if CONFIG_STM32L4_ADC1_JEXTTRIG > 0 # define ADC1_JEXTCFG_VALUE \ ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) # endif #endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */ @@ -399,7 +399,7 @@ # if CONFIG_STM32L4_ADC2_JEXTTRIG > 0 # define ADC2_JEXTCFG_VALUE \ ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) # endif #endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */ @@ -411,7 +411,7 @@ # if CONFIG_STM32L4_ADC3_JEXTTRIG > 0 # define ADC3_JEXTCFG_VALUE \ ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) + ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) # endif #endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h index 2256b1d32b..ba4e851cca 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h @@ -141,7 +141,7 @@ # define PWR_CR3_RRS_4K_ON (2 << PWE_CR3_RRS_SHIFT) /* 10: Upper 4KB of SRAM2 powered on in Standby-mode */ #define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ #define PWR_CR3_ULPMEN (1 << 11) /* Bit 11: Ultra-low-power mode enable */ -#define PWR_CR3_UCPD_STBY (1 << 13) /* Bit 13: USB Type-C power delivery Standby-mode */ +#define PWR_CR3_UCPD_STBY (1 << 13) /* Bit 13: USB Type-C power delivery Standby-mode */ #define PWR_CR3_UCPD_DBDIS (1 << 14) /* Bit 14: USB Type-C power delivery dead battery disable */ /* Power control register 4 */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index 60da5d5742..14531b8448 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -228,7 +228,7 @@ #define FLASH_NSCR_PNB_MASK (0x7F << FLASH_NSCR_PNB_SHIFT) #define FLASH_NSCR_PNB(n) ((n) << FLASH_NSCR_PNB_SHIFT) /* Page n, n = 0..127 */ #define FLASH_NSCR_BKER (1 << 11) /* Bit 11: Non-secure bank selection for page erase */ -#define FLASH_NSCR_BWR (1 << 14) /* Bit 14: Non-secure burst write programming mode */ +#define FLASH_NSCR_BWR (1 << 14) /* Bit 14: Non-secure burst write programming mode */ #define FLASH_NSCR_MER2 (1 << 15) /* Bit 15: Non-secure bank 2 mass erase */ #define FLASH_NSCR_STRT (1 << 16) /* Bit 16: Non-secure start */ #define FLASH_NSCR_OPTSTRT (1 << 17) /* Bit 17: Options modification start */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_pwr.h b/arch/arm/src/stm32u5/hardware/stm32_pwr.h index ee84924371..d0a52c820f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pwr.h @@ -180,7 +180,7 @@ /* PWR Disable backup domain register */ -#define PWR_DBPR_DBP (1 << 0) /* Bit 0: Disable Backup domain write protection. */ +#define PWR_DBPR_DBP (1 << 0) /* Bit 0: Disable Backup domain write protection. */ /* PWR Supply voltage monitoring status register */ diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 51063c6c84..d80b2f6b66 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -348,7 +348,7 @@ config STM32WB_SRAM2A_INIT memory can trigger parity faults from the random data. This can be avoided by first writing to all locations to force the parity into a valid state. - However, if the SRAM2a is being retained in Standby mode, this may be + However, if the SRAM2a is being retained in Standby mode, this may be undesirable (because it will destroy the contents). In that case, the board should handle the initialization itself at the appropriate time. @@ -359,7 +359,7 @@ config STM32WB_SRAM2B_HEAP config STM32WB_SRAM2B_USER_SIZE int "SRAM2b user application size" default 32768 - range 0 32768 + range 0 32768 depends on STM32WB_SRAM2B_HEAP ---help--- For any CPU2 firmware supporting the BLE protocol the ending part of @@ -1013,7 +1013,7 @@ config STM32WB_BLE_SLAVE_SCA ---help--- Sleep clock accuracy (ppm value) in slave mode. -choice +choice prompt "Sleep clock accuracy in master mode" default STM32WB_BLE_MASTER_SCA_0 ---help--- @@ -1056,7 +1056,7 @@ config STM32WB_BLE_MASTER_SCA default 1 if STM32WB_BLE_MASTER_SCA_1 default 0 -choice +choice prompt "Low speed clock source" default STM32WB_BLE_LS_CLK_SRC_LSE ---help--- @@ -1112,7 +1112,7 @@ config STM32WB_BLE_CHAN_SEL_ALG2 bool "Enable channel selection algorithm 2" default n -choice +choice prompt "Power class" default STM32WB_BLE_POWER_CLASS_2_3 @@ -1134,7 +1134,7 @@ config STM32WB_BLE_MAX_TX_POWER range -127 20 default 0 -choice +choice prompt "AGC RSSI model" default STM32WB_BLE_AGC_RSSI_LEGACY diff --git a/arch/arm/src/tiva/Kconfig b/arch/arm/src/tiva/Kconfig index 1d69cb7680..f939096b8c 100644 --- a/arch/arm/src/tiva/Kconfig +++ b/arch/arm/src/tiva/Kconfig @@ -1522,17 +1522,17 @@ menu "CAN Driver Configuration" choice prompt "CAN bus driver selection" default TIVA_SOCKET_CAN - + config TIVA_SOCKET_CAN bool "Use SocketCAN driver" depends on (TIVA_CAN0 || TIVA_CAN1) && NET_CAN select NET_CAN_HAVE_ERRORS - + config TIVA_CHAR_DEV_CAN bool "Character device driver" depends on (TIVA_CAN0 || TIVA_CAN1) && !NET_CAN select ARCH_HAVE_CAN_ERRORS - + endchoice # CAN driver selection config TIVA_CAN0_PRIO @@ -1544,12 +1544,12 @@ config TIVA_CAN0_PRIO than in the ISR or using a work queue. The ISR signals the kthread, but the kthread can be preempted if needed. This option sets the thread priority for CAN module 0. - + config TIVA_CAN0_BAUD int "CAN0 baud rate kb/s" default 125 depends on TIVA_CAN0 && TIVA_SOCKET_CAN - + config TIVA_CAN1_BAUD int "CAN1 baud rate kb/s" default 125 diff --git a/arch/arm64/src/common/arm64_gic.h b/arch/arm64/src/common/arm64_gic.h index 73fa4b4b68..4cc1b01e2f 100644 --- a/arch/arm64/src/common/arm64_gic.h +++ b/arch/arm64/src/common/arm64_gic.h @@ -110,7 +110,7 @@ #define GICD_TYPER_RSS BIT(26) #define GICD_TYPER_LPIS BIT(17) #define GICD_TYPER_MBIS BIT(16) -#define GICD_TYPER_ESPI BIT(8) +#define GICD_TYPER_ESPI BIT(8) #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1) #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1) #define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32) diff --git a/arch/avr/src/at32uc3/Make.defs b/arch/avr/src/at32uc3/Make.defs index 4b0f23fb57..81a59db525 100644 --- a/arch/avr/src/at32uc3/Make.defs +++ b/arch/avr/src/at32uc3/Make.defs @@ -29,7 +29,7 @@ CMN_CSRCS = avr_allocateheap.c avr_copystate.c avr_createstack.c avr_exit.c CMN_CSRCS += avr_mdelay.c avr_udelay.c avr_initialize.c avr_initialstate.c avr_idle.c CMN_CSRCS += avr_modifyreg8.c avr_modifyreg16.c avr_modifyreg32.c avr_releasestack.c CMN_CSRCS += avr_schedulesigaction.c avr_sigdeliver.c avr_stackframe.c avr_switchcontext.c -CMN_CSRCS += avr_usestack.c avr_doirq.c avr_nputs.c avr_registerdump.c avr_getintstack.c +CMN_CSRCS += avr_usestack.c avr_doirq.c avr_nputs.c avr_registerdump.c avr_getintstack.c # Required AT32UC3 files diff --git a/arch/renesas/src/rx65n/rx65n_usbhost.c b/arch/renesas/src/rx65n/rx65n_usbhost.c index ee1cd6691f..51b516f0d7 100644 --- a/arch/renesas/src/rx65n/rx65n_usbhost.c +++ b/arch/renesas/src/rx65n/rx65n_usbhost.c @@ -2856,7 +2856,7 @@ void usb_hstd_brdy_pipe_process(uint16_t bitsts) (NULL == g_rx65n_edlist[i].xfrinfo->callback)) #else if (i == g_kbdpipe) -#endif +#endif { usb_cstd_clr_stall(i); } diff --git a/arch/renesas/src/sh1/Make.defs b/arch/renesas/src/sh1/Make.defs index f346e87a8b..29036314f5 100644 --- a/arch/renesas/src/sh1/Make.defs +++ b/arch/renesas/src/sh1/Make.defs @@ -24,7 +24,7 @@ CMN_CSRCS = renesas_allocateheap.c renesas_createstack.c renesas_doirq.c CMN_CSRCS += renesas_exit.c renesas_getintstack.c renesas_initialize.c CMN_CSRCS += renesas_idle.c renesas_initialstate.c renesas_lowputs.c CMN_CSRCS += renesas_mdelay.c renesas_nputs.c renesas_releasestack.c -CMN_CSRCS += renesas_stackframe.c renesas_switchcontext.c renesas_udelay.c +CMN_CSRCS += renesas_stackframe.c renesas_switchcontext.c renesas_udelay.c CMN_CSRCS += renesas_usestack.c sh1_schedulesigaction.c sh1_sigdeliver.c CHIP_ASRCS = sh1_vector.S sh1_saveusercontext.S diff --git a/arch/risc-v/include/esp32c6/irq.h b/arch/risc-v/include/esp32c6/irq.h index 51ff111ee0..2c72d25393 100644 --- a/arch/risc-v/include/esp32c6/irq.h +++ b/arch/risc-v/include/esp32c6/irq.h @@ -107,9 +107,9 @@ #define ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH 59 /* interrupt of system timer 2, EDGE */ #define ESP32C6_APB_ADC_PERIPH 60 /* interrupt of APB ADC, level */ #define ESP32C6_MCPWM0_PERIPH 61 /* interrupt of MCPWM0, level */ -#define ESP32C6_PCNT_PERIPH 62 +#define ESP32C6_PCNT_PERIPH 62 #define ESP32C6_PARL_IO_PERIPH 63 -#define ESP32C6_SLC0_PERIPH 64 +#define ESP32C6_SLC0_PERIPH 64 #define ESP32C6_SLC_PERIPH 65 #define ESP32C6_DMA_IN_CH0_PERIPH 66 /* interrupt of general DMA IN channel 0, level */ #define ESP32C6_DMA_IN_CH1_PERIPH 67 /* interrupt of general DMA IN channel 1, level */ @@ -117,7 +117,7 @@ #define ESP32C6_DMA_OUT_CH0_PERIPH 69 /* interrupt of general DMA OUT channel 0, level */ #define ESP32C6_DMA_OUT_CH1_PERIPH 70 /* interrupt of general DMA OUT channel 1, level */ #define ESP32C6_DMA_OUT_CH2_PERIPH 71 /* interrupt of general DMA OUT channel 2, level */ -#define ESP32C6_GSPI2_PERIPH 72 +#define ESP32C6_GSPI2_PERIPH 72 #define ESP32C6_AES_PERIPH 73 /* interrupt of AES accelerator, level */ #define ESP32C6_SHA_PERIPH 74 /* interrupt of SHA accelerator, level */ #define ESP32C6_RSA_PERIPH 75 /* interrupt of RSA accelerator, level */ diff --git a/arch/risc-v/src/bl602/bl602_lowputc.c b/arch/risc-v/src/bl602/bl602_lowputc.c index f32548dcca..06dd41784f 100644 --- a/arch/risc-v/src/bl602/bl602_lowputc.c +++ b/arch/risc-v/src/bl602/bl602_lowputc.c @@ -52,7 +52,7 @@ ****************************************************************************/ #define UART_PARITY_NONE (0) -#define UART_PARITY_ODD (1) +#define UART_PARITY_ODD (1) #define UART_PARITY_EVEN (2) /* Select UART parameters for the selected console */ diff --git a/arch/risc-v/src/bl602/hardware/bl602_uart.h b/arch/risc-v/src/bl602/hardware/bl602_uart.h index b36693d205..7ee43d0e87 100644 --- a/arch/risc-v/src/bl602/hardware/bl602_uart.h +++ b/arch/risc-v/src/bl602/hardware/bl602_uart.h @@ -76,41 +76,41 @@ #define BL602_UART_FIFO_WDATA(n) (BL602_UART_BASE(n) + BL602_UART_FIFO_WDATA_OFFSET) #define BL602_UART_FIFO_RDATA(n) (BL602_UART_BASE(n) + BL602_UART_FIFO_RDATA_OFFSET) -#define BL602_UART0_UTX_CONFIG (BL602_UART_UTX_CONFIG(0)) -#define BL602_UART0_URX_CONFIG (BL602_UART_URX_CONFIG(0)) -#define BL602_UART0_UART_BIT_PRD (BL602_UART_BIT_PRD(0)) -#define BL602_UART0_DATA_CONFIG (BL602_UART_DATA_CONFIG(0)) -#define BL602_UART0_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(0)) -#define BL602_UART0_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(0)) -#define BL602_UART0_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(0)) -#define BL602_UART0_UART_INT_STS (BL602_UART_INT_STS(0)) -#define BL602_UART0_UART_INT_MASK (BL602_UART_INT_MASK(0)) -#define BL602_UART0_UART_INT_CLEAR (BL602_UART_INT_CLEAR(0)) -#define BL602_UART0_UART_INT_EN (BL602_UART_INT_EN(0)) -#define BL602_UART0_UART_STATUS (BL602_UART_STATUS(0)) -#define BL602_UART0_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(0)) -#define BL602_UART0_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(0)) -#define BL602_UART0_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(0)) -#define BL602_UART0_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(0)) -#define BL602_UART0_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(0)) +#define BL602_UART0_UTX_CONFIG (BL602_UART_UTX_CONFIG(0)) +#define BL602_UART0_URX_CONFIG (BL602_UART_URX_CONFIG(0)) +#define BL602_UART0_UART_BIT_PRD (BL602_UART_BIT_PRD(0)) +#define BL602_UART0_DATA_CONFIG (BL602_UART_DATA_CONFIG(0)) +#define BL602_UART0_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(0)) +#define BL602_UART0_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(0)) +#define BL602_UART0_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(0)) +#define BL602_UART0_UART_INT_STS (BL602_UART_INT_STS(0)) +#define BL602_UART0_UART_INT_MASK (BL602_UART_INT_MASK(0)) +#define BL602_UART0_UART_INT_CLEAR (BL602_UART_INT_CLEAR(0)) +#define BL602_UART0_UART_INT_EN (BL602_UART_INT_EN(0)) +#define BL602_UART0_UART_STATUS (BL602_UART_STATUS(0)) +#define BL602_UART0_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(0)) +#define BL602_UART0_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(0)) +#define BL602_UART0_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(0)) +#define BL602_UART0_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(0)) +#define BL602_UART0_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(0)) -#define BL602_UART1_UTX_CONFIG (BL602_UART_UTX_CONFIG(1)) -#define BL602_UART1_URX_CONFIG (BL602_UART_URX_CONFIG(1)) -#define BL602_UART1_UART_BIT_PRD (BL602_UART_BIT_PRD(1)) -#define BL602_UART1_DATA_CONFIG (BL602_UART_DATA_CONFIG(1)) -#define BL602_UART1_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(1)) -#define BL602_UART1_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(1)) -#define BL602_UART1_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(1)) -#define BL602_UART1_UART_INT_STS (BL602_UART_INT_STS(1)) -#define BL602_UART1_UART_INT_MASK (BL602_UART_INT_MASK(1)) -#define BL602_UART1_UART_INT_CLEAR (BL602_UART_INT_CLEAR(1)) -#define BL602_UART1_UART_INT_EN (BL602_UART_INT_EN(1)) -#define BL602_UART1_UART_STATUS (BL602_UART_STATUS(1)) -#define BL602_UART1_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(1)) -#define BL602_UART1_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(1)) -#define BL602_UART1_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(1)) -#define BL602_UART1_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(1)) -#define BL602_UART1_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(1)) +#define BL602_UART1_UTX_CONFIG (BL602_UART_UTX_CONFIG(1)) +#define BL602_UART1_URX_CONFIG (BL602_UART_URX_CONFIG(1)) +#define BL602_UART1_UART_BIT_PRD (BL602_UART_BIT_PRD(1)) +#define BL602_UART1_DATA_CONFIG (BL602_UART_DATA_CONFIG(1)) +#define BL602_UART1_UTX_IR_POSITION (BL602_UART_UTX_IR_POSITION(1)) +#define BL602_UART1_URX_IR_POSITION (BL602_UART_URX_IR_POSITION(1)) +#define BL602_UART1_URX_RTO_TIMER (BL602_UART_URX_RTO_TIMER(1)) +#define BL602_UART1_UART_INT_STS (BL602_UART_INT_STS(1)) +#define BL602_UART1_UART_INT_MASK (BL602_UART_INT_MASK(1)) +#define BL602_UART1_UART_INT_CLEAR (BL602_UART_INT_CLEAR(1)) +#define BL602_UART1_UART_INT_EN (BL602_UART_INT_EN(1)) +#define BL602_UART1_UART_STATUS (BL602_UART_STATUS(1)) +#define BL602_UART1_STS_URX_ABR_PRD (BL602_UART_STS_URX_ABR_PRD(1)) +#define BL602_UART1_UART_FIFO_CONFIG_0 (BL602_UART_FIFO_CONFIG_0(1)) +#define BL602_UART1_UART_FIFO_CONFIG_1 (BL602_UART_FIFO_CONFIG_1(1)) +#define BL602_UART1_UART_FIFO_WDATA (BL602_UART_FIFO_WDATA(1)) +#define BL602_UART1_UART_FIFO_RDATA (BL602_UART_FIFO_RDATA(1)) /* Register bit definitions *************************************************/ diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs index fde6828710..e7676e2bf4 100644 --- a/arch/risc-v/src/common/Make.defs +++ b/arch/risc-v/src/common/Make.defs @@ -28,12 +28,12 @@ CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_mhartid.S # Specify C code within the common directory to be included CMN_CSRCS += riscv_initialize.c riscv_swint.c riscv_mtimer.c CMN_CSRCS += riscv_allocateheap.c riscv_createstack.c riscv_copystate.c -CMN_CSRCS += riscv_cpuidlestack.c riscv_doirq.c riscv_exit.c riscv_exception.c +CMN_CSRCS += riscv_cpuidlestack.c riscv_doirq.c riscv_exit.c riscv_exception.c CMN_CSRCS += riscv_getnewintctx.c riscv_getintstack.c riscv_initialstate.c CMN_CSRCS += riscv_idle.c riscv_modifyreg32.c riscv_nputs.c riscv_releasestack.c CMN_CSRCS += riscv_registerdump.c riscv_stackframe.c riscv_schedulesigaction.c CMN_CSRCS += riscv_sigdeliver.c riscv_switchcontext.c riscv_saveusercontext.c -CMN_CSRCS += riscv_usestack.c riscv_tcbinfo.c +CMN_CSRCS += riscv_usestack.c riscv_tcbinfo.c ifneq ($(CONFIG_ALARM_ARCH),y) ifneq ($(CONFIG_TIMER_ARCH),y) diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs index 9c7e6a4719..44c14a05b6 100644 --- a/arch/risc-v/src/common/Toolchain.defs +++ b/arch/risc-v/src/common/Toolchain.defs @@ -133,7 +133,7 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) ARCHRVISAA = a ZARCHRVISAA := +a endif - + ifeq ($(CONFIG_ARCH_RV_ISA_C),y) ARCHRVISAC = c ZARCHRVISAC := +c diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.c b/arch/risc-v/src/esp32c3/esp32c3_ledc.c index b8b984b15c..74011eb820 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ledc.c +++ b/arch/risc-v/src/esp32c3/esp32c3_ledc.c @@ -62,9 +62,9 @@ # if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1 # define LEDC_TIM0_CHANS CONFIG_ESP32C3_LEDC_TIM0_CHANNELS # else -# define LEDC_TIM0_CHANS (1) +# define LEDC_TIM0_CHANS (1) # endif -# define LEDC_TIM0_CHANS_OFF (0) +# define LEDC_TIM0_CHANS_OFF (0) #endif /* LEDC timer1 channels and offset */ @@ -75,7 +75,7 @@ # else # define LEDC_TIM1_CHANS (1) # endif -# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS) +# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS) #endif /* LEDC timer2 channels and offset */ @@ -100,7 +100,7 @@ /* LEDC timer max clock divider parameter */ -#define LEDC_CLKDIV_MAX (1024) /* 2^10 */ +#define LEDC_CLKDIV_MAX (1024) /* 2^10 */ /* LEDC timer registers mapping */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c index d08f591510..8c9ed90935 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c +++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c @@ -46,7 +46,7 @@ #define ESP_IW_EVENT_SIZE(field) \ (offsetof(struct iw_event, u) + sizeof(((union iwreq_data *)0)->field)) -#ifdef CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE +#ifdef CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE # define WIFI_SCAN_RESULT_SIZE CONFIG_ESP32C3_WIFI_SCAN_RESULT_SIZE #else # define WIFI_SCAN_RESULT_SIZE (4096) diff --git a/arch/risc-v/src/k210/k210_head.S b/arch/risc-v/src/k210/k210_head.S index 03045997e3..77f618d4f3 100644 --- a/arch/risc-v/src/k210/k210_head.S +++ b/arch/risc-v/src/k210/k210_head.S @@ -75,7 +75,7 @@ __start: /* * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * + * * Note: Reserve some space used by up_initial_state since we are already * running and using the per CPU idle stack. */ diff --git a/arch/risc-v/src/litex/Kconfig b/arch/risc-v/src/litex/Kconfig index 56f94b03fa..a388a8cec1 100644 --- a/arch/risc-v/src/litex/Kconfig +++ b/arch/risc-v/src/litex/Kconfig @@ -41,7 +41,7 @@ config LITEX_USE_CUSTOM_IRQ_DEFINITIONS ---help--- Use custom definitions for risc-v IRQ numbers and sequence. Allowing for the definitions in arch/risc-v/include/litex/irq.h to be overridden. - + if LITEX_USE_CUSTOM_IRQ_DEFINITIONS config LITEX_CUSTOM_IRQ_DEFINITIONS_PATH diff --git a/arch/risc-v/src/litex/litex_pwm.c b/arch/risc-v/src/litex/litex_pwm.c index c502cac04d..db0175a63c 100644 --- a/arch/risc-v/src/litex/litex_pwm.c +++ b/arch/risc-v/src/litex/litex_pwm.c @@ -45,7 +45,7 @@ #error PWM puslecount not supported for Litex. #endif #ifdef CONFIG_PWM_MULTICHAN -#error PWM multichannel not supported for Litex. +#error PWM multichannel not supported for Litex. #endif /* Control register offsets from peripheral base address */ diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index 4489adba2b..58a172b788 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -130,7 +130,7 @@ choice prompt "Choose DDR type" depends on MPFS_DDR_INIT default MPFS_DDR_TYPE_LPDDR4 - + config MPFS_DDR_TYPE_DDR3 bool "Use DDR3" diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_head.S b/arch/risc-v/src/qemu-rv/qemu_rv_head.S index aad807fee1..4cce5e1ed2 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_head.S +++ b/arch/risc-v/src/qemu-rv/qemu_rv_head.S @@ -86,7 +86,7 @@ __start: /* * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * + * * Note: Reserve some space used by up_initial_state since we are already * running and using the per CPU idle stack. */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h index 1f986f1694..7dac09359f 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_lpuart.h @@ -156,7 +156,7 @@ #define LPUART_CTRL_RIE (1 << 21) /* Bit21: Receiver Interrupt Enable */ #define LPUART_CTRL_ILIE (1 << 20) /* Bit20: Idle Line Interrupt Enable */ #define LPUART_CTRL_TE (1 << 19) /* Bit19: Transmitter Enable */ -#define LPUART_CTRL_RE (1 << 18) /* Bit18: Receiver Enable */ +#define LPUART_CTRL_RE (1 << 18) /* Bit18: Receiver Enable */ #define LPUART_CTRL_RWU (1 << 17) /* Bit17: Receiver Wakeup Control */ #define LPUART_CTRL_SBK (1 << 16) /* Bit16: Send Break */ #define LPUART_CTRL_MA1IE (1 << 15) /* Bit15: Match 1 Interrupt Enable */ diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h index cd133b063a..f8b81835b7 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_pcc.h @@ -92,7 +92,7 @@ /* Register Bitfield Definitions ********************************************/ #define PCC_CLKCFG_PCD_SHIFT (0) -#define PCC_CLKCFG_PCD_MASK (7 << PCC_CLKCFG_PCD_SHIFT) +#define PCC_CLKCFG_PCD_MASK (7 << PCC_CLKCFG_PCD_SHIFT) #define PCC_CLKCFG_PCD_DIV1 (0 << PCC_CLKCFG_PCD_SHIFT) #define PCC_CLKCFG_PCD_DIV2 (1 << PCC_CLKCFG_PCD_SHIFT) #define PCC_CLKCFG_PCD_DIV3 (2 << PCC_CLKCFG_PCD_SHIFT) diff --git a/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h b/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h index 441179a35f..b13905ab62 100644 --- a/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h +++ b/arch/risc-v/src/rv32m1/hardware/rv32m1_wdog.h @@ -44,7 +44,7 @@ # define RV32M1_WDOG_BASE RV32M1_WDOG0_BASE #elif defined(CONFIG_ARCH_CHIP_RV32M1_ZERORISCY) # define RV32M1_WDOG_BASE RV32M1_WDOG1_BASE -#else +#else # error "Unsupported RV32M1 Watch dog" #endif diff --git a/arch/risc-v/src/rv32m1/rv32m1_linker.h b/arch/risc-v/src/rv32m1/rv32m1_linker.h index 71108d27e2..cd3d027631 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_linker.h +++ b/arch/risc-v/src/rv32m1/rv32m1_linker.h @@ -52,7 +52,7 @@ # define LOCATE_ITCM locate_code(SECTION_ITCM) /* System ITCM */ # define LOCATE_UITCM locate_code(SECTION_UITCM) /* User ITCM */ #else -# define LOCATE_ITCM +# define LOCATE_ITCM # define LOCATE_UITCM #endif diff --git a/arch/risc-v/src/rv32m1/rv32m1_serial.c b/arch/risc-v/src/rv32m1/rv32m1_serial.c index cfaf169ffa..cbc2a1be36 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_serial.c +++ b/arch/risc-v/src/rv32m1/rv32m1_serial.c @@ -64,7 +64,7 @@ struct rv32m1_tty_s #ifdef USE_SERIALDRIVER -#ifdef HAVE_UART +#ifdef HAVE_UART #if defined(CONFIG_RV32M1_LPUART0) # define RV32M1_LPUART0_DEV g_uart0dev diff --git a/arch/sparc/src/bm3803/bm3803-uart.h b/arch/sparc/src/bm3803/bm3803-uart.h index e93622ac5b..f3567c8fc4 100644 --- a/arch/sparc/src/bm3803/bm3803-uart.h +++ b/arch/sparc/src/bm3803/bm3803-uart.h @@ -128,17 +128,17 @@ : (UART_CONTROL &= ~(MSK_UART_ENABLE_RXIT | MSK_UART_ENABLE_TXIT))\ ) \ ) \ - ) + ) #define uart1_flow_ctrl_config(uart_flow) ( uart_flow == ON \ ? (BM3803_REG.uart_ctrl1 |= MSK_UART_ENABLE_FLOW) \ : (BM3803_REG.uart_ctrl1 &= ~MSK_UART_ENABLE_FLOW) \ - ) + ) #define uart1_loopback_config(uart_loopb) ( uart_loopb == ON \ ? (BM3803_REG.uart_ctrl1 |= MSK_UART_LOOPBACK) \ : (BM3803_REG.uart_ctrl1 &= ~MSK_UART_LOOPBACK) \ - ) + ) #define uart1_enable() (BM3803_REG.uart_ctrl1 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) #define uart1_disable() (BM3803_REG.uart_ctrl1 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) @@ -161,12 +161,12 @@ #define uart2_flow_ctrl_config(uart_flow) ( uart_flow == ON \ ? (BM3803_REG.uart_ctrl2 |= MSK_UART_ENABLE_FLOW) \ : (BM3803_REG.uart_ctrl2 &= ~MSK_UART_ENABLE_FLOW) \ - ) + ) #define uart2_loopback_config(uart_loopb) ( uart_loopb == ON \ ? (BM3803_REG.uart_ctrl2 |= MSK_UART_LOOPBACK) \ : (BM3803_REG.uart_ctrl2 &= ~MSK_UART_LOOPBACK) \ - ) + ) #define uart2_enable() (BM3803_REG.uart_ctrl2 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) #define uart2_disable() (BM3803_REG.uart_ctrl2 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) @@ -189,12 +189,12 @@ #define uart3_flow_ctrl_config(uart_flow) ( uart_flow == ON \ ? (BM3803_REG.uart_ctrl3 |= MSK_UART_ENABLE_FLOW) \ : (BM3803_REG.uart_ctrl3 &= ~MSK_UART_ENABLE_FLOW) \ - ) + ) #define uart3_loopback_config(uart_loopb) ( uart_loopb == ON \ ? (BM3803_REG.uart_ctrl3 |= MSK_UART_LOOPBACK) \ : (BM3803_REG.uart_ctrl3 &= ~MSK_UART_LOOPBACK) \ - ) + ) #define uart3_enable() (BM3803_REG.uart_ctrl3 |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) #define uart3_disable() (BM3803_REG.uart_ctrl3 &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) diff --git a/arch/sparc/src/s698pm/s698pm-uart.h b/arch/sparc/src/s698pm/s698pm-uart.h index 29a181a77d..3ba70a2da3 100644 --- a/arch/sparc/src/s698pm/s698pm-uart.h +++ b/arch/sparc/src/s698pm/s698pm-uart.h @@ -144,17 +144,17 @@ (reg &= ~(MSK_UART_ENABLE_RXIT | MSK_UART_ENABLE_TXIT)) \ ) \ ) \ - ) + ) #define uart_flow_ctrl_config(reg, uart_flow) ((uart_flow == ON) ? \ (reg |= MSK_UART_ENABLE_FLOW) : \ (reg &= ~MSK_UART_ENABLE_FLOW) \ - ) + ) #define uart_loopback_config(reg, uart_loopb) ((uart_loopb == ON) ? \ (reg |= MSK_UART_LOOPBACK) : \ (reg &= ~MSK_UART_LOOPBACK) \ - ) + ) #define uart_enable(reg) (reg |= (MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) #define uart_disable(reg) (reg &= ~(MSK_UART_ENABLE_RX | MSK_UART_ENABLE_TX)) diff --git a/arch/sparc/src/s698pm/s698pm_exceptions.S b/arch/sparc/src/s698pm/s698pm_exceptions.S index fe0eca4f2e..acc30c3335 100644 --- a/arch/sparc/src/s698pm/s698pm_exceptions.S +++ b/arch/sparc/src/s698pm/s698pm_exceptions.S @@ -242,7 +242,7 @@ fix_pil: cmp %l4, %g0 be do_irq nop - add %l4, 240, %l3 ! l3 = extended vector number + add %l4, 240, %l3 ! l3 = extended vector number do_irq: ! o1 = 2nd arg = address of the ISF ! WAS LOADED WHEN ISF WAS SAVED!!! diff --git a/arch/sparc/src/sparc_v8/sparc_v8_syscall.S b/arch/sparc/src/sparc_v8/sparc_v8_syscall.S index c1a0880a86..d80007c276 100644 --- a/arch/sparc/src/sparc_v8/sparc_v8_syscall.S +++ b/arch/sparc/src/sparc_v8/sparc_v8_syscall.S @@ -164,9 +164,9 @@ sys_call5: /* %o0 holds the syscall number, arguments in %o1, %o2, %o3, %o4 and /* Issue the ECALL opcode to perform a SW interrupt to the OS */ ta 8; ! syscall 8 - nop; - nop; - nop; + nop; + nop; + nop; jmp %o7 + 8 nop diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S index ccb70e22d5..e0ef5a213e 100644 --- a/arch/xtensa/src/common/xtensa_panic.S +++ b/arch/xtensa/src/common/xtensa_panic.S @@ -132,7 +132,7 @@ _xtensa_panic: ps_setup XCHAL_EXCM_LEVEL a0 - /* Call C panic handler: + /* Call C panic handler: * Arg1 = Exception code. * Arg2 = Start of the register save area. */ diff --git a/arch/xtensa/src/esp32/esp32_wifi_utils.c b/arch/xtensa/src/esp32/esp32_wifi_utils.c index a081c0a7b2..7f10e1c6fe 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_utils.c +++ b/arch/xtensa/src/esp32/esp32_wifi_utils.c @@ -46,7 +46,7 @@ #define ESP_IW_EVENT_SIZE(field) \ (offsetof(struct iw_event, u) + sizeof(((union iwreq_data *)0)->field)) -#ifdef CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE +#ifdef CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE # define WIFI_SCAN_RESULT_SIZE CONFIG_ESP32_WIFI_SCAN_RESULT_SIZE #else # define WIFI_SCAN_RESULT_SIZE (4096) diff --git a/arch/xtensa/src/esp32s2/esp32s2_freerun.c b/arch/xtensa/src/esp32s2/esp32s2_freerun.c index 148e796f36..5eab529e0d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_freerun.c +++ b/arch/xtensa/src/esp32s2/esp32s2_freerun.c @@ -46,7 +46,7 @@ ****************************************************************************/ #define MAX_TIMERS 4 -#define MAX_US_RESOLUTION 819 /* MAX_US = (PREmax * USEC_PER_SEC) / CLKmin */ +#define MAX_US_RESOLUTION 819 /* MAX_US = (PREmax * USEC_PER_SEC) / CLKmin */ #define TIMER_WIDTH 64 /**************************************************************************** diff --git a/arch/z80/src/ez80/Toolchain.defs b/arch/z80/src/ez80/Toolchain.defs index 920460f3a7..0d0a98866b 100644 --- a/arch/z80/src/ez80/Toolchain.defs +++ b/arch/z80/src/ez80/Toolchain.defs @@ -52,7 +52,7 @@ ARCHSTDINCLUDES = ARCHCPUFLAGS = -Dinterrupt="__attribute__((__interrupt__))" -ffreestanding ARCHCPUFLAGS += -Wa,-march=ez80 -ARCHLIST = +ARCHLIST = ARCHWARNINGS = -Wall -Wextra -Wno-incompatible-library-redeclaration ARCHWARNINGS += -Wno-main-return-type -Wno-unused-parameter ARCHWARNINGS += -Wno-invalid-noreturn -Wimplicit-int-conversion diff --git a/boards/arm/gd32f4/gd32f450zk-eval/include/board.h b/boards/arm/gd32f4/gd32f450zk-eval/include/board.h index 169395f65f..508d047d18 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/include/board.h +++ b/boards/arm/gd32f4/gd32f450zk-eval/include/board.h @@ -65,7 +65,7 @@ #ifndef CONFIG_GD32F4_BOARD_HXTAL_VALUE # define GD32_BOARD_HXTAL 25000000ul -#else +#else # define GD32_BOARD_HXTAL CONFIG_GD32F4_BOARD_HXTAL_VALUE #endif @@ -270,7 +270,7 @@ typedef enum # define DMA_CHANNEL_USART0_RX DMA_REQ_USART0_RX_1 #endif -#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA) +#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA) # define USART_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) #endif @@ -319,12 +319,12 @@ typedef enum # define GPIO_SPI0_SCK_PIN ((GPIO_SPI0_SCK_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) #endif -#ifdef CONFIG_GD32F4_SPI0_DMA +#ifdef CONFIG_GD32F4_SPI0_DMA # define DMA_CHANNEL_SPI0_TX DMA_REQ_SPI0_TX_1 # define DMA_CHANNEL_SPI0_RX DMA_REQ_SPI0_RX_1 #endif -#ifdef CONFIG_GD32F4_SPI_DMA +#ifdef CONFIG_GD32F4_SPI_DMA # define SPI_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) #endif diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c index 0b09118296..5bbf1daad9 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c @@ -69,7 +69,7 @@ * Private Functions ****************************************************************************/ -#if defined (CONFIG_IMXRT_USDHC) && (CONFIG_TEENSY_41) +#if defined (CONFIG_IMXRT_USDHC) && (CONFIG_TEENSY_41) static int nsh_sdmmc_initialize(void) { struct sdio_dev_s *sdmmc; diff --git a/boards/arm/phy62xx/phy6222/scripts/flash.ld b/boards/arm/phy62xx/phy6222/scripts/flash.ld index 4e25dcde3e..44cfa14721 100644 --- a/boards/arm/phy62xx/phy6222/scripts/flash.ld +++ b/boards/arm/phy62xx/phy6222/scripts/flash.ld @@ -37,17 +37,16 @@ SECTIONS } > flash __exidx_end = ABSOLUTE(.); - ._sjtblsstore : { _sjtblss = ABSOLUTE(.); - } > flash + } > flash .jumptbls : { _sjtbls = ABSOLUTE(.); *jump_table*(.jumptbls) _ejtbls = ABSOLUTE(.); } > jumptbl AT >flash - + .gcfgtbls : { _sgtbls = ABSOLUTE(.); *jump_table*(.gcfgtbls) @@ -56,7 +55,7 @@ SECTIONS ._eronlystore : { _eronly = ABSOLUTE(.); - } > flash + } > flash .data : { _sdata = ABSOLUTE(.); @@ -87,7 +86,6 @@ SECTIONS //*libarch.a:phy62xx_ble_patch.o(.text.ll_processBasicIRQ_ScanTRX0) //*libarch.a:phy62xx_ble_patch.o(.text.ll_processBasicIRQ_SRX0) //*libarch.a:phy62xx_ble_patch.o(.text.ll_hw_read_rfifo1) - *libphy6222_rf.a:patch.o(.text.ll_hw_go1) *libphy6222_rf.a:patch.o(.text.TIM1_IRQHandler1) @@ -110,7 +108,6 @@ SECTIONS *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_ScanTRX0) *libphy6222_rf.a:patch.o(.text.ll_processBasicIRQ_SRX0) *libphy6222_rf.a:patch.o(.text.ll_hw_read_rfifo1) - *libphy6222_rf.a:patch.o(.text.LL_set_default_conn_params1) *libphy6222_rf.a:patch.o(.text.llConnTerminate1) *libphy6222_rf.a:patch.o(.text.config_RTC1) @@ -125,17 +122,17 @@ SECTIONS *libphy6222_rf.a:patch.o(.text.llSetupSecAdvEvt1) *libphy6222_rf.a:patch.o(.text.ll_scheduler2) *libphy6222_rf.a:patch.o(.text.llSetupNextSlaveEvent1) - - *libapps.a:flash.c.*.o(.text .text.*) - *libapps.a:*.o(.text.drv_disable_irq1) - *libapps.a:*.o(.text.drv_enable_irq1) + + *libapps.a:flash.c.*.o(.text .text.*) + *libapps.a:*.o(.text.drv_disable_irq1) + *libapps.a:*.o(.text.drv_enable_irq1) *rf_phy_driver.o(.text.rf_phy_get_pktFoot) *rf_phy_driver.o(.text.rf_phy_change_cfg0 ) *libphy6222_host.a:l2cap_util.o(.text.L2CAP_Fragment_SendDataPkt) *libphy6222_host.a:l2cap_util.o(.text.l2capSegmentBuffToLinkLayer) *libphy6222_host.a:l2cap_util.o(.text.l2capPocessFragmentTxData) - + *libarch.a:phy62xx_ble_hcitl.o(.text.phy62xx_ble_init) *libarch.a:phy62xx_ble_hcitl.o(.text.HCI_ProcessEvent1) *libarch.a:up_idle.o(.text .text.*) @@ -149,7 +146,6 @@ SECTIONS *libarch.a:arm_doirq.o(.text.arm_doirq ) *libarch.a:phy62xx_hardfault.o(.text.arm_hardfault ) *libsched.a:irq_dispatch.o(.text.irq_dispatch ) - *libsched.a:clock_initialize.o(.text.clock_timer) *libsched.a:sched_processtimer.o(.text.nxsched_process_timer) *libsched.a:sem_wait.o(.text .text.*) @@ -157,28 +153,27 @@ SECTIONS *libsched.a:sched_yield.o(.text .text.*) *libsched.a:sched_lock.o(.text .text.*) *libsched.a:sched_unlock.o(.text .text.*) - *libdrivers.a:uart_bth4.o(.text.uart_bth4_pollnotify) *libdrivers.a:uart_bth4.o(.text.uart_bth4_post) *libdrivers.a:uart_bth4.o(.text.uart_bth4_receive) - - *libarch.a:uart.o(.text .text.*) - + + *libarch.a:uart.o(.text .text.*) + *libmm.a:circbuf.o(.text .text.*) - - *libc.a:lib_libvsprintf.o(.text .text.*) - *libc.a:lib_printf.o(.text .text.*) - *libc.a:lib_vfprintf.o(.text .text.*) - *libc.a:lib_skipspace.o(.text .text.*) + + *libc.a:lib_libvsprintf.o(.text .text.*) + *libc.a:lib_printf.o(.text .text.*) + *libc.a:lib_vfprintf.o(.text .text.*) + *libc.a:lib_skipspace.o(.text .text.*) *libc.a:lib_sprintf.o(.text .text.*) *libc.a:lib_strlen.o(.text .text.*) *libc.a:lib_memcmp.o(.text .text.*) *libc.a:lib_memcpy.o(.text .text.*) *libc.a:lib_memset.o(.text .text.*) *libc.a:lib_memmove.o(.text .text.*) - - *libapps.a:zblue.o(.text.k_yield .text.k_sleep .text.z_tick_get) + + *libapps.a:zblue.o(.text.k_yield .text.k_sleep .text.z_tick_get) _etextram = ABSOLUTE(.); @@ -197,7 +192,7 @@ SECTIONS . = ALIGN(4); _ebss = ABSOLUTE(.); } > sram - + .common_text : { *(.text .text.*) *(.rodata .rodata.*) @@ -211,9 +206,8 @@ SECTIONS *(.gcc_except_table) *(.gnu.linkonce.r.*) _etext = ABSOLUTE(.); - } > flash - - + } > flash + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } diff --git a/boards/arm/rp2040/adafruit-feather-rp2040/README.txt b/boards/arm/rp2040/adafruit-feather-rp2040/README.txt index 21030c62d7..713a9ece2f 100644 --- a/boards/arm/rp2040/adafruit-feather-rp2040/README.txt +++ b/boards/arm/rp2040/adafruit-feather-rp2040/README.txt @@ -83,7 +83,7 @@ Defconfigs - nshsram Load NuttX binary to SRAM - + - smp Enable SMP mode. Both Core 0 and Core 1 are used by NuttX. @@ -95,8 +95,8 @@ Defconfigs VCC ----- 3V3 OUT (Pin 36) SDA ----- GP4 (I2C0 SDA) (Pin 6) SCL ----- GP5 (I2C0 SCL) (Pin 7) - -- lcd1602 + +- lcd1602 LCD 1602 Segment LCD Disaply (I2C) Connection: PCF8574 BackPack Raspberry Pi Pico @@ -119,7 +119,7 @@ Defconfigs * Card hot swapping is not supported. - st7735 - st7735 SPI LCD support + st7735 SPI LCD support Connection: st7735 Raspberry Pi Pico GND ----- GND (Pin 3 or 38 or ...) @@ -129,7 +129,7 @@ Defconfigs CS ----- GP13 (SPI1 CSn) (Pin 17) AO(D/C) ----- GP12 (SPI1 RX) (Pin 16) BL ----- GP11 (Pin 15) - RESET ----- GP10 (Pin 14) + RESET ----- GP10 (Pin 14) - enc28j60 ENC28J60 SPI ethernet controller support diff --git a/boards/arm/rp2040/adafruit-feather-rp2040/src/rp2040_boardinitialize.c b/boards/arm/rp2040/adafruit-feather-rp2040/src/rp2040_boardinitialize.c index 2ec9864b66..19b738e471 100644 --- a/boards/arm/rp2040/adafruit-feather-rp2040/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/adafruit-feather-rp2040/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ @@ -81,7 +81,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/rp2040/adafruit-kb2040/README.txt b/boards/arm/rp2040/adafruit-kb2040/README.txt index 500aef9993..b7a2adf81e 100644 --- a/boards/arm/rp2040/adafruit-kb2040/README.txt +++ b/boards/arm/rp2040/adafruit-kb2040/README.txt @@ -82,7 +82,7 @@ Defconfigs - nshsram Load NuttX binary to SRAM - + - smp Enable SMP mode. Both Core 0 and Core 1 are used by NuttX. @@ -94,8 +94,8 @@ Defconfigs VCC ----- 3V3 OUT (Pin 36) SDA ----- GP4 (I2C0 SDA) (Pin 6) SCL ----- GP5 (I2C0 SCL) (Pin 7) - -- lcd1602 + +- lcd1602 LCD 1602 Segment LCD Disaply (I2C) Connection: PCF8574 BackPack Raspberry Pi Pico @@ -118,7 +118,7 @@ Defconfigs * Card hot swapping is not supported. - st7735 - st7735 SPI LCD support + st7735 SPI LCD support Connection: st7735 Raspberry Pi Pico GND ----- GND (Pin 3 or 38 or ...) @@ -128,7 +128,7 @@ Defconfigs CS ----- GP13 (SPI1 CSn) (Pin 17) AO(D/C) ----- GP12 (SPI1 RX) (Pin 16) BL ----- GP11 (Pin 15) - RESET ----- GP10 (Pin 14) + RESET ----- GP10 (Pin 14) - enc28j60 ENC28J60 SPI ethernet controller support diff --git a/boards/arm/rp2040/adafruit-kb2040/src/rp2040_boardinitialize.c b/boards/arm/rp2040/adafruit-kb2040/src/rp2040_boardinitialize.c index f11ea5cad1..c416e91ffc 100644 --- a/boards/arm/rp2040/adafruit-kb2040/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/adafruit-kb2040/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ } @@ -75,7 +75,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/rp2040/adafruit-qt-py-rp2040/README.txt b/boards/arm/rp2040/adafruit-qt-py-rp2040/README.txt index 383f0838c7..5dccebf539 100644 --- a/boards/arm/rp2040/adafruit-qt-py-rp2040/README.txt +++ b/boards/arm/rp2040/adafruit-qt-py-rp2040/README.txt @@ -2,7 +2,7 @@ README ====== This directory contains the port of NuttX to the Adafruit QT Py RP2040. -See https://learn.adafruit.com/adafruit-qt-py-2040 for information +See https://learn.adafruit.com/adafruit-qt-py-2040 for information about Adafruit QT Py RP2040. NuttX supports the following RP2040 capabilities: @@ -77,7 +77,7 @@ Defconfigs - nshsram Load NuttX binary to SRAM - + - smp Enable SMP mode. Both Core 0 and Core 1 are used by NuttX. diff --git a/boards/arm/rp2040/adafruit-qt-py-rp2040/src/rp2040_boardinitialize.c b/boards/arm/rp2040/adafruit-qt-py-rp2040/src/rp2040_boardinitialize.c index 4d3010f8f4..917e3124bd 100644 --- a/boards/arm/rp2040/adafruit-qt-py-rp2040/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/adafruit-qt-py-rp2040/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ } @@ -75,7 +75,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/rp2040/pimoroni-tiny2040/README.txt b/boards/arm/rp2040/pimoroni-tiny2040/README.txt index e86e43a7fb..91f05776c8 100644 --- a/boards/arm/rp2040/pimoroni-tiny2040/README.txt +++ b/boards/arm/rp2040/pimoroni-tiny2040/README.txt @@ -81,7 +81,7 @@ Defconfigs - nshsram Load NuttX binary to SRAM - + - smp Enable SMP mode. Both Core 0 and Core 1 are used by NuttX. diff --git a/boards/arm/rp2040/pimoroni-tiny2040/src/rp2040_boardinitialize.c b/boards/arm/rp2040/pimoroni-tiny2040/src/rp2040_boardinitialize.c index 05986e662f..c070364185 100644 --- a/boards/arm/rp2040/pimoroni-tiny2040/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/pimoroni-tiny2040/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ @@ -91,7 +91,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/rp2040/raspberrypi-pico-w/include/board.h b/boards/arm/rp2040/raspberrypi-pico-w/include/board.h index 83c516eb74..f7d3eb7957 100644 --- a/boards/arm/rp2040/raspberrypi-pico-w/include/board.h +++ b/boards/arm/rp2040/raspberrypi-pico-w/include/board.h @@ -62,7 +62,7 @@ /* GPIO definitions *********************************************************/ -#undef BOARD_GPIO_LED_PIN +#undef BOARD_GPIO_LED_PIN #define BOARD_NGPIOOUT 1 #define BOARD_NGPIOIN 1 #define BOARD_NGPIOINT 1 diff --git a/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs b/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs index e68161cc2d..d5ec27cfc5 100644 --- a/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs +++ b/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs @@ -63,11 +63,11 @@ $(FIRMWARE_SRC): $(FIRMWARE): $(FIRMWARE_SRC) $(call CATFILE, $(FIRMWARE), $(FIRMWARE_SRC)) -src$(DELIM)rp2040_firmware.c: $(FIRMWARE) +src$(DELIM)rp2040_firmware.c: $(FIRMWARE) -#depend: $(FIRMWARE) +#depend: $(FIRMWARE) -distclean:: +distclean:: $(call DELFILE, src$(DELIM)cyw43439.firmware.image) endif diff --git a/boards/arm/rp2040/raspberrypi-pico-w/src/rp2040_boardinitialize.c b/boards/arm/rp2040/raspberrypi-pico-w/src/rp2040_boardinitialize.c index b9b582589d..dee2a31d29 100644 --- a/boards/arm/rp2040/raspberrypi-pico-w/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/raspberrypi-pico-w/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ } @@ -75,7 +75,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/rp2040/raspberrypi-pico/README.txt b/boards/arm/rp2040/raspberrypi-pico/README.txt index 1e3177f99f..735b561040 100644 --- a/boards/arm/rp2040/raspberrypi-pico/README.txt +++ b/boards/arm/rp2040/raspberrypi-pico/README.txt @@ -83,7 +83,7 @@ Defconfigs - nshsram Load NuttX binary to SRAM - + - smp Enable SMP mode. Both Core 0 and Core 1 are used by NuttX. @@ -95,8 +95,8 @@ Defconfigs VCC ----- 3V3 OUT (Pin 36) SDA ----- GP4 (I2C0 SDA) (Pin 6) SCL ----- GP5 (I2C0 SCL) (Pin 7) - -- lcd1602 + +- lcd1602 LCD 1602 Segment LCD Disaply (I2C) Connection: PCF8574 BackPack Raspberry Pi Pico @@ -119,7 +119,7 @@ Defconfigs * Card hot swapping is not supported. - st7735 - st7735 SPI LCD support + st7735 SPI LCD support Connection: st7735 Raspberry Pi Pico GND ----- GND (Pin 3 or 38 or ...) @@ -129,7 +129,7 @@ Defconfigs CS ----- GP13 (SPI1 CSn) (Pin 17) AO(D/C) ----- GP12 (SPI1 RX) (Pin 16) BL ----- GP11 (Pin 15) - RESET ----- GP10 (Pin 14) + RESET ----- GP10 (Pin 14) - enc28j60 ENC28J60 SPI ethernet controller support diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_boardinitialize.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_boardinitialize.c index c35e85fd13..ac33c7d4e6 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_boardinitialize.c +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_boardinitialize.c @@ -59,7 +59,7 @@ void rp2040_boardearlyinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_earlyinitialize(); - #endif + #endif /* --- Place any board specific early initialization here --- */ @@ -81,7 +81,7 @@ void rp2040_boardinitialize(void) { #ifdef CONFIG_ARCH_BOARD_COMMON rp2040_common_initialize(); - #endif + #endif /* --- Place any board specific initialization here --- */ } diff --git a/boards/arm/s32k1xx/rddrone-bms772/README.txt b/boards/arm/s32k1xx/rddrone-bms772/README.txt index 47b872ad04..bb1ade0255 100644 --- a/boards/arm/s32k1xx/rddrone-bms772/README.txt +++ b/boards/arm/s32k1xx/rddrone-bms772/README.txt @@ -9,7 +9,7 @@ available. It contains additional drivers and example software to use most features of the battery management system. This application is currently published in a separate repository, but -(parts) may eventually be upstreamed to Apache NuttX: +(parts) may eventually be upstreamed to Apache NuttX: https://github.com/NXPHoverGames/RDDRONE-BMS772 @@ -87,7 +87,7 @@ Thread-Aware Debugging with Eclipse Thread-aware debugging is possible with openocd-nuttx ( https://github.com/sony/openocd-nuttx ) and was tested together with the - Eclipse-based S32 Design Studio for Arm: + Eclipse-based S32 Design Studio for Arm: https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1. diff --git a/boards/arm/s32k1xx/rddrone-bms772/scripts/rddrone-bms772.jlink b/boards/arm/s32k1xx/rddrone-bms772/scripts/rddrone-bms772.jlink index 6d94e8cc85..d07fb2a214 100644 --- a/boards/arm/s32k1xx/rddrone-bms772/scripts/rddrone-bms772.jlink +++ b/boards/arm/s32k1xx/rddrone-bms772/scripts/rddrone-bms772.jlink @@ -4,7 +4,7 @@ // J-Link Command File for connecting to RDDRONE-BMS772 with a J-Link debugger and flashing a compiled NuttX binary. // // The script can be executed by entering the command: JLinkExe -CommandFile rddrone-bms772.jlink -// Note that the current working directory needs to be /boards/arm/s32k1xx/rddrone-bms772/scripts/ +// Note that the current working directory needs to be /boards/arm/s32k1xx/rddrone-bms772/scripts/ // usb diff --git a/boards/arm/s32k1xx/s32k144evb/README.txt b/boards/arm/s32k1xx/s32k144evb/README.txt index e0fdd29ad3..918e977f72 100644 --- a/boards/arm/s32k1xx/s32k144evb/README.txt +++ b/boards/arm/s32k1xx/s32k144evb/README.txt @@ -102,7 +102,7 @@ Thread-Aware Debugging with Eclipse Thread-aware debugging is possible with openocd-nuttx ( https://github.com/sony/openocd-nuttx ) and was tested together with the - Eclipse-based S32 Design Studio for Arm: + Eclipse-based S32 Design Studio for Arm: https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1. diff --git a/boards/arm/s32k1xx/s32k146evb/README.txt b/boards/arm/s32k1xx/s32k146evb/README.txt index bdfadd51a8..64edeadf22 100644 --- a/boards/arm/s32k1xx/s32k146evb/README.txt +++ b/boards/arm/s32k1xx/s32k146evb/README.txt @@ -32,7 +32,7 @@ Status for recovery from this condition at the NXP Community Forums, but none of those options are working for me: https://community.nxp.com/thread/505593 - + Given the success running from SRAM and the success of the same fixes on the S32K118, I believe that the NSH configuration should now run out of FLASH. Unfortunately, I cannot demonstrate that. @@ -43,7 +43,7 @@ Status configuration options, with a proven default state. 2019-11-07: A s32k146.cfg configuration file (for OpenOCD) was added to - the scripts/ folder. + the scripts/ folder. 2020-06-15: Added FlexCAN driver with SocketCAN support to the S32K1XX arch. Should work also on the S32K146EVB board, but remains untested. @@ -132,7 +132,7 @@ Thread-Aware Debugging with Eclipse Thread-aware debugging is possible with openocd-nuttx ( https://github.com/sony/openocd-nuttx ) and was tested together with the - Eclipse-based S32 Design Studio for Arm: + Eclipse-based S32 Design Studio for Arm: https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1. diff --git a/boards/arm/s32k1xx/ucans32k146/README.txt b/boards/arm/s32k1xx/ucans32k146/README.txt index 7477d0964a..345bf240a5 100644 --- a/boards/arm/s32k1xx/ucans32k146/README.txt +++ b/boards/arm/s32k1xx/ucans32k146/README.txt @@ -91,7 +91,7 @@ Thread-Aware Debugging with Eclipse Thread-aware debugging is possible with openocd-nuttx ( https://github.com/sony/openocd-nuttx ) and was tested together with the - Eclipse-based S32 Design Studio for Arm: + Eclipse-based S32 Design Studio for Arm: https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-arm:S32DS-ARM NOTE: This method was last tested with NuttX 8.2 and S32DS for Arm 2018.R1. diff --git a/boards/arm/s32k3xx/mr-canhubk3/scripts/memory.ld b/boards/arm/s32k3xx/mr-canhubk3/scripts/memory.ld index 82bd6a0a05..fd3cae61a5 100644 --- a/boards/arm/s32k3xx/mr-canhubk3/scripts/memory.ld +++ b/boards/arm/s32k3xx/mr-canhubk3/scripts/memory.ld @@ -33,7 +33,7 @@ * ****************************************************************************/ -/* +/* * * 0x00400000 - 0x007fffff 4194304 Program Flash (last 64K sBAF) * 0x10000000 - 0x1003ffff 262144 Data Flash (last 32K HSE_NVM) @@ -54,7 +54,7 @@ MEMORY /* 4096KB FLASH*/ BOOT_HEADER (R) : ORIGIN = 0x00400000, LENGTH = 0x00001000 /* 0x00400000 - 0x00400fff */ - flash (rx) : ORIGIN = 0x00401000, LENGTH = 0x003cffff + flash (rx) : ORIGIN = 0x00401000, LENGTH = 0x003cffff kflash (rx) : ORIGIN = 0x00401000, LENGTH = 1024K uflash (rx) : ORIGIN = 0x00401000+1024K, LENGTH = 0x003cffff-1024K diff --git a/boards/arm/s32k3xx/s32k344evb/README.txt b/boards/arm/s32k3xx/s32k344evb/README.txt index 6dc6f5679d..a873687a6d 100644 --- a/boards/arm/s32k3xx/s32k344evb/README.txt +++ b/boards/arm/s32k3xx/s32k344evb/README.txt @@ -42,7 +42,7 @@ LEDs and Buttons RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12) GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13) BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0) - + RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1) GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6) BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8) diff --git a/boards/arm/sama5/jupiter-nano/README.md b/boards/arm/sama5/jupiter-nano/README.md index 9182d23805..d0b2f50f37 100644 --- a/boards/arm/sama5/jupiter-nano/README.md +++ b/boards/arm/sama5/jupiter-nano/README.md @@ -32,19 +32,19 @@ Segger J-Link. You may have to adapt them for other JTAG debuggers. There is a mini-JTAG connector on the board, labeled J4 JTAG. You will need a mini-JTAG adapter board and cable. -1. Start the GDB server -2. Start GDB -3. Use the 'target remote localhost:xxxx' command to attach to the GDB - server -4. Do 'mon reset' then 'mon go' to start the internal boot loader (maybe - U-Boot). -5. Let the boot loader run until it completes SDRAM initialization, then - do 'mon halt'. -6. Now you have SDRAM initialized and you use 'load nuttx' to load the - ELF file into SDRAM. -7. Use 'file nuttx' to load symbols -8. Set the PC to the NuttX entry point 'mon pc 0x20008E20' and start - nuttx using 'mon go'. +1. Start the GDB server +2. Start GDB +3. Use the 'target remote localhost:xxxx' command to attach to the GDB + server +4. Do 'mon reset' then 'mon go' to start the internal boot loader (maybe + U-Boot). +5. Let the boot loader run until it completes SDRAM initialization, then + do 'mon halt'. +6. Now you have SDRAM initialized and you use 'load nuttx' to load the + ELF file into SDRAM. +7. Use 'file nuttx' to load symbols +8. Set the PC to the NuttX entry point 'mon pc 0x20008E20' and start + nuttx using 'mon go'. ### Loading Code into SRAM from SD Card @@ -168,9 +168,9 @@ U-Boot, and then from the U-Boot prompt do the following: Two buttons, labeled S1 RESET, and S2 WAKEUP are available on the Jupiter Nano. Both are connected to the Power Management Integrated Circuit (PMIC) and are -not available to user programs. Pressing RESET will reset the SAMA5D27C-LD1G and the +not available to user programs. Pressing RESET will reset the SAMA5D27C-LD1G and the ACT8945A PMIC chips. WAKEUP is used to wake up the board if it has been put -into a sleep state. +into a sleep state. You can add your own buttons, support for pollable buttons is enabled with: @@ -224,7 +224,7 @@ is, apparently, running normally. If LED is flashing at approximately ## Serial Console The default serial console is UART1. UART1 is connected to the MCP2200 -USB-UART converter, and is available as a USB serial connection on the +USB-UART converter, and is available as a USB serial connection on the micro-USB connector labeled CONSOLE. This is the default serial console. ------------------------ ------------- @@ -490,7 +490,7 @@ Board Selection -> CPU Frequency ### Configuration Sub-directories Summary: Some of the descriptions below are long and wordy. Here is the -concise summary of the available Jupiter Nano configurations: +concise summary of the available Jupiter Nano configurations: - nsh: This is a basic NuttShell (NSH) configuration. @@ -630,29 +630,29 @@ concise summary of the available Jupiter Nano configurations: This is a configuration based on the NuttShell (NSH). Internet networking and the SDMMC peripheral is enabled. NuttX can read and write to a VFAT - filesystem on the SD Card. + filesystem on the SD Card. NuttX will mount the SD Card at `/mnt/mmcsd1`. ## Networking - Jupiter Nano has support for Ethernet over USB using CDC-ECM protocol. (All the - SAMA5D27C boards do, actually.) The Jupiter Nano will appear as an Ethernet USB - Gadget on the Linux side. This is a high performance link and can transfer 30MB/s + Jupiter Nano has support for Ethernet over USB using CDC-ECM protocol. (All the + SAMA5D27C boards do, actually.) The Jupiter Nano will appear as an Ethernet USB + Gadget on the Linux side. This is a high performance link and can transfer 30MB/s of data to or from a host computer. - The netnsh sdmmcnsh, or sdmmc-nsh-net-resolvconf configurations will set up the - Ethernet over USB interface to be `10.0.0.2`, and set up default routing via + The netnsh sdmmcnsh, or sdmmc-nsh-net-resolvconf configurations will set up the + Ethernet over USB interface to be `10.0.0.2`, and set up default routing via `10.0.0.1`. The sdmmc-nsh-net-resolvconf also sets up the /etc/resolv.conf file and configures NuttX to support it, which enables DNS resolution using Google's open DNS servers. - The tools/netusb.sh script can set up a Linux computer with IP tables NAT rules - and proper routes to allow the NuttX computer to access the Internet, setting - the Linux side of the Ethernet over USB link to have the IP address of + The tools/netusb.sh script can set up a Linux computer with IP tables NAT rules + and proper routes to allow the NuttX computer to access the Internet, setting + the Linux side of the Ethernet over USB link to have the IP address of `10.0.0.1`. - In the commands below, replace the interface identifier `wlp0s20f3` with the + In the commands below, replace the interface identifier `wlp0s20f3` with the interface that you use to access the Internet. $./tools/netusb.sh show @@ -665,11 +665,11 @@ concise summary of the available Jupiter Nano configurations: TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 $ sudo ./tools/netusb.sh wlp0s20f3 enx020000112233 on - default via 192.168.1.1 dev wlp0s20f3 proto dhcp metric 600 - 169.254.0.0/16 dev br-cc496150b4da scope link metric 1000 linkdown - 172.17.0.0/16 dev docker0 proto kernel scope link src 172.17.0.1 linkdown - 172.18.0.0/16 dev br-cc496150b4da proto kernel scope link src 172.18.0.1 linkdown - 192.168.1.0/24 dev wlp0s20f3 proto kernel scope link src 192.168.1.209 metric 600 + default via 192.168.1.1 dev wlp0s20f3 proto dhcp metric 600 + 169.254.0.0/16 dev br-cc496150b4da scope link metric 1000 linkdown + 172.17.0.0/16 dev docker0 proto kernel scope link src 172.17.0.1 linkdown + 172.18.0.0/16 dev br-cc496150b4da proto kernel scope link src 172.18.0.1 linkdown + 192.168.1.0/24 dev wlp0s20f3 proto kernel scope link src 192.168.1.209 metric 600 enx020000112233: flags=4163 mtu 1500 ether 02:00:00:11:22:33 txqueuelen 1000 (Ethernet) @@ -679,15 +679,15 @@ concise summary of the available Jupiter Nano configurations: TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 - default via 192.168.1.1 dev wlp0s20f3 proto dhcp metric 600 - 10.0.0.0/24 dev enx020000112233 scope link src 10.0.0.1 - 10.0.0.0/24 dev enx020000112233 proto kernel scope link src 10.0.0.1 metric 100 - 10.0.0.0/8 dev enx020000112233 proto kernel scope link src 10.0.0.1 - 10.0.0.2 dev enx020000112233 scope link src 10.0.0.1 - 169.254.0.0/16 dev br-cc496150b4da scope link metric 1000 linkdown - 172.17.0.0/16 dev docker0 proto kernel scope link src 172.17.0.1 linkdown - 172.18.0.0/16 dev br-cc496150b4da proto kernel scope link src 172.18.0.1 linkdown - 192.168.1.0/24 dev wlp0s20f3 proto kernel scope link src 192.168.1.209 metric 600 + default via 192.168.1.1 dev wlp0s20f3 proto dhcp metric 600 + 10.0.0.0/24 dev enx020000112233 scope link src 10.0.0.1 + 10.0.0.0/24 dev enx020000112233 proto kernel scope link src 10.0.0.1 metric 100 + 10.0.0.0/8 dev enx020000112233 proto kernel scope link src 10.0.0.1 + 10.0.0.2 dev enx020000112233 scope link src 10.0.0.1 + 169.254.0.0/16 dev br-cc496150b4da scope link metric 1000 linkdown + 172.17.0.0/16 dev docker0 proto kernel scope link src 172.17.0.1 linkdown + 172.18.0.0/16 dev br-cc496150b4da proto kernel scope link src 172.18.0.1 linkdown + 192.168.1.0/24 dev wlp0s20f3 proto kernel scope link src 192.168.1.209 metric 600 PING 10.0.0.2 (10.0.0.2) 56(84) bytes of data. 64 bytes from 10.0.0.2: icmp_seq=1 ttl=64 time=0.187 ms diff --git a/boards/arm/sama5/sama5d2-xult/README.txt b/boards/arm/sama5/sama5d2-xult/README.txt index 8606869d8e..7feff18455 100644 --- a/boards/arm/sama5/sama5d2-xult/README.txt +++ b/boards/arm/sama5/sama5d2-xult/README.txt @@ -881,7 +881,7 @@ Configurations from the SD card: U-Boot> fatload mmc 0 0x20008000 nuttx.bin - U-Boot> go 0x20008E20 + U-Boot> go 0x20008E20 6. Board LEDs and buttons are supported as described under "Buttons and LEDs". The interrupt button test is also enabled as an NSH built-in diff --git a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu index c13d11a744..82f18ee19e 100644 --- a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu +++ b/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu @@ -67,7 +67,7 @@ SECTIONS *(.tdata .tdata.* .gnu.linkonce.td.*); _etdata = ABSOLUTE(.); } > flash - + .tbss : { _stbss = ABSOLUTE(.); *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32/shenzhou/scripts/ld.script.dfu index 61c9ae6235..fca7e5d10f 100644 --- a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu +++ b/boards/arm/stm32/shenzhou/scripts/ld.script.dfu @@ -72,7 +72,7 @@ SECTIONS *(.tdata .tdata.* .gnu.linkonce.td.*); _etdata = ABSOLUTE(.); } > flash - + .tbss : { _stbss = ABSOLUTE(.); *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu index 62da453566..d3e8075233 100644 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu +++ b/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu @@ -72,7 +72,7 @@ SECTIONS *(.tdata .tdata.* .gnu.linkonce.td.*); _etdata = ABSOLUTE(.); } > flash - + .tbss : { _stbss = ABSOLUTE(.); *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu index 5c72c8fe73..c8b9529484 100644 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu +++ b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu @@ -72,7 +72,7 @@ SECTIONS *(.tdata .tdata.* .gnu.linkonce.td.*); _etdata = ABSOLUTE(.); } > flash - + .tbss : { _stbss = ABSOLUTE(.); *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c index e78f90a8db..aeecb27310 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_bringup.c @@ -197,7 +197,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32F7_TIM4_QE sprintf(buf, "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) diff --git a/boards/arm/stm32h7/nucleo-h743zi/README.txt b/boards/arm/stm32h7/nucleo-h743zi/README.txt index 240103c0bd..726e7ad5cf 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/README.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/README.txt @@ -160,7 +160,6 @@ Configurations This configuration provides a basic NuttShell configuration (NSH) for the Nucleo-H743ZI. The default console is the VCOM on USART3. - MCUboot safe bootloader implementation -------------------------------------- diff --git a/boards/arm/stm32h7/nucleo-h743zi2/README.txt b/boards/arm/stm32h7/nucleo-h743zi2/README.txt index e491c4a69d..92d890773d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/README.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/README.txt @@ -108,7 +108,7 @@ Configurations Testing: - OS Test with FPU support - Filesystem testing - + USB Host: - USB Hub support - Mass Storage Device @@ -121,14 +121,14 @@ NuttX 10.0.1 3ab35e48ff-dirty Mar 28 2021 15:35:29 arm nucleo-h743zi2 nsh> ? help usage: help [-v] [] - . cd dmesg hexdump mkrd reboot telnetd xd - [ cp echo ifconfig mh rm time - ? cmp env irqinfo mount rmdir true - addroute dirname exec kill mv route uname - arp date exit ls mw set umount - basename dd false mb nslookup sleep unset - break delroute free mkdir ps source usleep - cat df help mkfatfs pwd test wget + . cd dmesg hexdump mkrd reboot telnetd xd + [ cp echo ifconfig mh rm time + ? cmp env irqinfo mount rmdir true + addroute dirname exec kill mv route uname + arp date exit ls mw set umount + basename dd false mb nslookup sleep unset + break delroute free mkdir ps source usleep + cat df help mkfatfs pwd test wget Builtin Apps: fstest getprime nsh ostest ping renew sh @@ -202,7 +202,7 @@ PING 172.217.14.196 56 bytes of data 56 bytes from 172.217.14.196: icmp_seq=8 time=0 ms 56 bytes from 172.217.14.196: icmp_seq=9 time=0 ms 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms -nsh> +nsh> nsh> ls /dev /dev: console @@ -236,7 +236,7 @@ nsh> ls /mnt/sda afile nsh> cat /mnt/sda/afile This will stay on the USB drive -nsh> +nsh> ``` ``` @@ -257,5 +257,5 @@ nsh> ps 6 100 RR Task --- Waiting Semaphore 00000000 002012 000648 32.2% 0.0% Telnet daemon 0x38005600 9 100 RR Kthread --- Waiting Semaphore 00000000 001004 000448 44.6% 0.0% telnet_io 10 100 RR Task --- Running 00000000 002028 001328 65.4% 0.0% Telnet session -nsh> +nsh> ``` \ No newline at end of file diff --git a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h index b2427d2610..268b603688 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h @@ -390,7 +390,7 @@ #define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2 /* PE11 - D5 */ #define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_3 /* PE10 - D40 */ -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_2 /* PE9 */ +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_2 /* PE9 */ #define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_2 /* PE11 */ /* TIM3 */ @@ -398,12 +398,12 @@ #define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_2 /* PB4 */ #define GPIO_TIM3_CH2OUT GPIO_TIM3_CH2OUT_2 /* PB5 */ -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 /* PA4 */ +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 /* PA4 */ #define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_2 /* PB5 */ /* TIM4 */ -#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_2 /* PD12 */ +#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_2 /* PD12 */ #define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_2 /* PD13 */ /* FDCAN1 */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/README.txt b/boards/arm/stm32l4/steval-stlcs01v1/README.txt index 2833f765f7..c4c89b3a0b 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/README.txt +++ b/boards/arm/stm32l4/steval-stlcs01v1/README.txt @@ -7,7 +7,7 @@ STM32L476JG MCU. The board features: - LSM6DSM, 6DoF inertial measurement unit (IMU), - LSM303AGR, 3D accelerometer and 3D magnetometer, - - LPS22HB, pressure sensor, + - LPS22HB, pressure sensor, - MP34DT05-A, omni-directional digital microphone - BlueNRG-MS, SPI based BLE Network Processor diff --git a/boards/arm/stm32l5/stm32l562e-dk/README.txt b/boards/arm/stm32l5/stm32l562e-dk/README.txt index eefa923380..d8743f3954 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/README.txt +++ b/boards/arm/stm32l5/stm32l562e-dk/README.txt @@ -39,7 +39,7 @@ LEDs include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS related events as follows when the LEDs are available: - SYMBOL Meaning RED GREEN + SYMBOL Meaning RED GREEN ------------------- ----------------------- --- ----- LED_STARTED NuttX has been started OFF OFF @@ -127,7 +127,7 @@ TrustedFirmware-M @@ -306,6 +306,9 @@ void jumper(struct arm_vector_table *vector) /* set the secure vector */ SCB->VTOR = (uint32_t)vector; - + + /* Stay in Non-Secure mode for BusFault, HardFault, and NMI exceptions */ + SCB->AIRCR = (SCB->AIRCR & 0x0000FFFF) | 0x05FA0000 | SCB_AIRCR_BFHFNMINS_Msk; + diff --git a/boards/arm/tiva/tm4c1294-launchpad/Kconfig b/boards/arm/tiva/tm4c1294-launchpad/Kconfig index 8d646582ed..27d881752a 100644 --- a/boards/arm/tiva/tm4c1294-launchpad/Kconfig +++ b/boards/arm/tiva/tm4c1294-launchpad/Kconfig @@ -79,35 +79,35 @@ config TM4C1294_LAUNCHPAD_JUMPERS_CAN ---help--- If set, NuttX will assume the jumpers JP4 and JP5 are set in CAN configuration. This means UART2 will be connected to the ICDI serial port. - + choice prompt "UART2 Rx pin selection" depends on TIVA_UART2 default TM4C1294_LAUNCHPAD_UART2_RX_A6 - + config TM4C1294_LAUNCHPAD_UART2_RX_A6 bool "Use A6 as UART Rx pin" depends on TIVA_UART2 && !TM4C1294_LAUNCHPAD_JUMPERS_CAN - + config TM4C1294_LAUNCHPAD_UART2_RX_D4 bool "Use D4 as UART Rx pin" depends on TIVA_UART2 - + endchoice # UART2 Rx pin selection choice prompt "UART2 Tx pin selection" default TM4C1294_LAUNCHPAD_UART2_TX_A7 depends on TIVA_UART2 - + config TM4C1294_LAUNCHPAD_UART2_TX_A7 bool "Use A7 as UART Tx pin" depends on TIVA_UART2 && !TM4C1294_LAUNCHPAD_JUMPERS_CAN - + config TM4C1294_LAUNCHPAD_UART2_TX_D5 bool "Use D5 as UART Tx pin" depends on TIVA_UART2 - + endchoice # UART2 Tx pin selection endif # ARCH_BOARD_TM4C1294_LAUNCHPAD diff --git a/boards/arm64/qemu/qemu-armv8a/README.txt b/boards/arm64/qemu/qemu-armv8a/README.txt index 38a2d337b7..7628ec3d54 100644 --- a/boards/arm64/qemu/qemu-armv8a/README.txt +++ b/boards/arm64/qemu/qemu-armv8a/README.txt @@ -189,7 +189,6 @@ The nuttx ELF image can be debugged with QEMU. $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic -machine virt,virtualization=on,gic-version=3 \ -net none -chardev stdio,id=con,mux=on -serial chardev:con -mon chardev=con,mode=readline \ -kernel ./nuttx -S -s - 3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2) @@ -220,9 +219,9 @@ The nuttx ELF image can be debugged with QEMU. (gdb) Note: - 1. it will make your debugging more easier in source level if you setting - CONFIG_DEBUG_FULLOPT=n. but there is a risk of stack overflow when the - option is disabled. Just enlarging your stack size will avoid the + 1. it will make your debugging more easier in source level if you setting + CONFIG_DEBUG_FULLOPT=n. but there is a risk of stack overflow when the + option is disabled. Just enlarging your stack size will avoid the issue (eg. enlarging CONFIG_DEFAULT_TASK_STACKSIZE) 2. TODO: ARMv8-A Supporting for tools/nuttx-gdbinit @@ -240,17 +239,17 @@ need to be considered: In many cases, the FPU trap is triggered by va_start() that copies the content of FP registers used for floating point argument passing into the va_list object in case there were actual float arguments from -the caller. But In practice this is almost never the case. +the caller. But In practice this is almost never the case. Seeing the save_count/restore_count at the g_cpu_fpu_ctx, which will be increase when saving/restoring FPU context. After running ostest, we can see the count with GDB: - + (gdb) p g_cpu_fpu_ctx $1 = {{fpu_owner = 0x0, idle_thread = 0x402b3110 , save_count = 1293, restore_count = 2226, switch_count = 4713, exe_depth_count = 0}} (gdb) - + adding -mgeneral-regs-only option will make compiler not use the FPU register, we can use the following patch to syslog: @@ -263,8 +262,8 @@ index c58fb45512..acac6febaa DEPPATH += --dep-path syslog VPATH += :syslog +syslog/lib_syslog.c_CFLAGS += -mgeneral-regs-only - - With the option to make NuttX and booting. After running ostest, see + + With the option to make NuttX and booting. After running ostest, see the count with GDB again: (gdb) p g_cpu_fpu_ctx @@ -276,7 +275,7 @@ $1 = {{fpu_owner = 0x0, idle_thread = 0x402b3110 , save_count = 141, add this compile option. Almost all of FPU accessing switch is argument passing at the syslog. I cannot commit the patch for NuttX mainline because it's very special case -since ostest is using syslog for lots of information printing. but this is +since ostest is using syslog for lots of information printing. but this is a clue for FPU performance analysis. va_list object is using for many C code to handle argument passing, but if it's not passing floating point argument indeed. Add the option to your code maybe increase FPU performance @@ -311,7 +310,7 @@ SMP Support for every CPU core ->up_cpu_start ->arm64_start_cpu(call PCSI to boot CPU) - ->waiting for every core to boot + ->waiting for every core to boot ->nx_bringup Secondary Core call sequence @@ -321,7 +320,7 @@ SMP Support ->Initialize GIC: Secondary core GICR ->Notify Primary core booting is Ready ->nx_idle_trampoline - + 2. interrupt SGI @@ -339,7 +338,7 @@ SPI should be enabled at every core. But for NuttX, it's design only for primary core to handle timer - interrupt and call nxsched_process_timer at timer tick mode. + interrupt and call nxsched_process_timer at timer tick mode. So we need only enable timer for primary core IMX6 use GPT which is a SPI rather than generic timer to handle diff --git a/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld b/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld index 71997bd461..bd58c25e7d 100644 --- a/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld +++ b/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld @@ -1,16 +1,16 @@ MEMORY -{ -/* RSK-RX65N-1MB */ +{ +/* RSK-RX65N-1MB */ /* RAM : ORIGIN = 0x0, LENGTH = 262144 ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576 OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 -*/ -/* RSK-RX65N-2MB | GR-ROSE */ +*/ +/* RSK-RX65N-2MB | GR-ROSE */ RAM : ORIGIN = 0x0, LENGTH = 262144 - RAMHI : ORIGIN = 0x800000, LENGTH = 393216 - ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 - OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 + RAMHI : ORIGIN = 0x800000, LENGTH = 393216 + ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 } SECTIONS { @@ -23,13 +23,13 @@ SECTIONS .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) { KEEP(*(.fvectors)) - } > ROM -/* RSK-RX65N-1MB */ - + } > ROM +/* RSK-RX65N-1MB */ + /* .text 0xFFF00000: AT(0xFFF00000) */ - -/* RSK-RX65N-2MB | GR-ROSE */ - .text 0xFFE00000: AT(0xFFE00000) + +/* RSK-RX65N-2MB | GR-ROSE */ + .text 0xFFE00000: AT(0xFFE00000) { *(.text) . = ALIGN(4); diff --git a/boards/risc-v/esp32c6/common/scripts/flat_memory.ld b/boards/risc-v/esp32c6/common/scripts/flat_memory.ld index 5aee550334..ee17a5d500 100644 --- a/boards/risc-v/esp32c6/common/scripts/flat_memory.ld +++ b/boards/risc-v/esp32c6/common/scripts/flat_memory.ld @@ -54,7 +54,7 @@ MEMORY { /* All these values assume the flash cache is on, and have the blocks it * uses subtracted from the length of the various regions. The 'data access - * port' dram/drom regions map to the same iram/irom regions but are + * port' dram/drom regions map to the same iram/irom regions but are * connected to the data port of the CPU and eg allow byte-wise access. */ diff --git a/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml b/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml index 05b4214a02..e35fb8e54b 100644 --- a/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml +++ b/boards/risc-v/mpfs/icicle/scripts/hss-nuttx.yml @@ -1,4 +1,4 @@ -# HSS Payload Generator +# HSS Payload Generator # First, we can optionally set a name for our image, otherwise one will be created dynamically set-name: 'PolarFire-SoC-HSS::nuttx' @@ -6,7 +6,7 @@ set-name: 'PolarFire-SoC-HSS::nuttx' # Next, we'll define the entry point addresses for each hart, as follows: hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'} -# +# payloads: nuttx.bin: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m} diff --git a/boards/risc-v/mpfs/icicle/scripts/kernel-space.ld b/boards/risc-v/mpfs/icicle/scripts/kernel-space.ld index c8bf774180..20ecbffab5 100644 --- a/boards/risc-v/mpfs/icicle/scripts/kernel-space.ld +++ b/boards/risc-v/mpfs/icicle/scripts/kernel-space.ld @@ -21,7 +21,7 @@ /* NOTE: This depends on the memory.ld script having been included prior to * this script. */ - + OUTPUT_ARCH("riscv") /* Provide these so there is no need for using config files for this */ diff --git a/boards/risc-v/mpfs/m100pfsevp/scripts/hss-nuttx.yml b/boards/risc-v/mpfs/m100pfsevp/scripts/hss-nuttx.yml index 05b4214a02..e35fb8e54b 100644 --- a/boards/risc-v/mpfs/m100pfsevp/scripts/hss-nuttx.yml +++ b/boards/risc-v/mpfs/m100pfsevp/scripts/hss-nuttx.yml @@ -1,4 +1,4 @@ -# HSS Payload Generator +# HSS Payload Generator # First, we can optionally set a name for our image, otherwise one will be created dynamically set-name: 'PolarFire-SoC-HSS::nuttx' @@ -6,7 +6,7 @@ set-name: 'PolarFire-SoC-HSS::nuttx' # Next, we'll define the entry point addresses for each hart, as follows: hart-entry-points: {u54_1: '0x80000000', u54_2: '0x80000000', u54_3: '0x80000000', u54_4: '0x80000000'} -# +# payloads: nuttx.bin: {exec-addr: '0x80000000', owner-hart: u54_1, priv-mode: prv_m} diff --git a/boards/risc-v/rv32m1/rv32m1-vega/README.txt b/boards/risc-v/rv32m1/rv32m1-vega/README.txt index 6a757d09d3..28106901c2 100644 --- a/boards/risc-v/rv32m1/rv32m1-vega/README.txt +++ b/boards/risc-v/rv32m1/rv32m1-vega/README.txt @@ -3,7 +3,7 @@ README This README discusses issues unique to NuttX configurations for the OPEN ISA RV32M1-VEGA development board featuring the RV32M1 MCU. The -RV32M1 is a heterogeneous soc including an ARM Cortex-M4 CPU, an ARM +RV32M1 is a heterogeneous soc including an ARM Cortex-M4 CPU, an ARM Cortex-M0+ CPU, a RISC-V RI5CY CPU, and a RISC-V ZERO_RISCY CPU. the SOC integrates 1.25 MB flash, 384 KB SRAM, and varieties of peripherals. The RV32M1-VEGA board features: @@ -39,13 +39,13 @@ Contents LEDs ==== -The RV32M1-VEGA board has ONE user RGB LED; Only the red part led is used to +The RV32M1-VEGA board has ONE user RGB LED; Only the red part led is used to indicate an interrupt request is being serviced. SYMBOL Meaning RED* GREEN BLUE ------------------- ----------------------- ------- ------- ----- - LED_STARTED NuttX has been started OFF OFF OFF - LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF OFF LED_IRQSENABLED Interrupts enabled OFF OFF OFF LED_STACKCREATED Idle stack created OFF OFF OFF LED_INIRQ In an interrupt** OFF OFF OFF @@ -108,7 +108,7 @@ TSTMR ==== TSTMR Module is embedded in RV32M1 to provide system time stamp. It runs off 1MHz -with a 56-bit counter, and can be adopted to get more accurate delay counting. If +with a 56-bit counter, and can be adopted to get more accurate delay counting. If the Module is selected, a hardware delay method will replace mdealy and udelay, the built-in software delay methods. @@ -116,7 +116,7 @@ TOOLCHAIN ======== It is preferable to use OPEN ISA gcc Toolchain to exploit RV32M1 RI5CY capabi- -lities, though the generic GNU RVG Toolchain can generate binary codes running +lities, though the generic GNU RVG Toolchain can generate binary codes running on RV32M1 RI5CY without any problems. To switch generic GNU RVG Toolchain to OPEN ISA Toolchain, the following option must be selected: @@ -162,9 +162,9 @@ Program ==== To program RV32M1, openocd from OPEN ISA and an external jtag adapter are pre- -requisite. There are 2 tested jtag adapters: Segger Jlink EDU mini and SiPEED -USB Jtag Adapter. The Segger Jlink EDU mini can connect J55 header on RV32M1-VEGA -board directly while SiPEED USB Jtag Adpater has to co-operate with an Adapter +requisite. There are 2 tested jtag adapters: Segger Jlink EDU mini and SiPEED +USB Jtag Adapter. The Segger Jlink EDU mini can connect J55 header on RV32M1-VEGA +board directly while SiPEED USB Jtag Adpater has to co-operate with an Adapter board to setup wires connection. Compared to Segger Jlink EDU Mini Adapter, SiPEED USB Jtag Adpater is cheaper but not inferior. @@ -200,8 +200,8 @@ https://open-isa.org/downloads/ Debug ==== -riscv64-unknonw-elf-gdb can not debug RV32M1 RISC-V Cores currently. GDB from -OPEN ISA Toolchain seems the only option and even can debug elf files generated +riscv64-unknonw-elf-gdb can not debug RV32M1 RISC-V Cores currently. GDB from +OPEN ISA Toolchain seems the only option and even can debug elf files generated by risc64-unknown-elf-* tools. Configuration Sub-directories @@ -218,8 +218,8 @@ buttons a. Start the buttons daemon: nsh> buttons - - b. Press and release SW2, SW3, SW4, SW5 freely, the button pressed + + b. Press and release SW2, SW3, SW4, SW5 freely, the button pressed and released messages will display correspondingly. nsh @@ -234,6 +234,6 @@ nsh-itcm Interrupt Service Routines are placed in ITCM. Performance can be calculated by getprime, and you might find it deteriorated a little ironically. The drawback may be caused by long jump frequently between ITCM and flash. Besides, an instr- - uction cache is enabled always after RI5CY resets, and amelioration could not be + uction cache is enabled always after RI5CY resets, and amelioration could not be achieved with even ITCM enabled. What if codes fulfill the 64KB ITCM ? diff --git a/boards/sim/sim/sim/README.txt b/boards/sim/sim/sim/README.txt index a27109c7f4..c6e25de7b9 100644 --- a/boards/sim/sim/sim/README.txt +++ b/boards/sim/sim/sim/README.txt @@ -1367,7 +1367,7 @@ vncserver This a simple vnc server test configuration, Remmina is tested and recommended since there are some compatibility issues. By default SIM will be blocked at startup to - wait client connection, if a client connected, then the fb example will launch. + wait client connection, if a client connected, then the fb example will launch. vpnkit diff --git a/boards/sparc/bm3803/xx3803/scripts/linksparc.ld b/boards/sparc/bm3803/xx3803/scripts/linksparc.ld index a095f051b7..04c7b15675 100644 --- a/boards/sparc/bm3803/xx3803/scripts/linksparc.ld +++ b/boards/sparc/bm3803/xx3803/scripts/linksparc.ld @@ -37,7 +37,7 @@ * +--------------------+ * | heap space | * | _ENDHEAP | - * | stack space | + * | stack space | * | __stack | top of stack * +--------------------+ <- high memory */ @@ -116,7 +116,7 @@ SECTIONS *(.eh_frame) . = ALIGN (16); - + /* *(.gnu.linkonce.t*) */ /* @@ -147,7 +147,7 @@ SECTIONS . = ALIGN (16); _endtext = .; } >ram - + /* .dynamic : { *(.dynamic) } >ram .got : { *(.got) } >ram @@ -158,7 +158,7 @@ SECTIONS .dynstr : { *(.dynstr) } >ram .hash : { *(.hash) } >ram */ - + .data : { data_start = .; @@ -176,7 +176,7 @@ SECTIONS .shbss : { *(.shbss) - } + } .bss : { __bss_start = ALIGN(0x10); @@ -188,10 +188,9 @@ SECTIONS _end = ALIGN(0x10); __end = ALIGN(0x10); } > ram - - + .jcr . (NOLOAD) : { *(.jcr) } - + .stab . (NOLOAD) : { [ .stab ] @@ -200,6 +199,4 @@ SECTIONS { [ .stabstr ] } - - } diff --git a/boards/sparc/bm3823/xx3823/scripts/linksparc.ld b/boards/sparc/bm3823/xx3823/scripts/linksparc.ld index b4da58e92b..63f1a8f9bb 100644 --- a/boards/sparc/bm3823/xx3823/scripts/linksparc.ld +++ b/boards/sparc/bm3823/xx3823/scripts/linksparc.ld @@ -37,7 +37,7 @@ * +--------------------+ * | heap space | * | _ENDHEAP | - * | stack space | + * | stack space | * | __stack | top of stack * +--------------------+ <- high memory */ @@ -117,7 +117,7 @@ SECTIONS *(.eh_frame) . = ALIGN (16); - + /* *(.gnu.linkonce.t*) */ /* @@ -148,7 +148,7 @@ SECTIONS . = ALIGN (16); _endtext = .; } >ram - + /* .dynamic : { *(.dynamic) } >ram .got : { *(.got) } >ram @@ -159,7 +159,7 @@ SECTIONS .dynstr : { *(.dynstr) } >ram .hash : { *(.hash) } >ram */ - + .data : { data_start = .; @@ -177,7 +177,7 @@ SECTIONS .shbss : { *(.shbss) - } + } .bss : { __bss_start = ALIGN(0x10); @@ -189,10 +189,9 @@ SECTIONS _end = ALIGN(0x10); __end = ALIGN(0x10); } > ram - - + .jcr . (NOLOAD) : { *(.jcr) } - + .stab . (NOLOAD) : { [ .stab ] @@ -201,6 +200,4 @@ SECTIONS { [ .stabstr ] } - - } diff --git a/boards/sparc/s698pm/s698pm-dkit/scripts/linksparc.ld b/boards/sparc/s698pm/s698pm-dkit/scripts/linksparc.ld index 61953ef1b8..bf8bb409ca 100644 --- a/boards/sparc/s698pm/s698pm-dkit/scripts/linksparc.ld +++ b/boards/sparc/s698pm/s698pm-dkit/scripts/linksparc.ld @@ -37,7 +37,7 @@ * +--------------------+ * | heap space | * | _ENDHEAP | - * | stack space | + * | stack space | * | __stack | top of stack * +--------------------+ <- high memory */ @@ -109,7 +109,7 @@ SECTIONS *(.eh_frame) . = ALIGN (16); - + /* *(.gnu.linkonce.t*) */ /* @@ -140,7 +140,7 @@ SECTIONS . = ALIGN (16); _endtext = .; } >ram - + /* .dynamic : { *(.dynamic) } >ram .got : { *(.got) } >ram @@ -151,7 +151,7 @@ SECTIONS .dynstr : { *(.dynstr) } >ram .hash : { *(.hash) } >ram */ - + .data : { data_start = .; @@ -169,7 +169,7 @@ SECTIONS .shbss : { *(.shbss) - } + } .bss : { __bss_start = ALIGN(0x10); @@ -187,9 +187,9 @@ SECTIONS *(.noinit*) _enoinit = ABSOLUTE(.); } > ram - + .jcr . (NOLOAD) : { *(.jcr) } - + .stab . (NOLOAD) : { [ .stab ] @@ -198,5 +198,4 @@ SECTIONS { [ .stabstr ] } - } diff --git a/boards/xtensa/esp32/common/src/esp32_board_spi.c b/boards/xtensa/esp32/common/src/esp32_board_spi.c index c9aefde260..7d6e300600 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_spi.c +++ b/boards/xtensa/esp32/common/src/esp32_board_spi.c @@ -71,7 +71,7 @@ static inline uint8_t spi_status(struct spi_dev_s *dev, uint32_t devid) static inline int spi_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { -#if defined(CONFIG_LCD_ILI9341) || defined(CONFIG_LCD_SSD1680) || defined(CONFIG_LCD_ST7789) +#if defined(CONFIG_LCD_ILI9341) || defined(CONFIG_LCD_SSD1680) || defined(CONFIG_LCD_ST7789) if (devid == SPIDEV_DISPLAY(0)) { /* This is the Data/Command control pad which determines whether the diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/README.txt b/boards/xtensa/esp32/esp32-ethernet-kit/README.txt index 0a1a6031d5..fbc5904264 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/README.txt +++ b/boards/xtensa/esp32/esp32-ethernet-kit/README.txt @@ -76,4 +76,3 @@ A new image "esp32_qemu_image.bin" will be created. It can be run as: ~/PATH_TO_QEMU/qemu/build/xtensa-softmmu/qemu-system-xtensa -nographic \ -machine esp32 \ -drive file=esp32_qemu_image.bin,if=mtd,format=raw - diff --git a/drivers/audio/wm8994.h b/drivers/audio/wm8994.h index 59248b3b4e..f64667e8d1 100644 --- a/drivers/audio/wm8994.h +++ b/drivers/audio/wm8994.h @@ -381,14 +381,14 @@ #define WM8994_MICB2_ENA_ENABLE (WM8994_MICB2_ENA) /* Enabled */ /* Bits 6-7: Reserved */ #define WM8994_HPOUT1R_ENA (1 << 8) /* Bit 8: Enables HPOUT1R input stage */ -#define WM8994_HPOUT1R_ENA_DISABLE (0) /* Disabled */ +#define WM8994_HPOUT1R_ENA_DISABLE (0) /* Disabled */ #define WM8994_HPOUT1R_ENA_ENABLE (WM8994_HPOUT1R_ENA) /* Enabled */ #define WM8994_HPOUT1L_ENA (1 << 9) /* Bit 9: Enables HPOUT1L input stage */ -#define WM8994_HPOUT1L_ENA_DISABLE (0) /* Disabled */ +#define WM8994_HPOUT1L_ENA_DISABLE (0) /* Disabled */ #define WM8994_HPOUT1L_ENA_ENABLE (WM8994_HPOUT1L_ENA) /* Enabled */ /* Bit 10: Reserved */ #define WM8994_HPOUT2_ENA (1 << 11) /* Bit 11: Enables HPOUT2 input stage */ -#define WM8994_HPOUT2_ENA_DISABLE (0) /* Disabled */ +#define WM8994_HPOUT2_ENA_DISABLE (0) /* Disabled */ #define WM8994_HPOUT2_ENA_ENABLE (WM8994_HPOUT2_ENA) /* Enabled */ #define WM8994_SPKOUTL_ENA (1 << 12) /* Bit 12: SPKMIXL Mixer, SPKLVOL PGA and SPKOUTL Output Enable */ #define WM8994_SPKOUTL_ENA_DISABLE (0) /* Disabled */ @@ -427,11 +427,11 @@ #define WM8994_OPCLK_ENA_ENABLE (WM8994_OPCLK_ENA) /* Enabled */ /* Bit 12: Reserved */ #define WM8994_TSHUT_OPDIS (1 << 13) /* Bit 13: Thermal shutdown control */ -#define WM8994_TSHUT_OPDIS_DISABLE (0) /* Disabled */ -#define WM8994_TSHUT_OPDIS_ENABLE (WM8994_TSHUT_OPDIS) /* Enabled */ +#define WM8994_TSHUT_OPDIS_DISABLE (0) /* Disabled */ +#define WM8994_TSHUT_OPDIS_ENABLE (WM8994_TSHUT_OPDIS) /* Enabled */ #define WM8994_TSHUT_ENA (1 << 14) /* Bit 14: Thermal sensor enable */ -#define WM8994_TSHUT_ENA_DISABLE (0) /* Disabled */ -#define WM8994_TSHUT_ENA_ENABLE (WM8994_TSHUT_ENA) /* Enabled */ +#define WM8994_TSHUT_ENA_DISABLE (0) /* Disabled */ +#define WM8994_TSHUT_ENA_ENABLE (WM8994_TSHUT_ENA) /* Enabled */ /* Bit 15: Reserved */ /* R3 (0x03) - Power Management (3) @@ -440,22 +440,22 @@ /* Bits 0-3: Reserved */ #define WM8994_MIXOUTR_ENA (1 << 4) /* Bit 4: MIXOUTR Right Output Mixer Enable */ #define WM8994_MIXOUTR_ENA_DISABLE (0) /* Disabled */ -#define WM8994_MIXOUTR_ENA_ENABLE (WM8994_MIXOUTR_ENA) /* Enabled */ +#define WM8994_MIXOUTR_ENA_ENABLE (WM8994_MIXOUTR_ENA) /* Enabled */ #define WM8994_MIXOUTL_ENA (1 << 5) /* Bit 5: MIXOUTL Left Output Mixer Enable */ #define WM8994_MIXOUTL_ENA_DISABLE (0) /* Disabled */ -#define WM8994_MIXOUTL_ENA_ENABLE (WM8994_MIXOUTL_ENA) /* Enabled */ +#define WM8994_MIXOUTL_ENA_ENABLE (WM8994_MIXOUTL_ENA) /* Enabled */ #define WM8994_MIXOUTRVOL_ENA (1 << 6) /* Bit 6: MIXOUTR Right Volume Control Enable */ #define WM8994_MIXOUTRVOL_ENA_DISABLE (0) /* Disabled */ -#define WM8994_MIXOUTRVOL_ENA_ENABLE (WM8994_MIXOUTRVOL_ENA) /* Enabled */ +#define WM8994_MIXOUTRVOL_ENA_ENABLE (WM8994_MIXOUTRVOL_ENA) /* Enabled */ #define WM8994_MIXOUTLVOL_ENA (1 << 7) /* Bit 7: MIXOUTL Left Volume Control Enable */ #define WM8994_MIXOUTLVOL_ENA_DISABLE (0) /* Disabled */ -#define WM8994_MIXOUTLVOL_ENA_ENABLE (WM8994_MIXOUTLVOL_ENA) /* Enabled */ +#define WM8994_MIXOUTLVOL_ENA_ENABLE (WM8994_MIXOUTLVOL_ENA) /* Enabled */ #define WM8994_SPKLVOL_ENA (1 << 8) /* Bit 8: SPKMIXL Mixer and SPKLVOL PGA Enable */ #define WM8994_SPKLVOL_ENA_DISABLE (0) /* Disabled */ -#define WM8994_SPKLVOL_ENA_ENABLE (WM8994_SPKLVOL_ENA) /* Enabled */ +#define WM8994_SPKLVOL_ENA_ENABLE (WM8994_SPKLVOL_ENA) /* Enabled */ #define WM8994_SPKRVOL_ENA (1 << 9) /* Bit 9: SPKMIXR Mixer and SPKRVOL PGA Enable */ #define WM8994_SPKRVOL_ENA_DISABLE (0) /* Disabled */ -#define WM8994_SPKRVOL_ENA_ENABLE (WM8994_SPKRVOL_ENA) /* Enabled */ +#define WM8994_SPKRVOL_ENA_ENABLE (WM8994_SPKRVOL_ENA) /* Enabled */ #define WM8994_LINEOUT2P_ENA (1 << 10) /* Bit 10: LINEOUT2P Line Out and LINEOUT2PMIX Enable */ #define WM8994_LINEOUT2P_ENA_DISABLE (0) /* Disabled */ #define WM8994_LINEOUT2P_ENA_ENABLE (WM8994_LINEOUT2P_ENA) /* Enabled */ @@ -481,16 +481,16 @@ #define WM8994_ADCL_ENA_ENABLE (WM8994_ADCL_ENA) /* Enabled */ #define WM8994_DMIC1R_ENA (1 << 2) /* Bit 2: Digital microphone DMICDAT1 Right channel enable */ #define WM8994_DMIC1R_ENA_DISABLE (0) /* Disabled */ -#define WM8994_DMIC1R_ENA_ENABLE (WM8994_DMIC1R_ENA) /* Enabled */ +#define WM8994_DMIC1R_ENA_ENABLE (WM8994_DMIC1R_ENA) /* Enabled */ #define WM8994_DMIC1L_ENA (1 << 3) /* Bit 3: Digital microphone DMICDAT1 Left channel enable */ #define WM8994_DMIC1L_ENA_DISABLE (0) /* Disabled */ -#define WM8994_DMIC1L_ENA_ENABLE (WM8994_DMIC1L_ENA) /* Enabled */ +#define WM8994_DMIC1L_ENA_ENABLE (WM8994_DMIC1L_ENA) /* Enabled */ #define WM8994_DMIC2R_ENA (1 << 4) /* Bit 4: Digital microphone DMICDAT2 Right channel enable */ #define WM8994_DMIC2R_ENA_DISABLE (0) /* Disabled */ -#define WM8994_DMIC2R_ENA_ENABLE (WM8994_DMIC2R_ENA) /* Enabled */ +#define WM8994_DMIC2R_ENA_ENABLE (WM8994_DMIC2R_ENA) /* Enabled */ #define WM8994_DMIC2L_ENA (1 << 5) /* Bit 5: Digital microphone DMICDAT2 Left channel enable */ #define WM8994_DMIC2L_ENA_DISABLE (0) /* Disabled */ -#define WM8994_DMIC2L_ENA_ENABLE (WM8994_DMIC2L_ENA) /* Enabled */ +#define WM8994_DMIC2L_ENA_ENABLE (WM8994_DMIC2L_ENA) /* Enabled */ /* Bits 6-7: Reserved */ #define WM8994_AIF1ADC1R_ENA (1 << 8) /* Bit 8: Enable AIF1ADC1(Right) output path (AIF1, Timeslot 0) */ #define WM8994_AIF1ADC1R_ENA_DISABLE (0) /* Disabled */ @@ -568,7 +568,7 @@ #define WM8994_IN1L_VOL_DEFAULT (11 << 0) /* -16.5dB to +30dB in 1.5dB steps */ #define WM8994_IN1L_VOL_MAX (31 << 0) /* +30dB */ /* Bit 5: Reserved */ -#define WM8994_IN1L_ZC (1 << 6) /* Bit 6: IN1L PGA Zero Cross Detector */ +#define WM8994_IN1L_ZC (1 << 6) /* Bit 6: IN1L PGA Zero Cross Detector */ #define WM8994_IN1L_ZC_NO (0) /* Change gain immediately */ #define WM8994_IN1L_ZC_YES (WM8994_IN1L_ZC) /* Change gain on zero cross only */ #define WM8994_IN1L_MUTE (1 << 7) /* Bit 7: IN1L PGA Mute */ @@ -586,7 +586,7 @@ #define WM8994_IN2L_VOL_DEFAULT (11 << WM8994_IN2L_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */ #define WM8994_IN2L_VOL_MAX (31 << WM8994_IN2L_VOL_SHIFT) /* +30dB */ /* Bit 5: Reserved */ -#define WM8994_IN2L_ZC (1 << 6) /* Bit 6: IN2L PGA Zero Cross Detector */ +#define WM8994_IN2L_ZC (1 << 6) /* Bit 6: IN2L PGA Zero Cross Detector */ #define WM8994_IN2L_ZC_NO (0) /* Change gain immediately */ #define WM8994_IN2L_ZC_YES (WM8994_IN2L_ZC) /* Change gain on zero cross only */ #define WM8994_IN2L_MUTE (1 << 7) /* Bit 7: IN2L PGA Mute */ @@ -604,7 +604,7 @@ #define WM8994_IN1R_VOL_DEFAULT (11 << WM8994_IN1R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */ #define WM8994_IN1R_VOL_MAX (31 << WM8994_IN1R_VOL_SHIFT) /* +30dB */ /* Bit 5: Reserved */ -#define WM8994_IN1R_ZC_SHIFT (6) /* Bit 6: IN1R PGA Zero Cross Detector */ +#define WM8994_IN1R_ZC_SHIFT (6) /* Bit 6: IN1R PGA Zero Cross Detector */ #define WM8994_IN1R_ZC_NO (0) /* Change gain immediately */ #define WM8994_IN1R_ZC_YES (1 << WM8994_IN1R_ZC_SHIFT) /* Change gain on zero cross only */ #define WM8994_IN1R_MUTE_SHIFT (7) /* Bit 7: IN1R PGA Mute */ @@ -623,7 +623,7 @@ #define WM8994_IN2R_VOL_DEFAULT (11 << WM8994_IN2R_VOL_SHIFT) /* -16.5dB to +30dB in 1.5dB steps */ #define WM8994_IN2R_VOL_MAX (31 << WM8994_IN2R_VOL_SHIFT) /* +30dB */ /* Bit 5: Reserved */ -#define WM8994_IN2R_ZC_SHIFT (6) /* Bit 6: IN2R PGA Zero Cross Detector */ +#define WM8994_IN2R_ZC_SHIFT (6) /* Bit 6: IN2R PGA Zero Cross Detector */ #define WM8994_IN2R_ZC_NO (0) /* Change gain immediately */ #define WM8994_IN2R_ZC_YES (1 << WM8994_IN2R_ZC_SHIFT) /* Change gain on zero cross only */ #define WM8994_IN2R_MUTE_SHIFT (7) /* Bit 7: IN2R PGA Mute */ @@ -648,7 +648,7 @@ #define WM8994_HPOUT1L_ZC_DIABLED (0) /* Zero cross disabled */ #define WM8994_HPOUT1L_ZC_ENABLED (1 << WM8994_HPOUT1L_ZC_SHIFT) /* Zero cross enabled */ #define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */ -#define WM8994_HPOUT1_VU_DISABLE (0) +#define WM8994_HPOUT1_VU_DISABLE (0) #define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and * HPOUT1RVOL volumes simultaneously */ @@ -734,10 +734,10 @@ #define WM8994_IN2LP_TO_MIXOUTL_UNMUTE (WM8994_IN2LP_TO_MIXOUTL) /* Un-mute */ #define WM8994_IN1L_TO_MIXOUTL (1 << 2) /* Bit 2: IN1L PGA Output to MIXOUTL Mute */ #define WM8994_IN1L_TO_MIXOUTL_MUTE (0) /* Mute */ -#define WM8994_IN1L_TO_MIXOUTL_UNMUTE (WM8994_IN1L_TO_MIXOUTL_MUTE) /* Un-mute */ +#define WM8994_IN1L_TO_MIXOUTL_UNMUTE (WM8994_IN1L_TO_MIXOUTL_MUTE) /* Un-mute */ #define WM8994_IN1R_TO_MIXOUTL (1 << 3) /* Bit 3: IN1R PGA Output to MIXOUTL Mute */ #define WM8994_IN1R_TO_MIXOUTL_MUTE (0) /* Mute */ -#define WM8994_IN1R_TO_MIXOUTL_UNMUTE (WM8994_IN1R_TO_MIXOUTL_MUTE) /* Un-mute */ +#define WM8994_IN1R_TO_MIXOUTL_UNMUTE (WM8994_IN1R_TO_MIXOUTL_MUTE) /* Un-mute */ #define WM8994_IN2LN_TO_MIXOUTL (1 << 4) /* Bit 4: IN2LN to MIXOUTL Mute */ #define WM8994_IN2LN_TO_MIXOUTL_MUTE (0) /* Mute */ #define WM8994_IN2LN_TO_MIXOUTL_UNMUTE (WM8994_IN2LN_TO_MIXOUTL) /* Un-mute */ @@ -862,8 +862,8 @@ #define WM8994_VMID_DISCH_DISABLE (0) /* Disabled */ #define WM8994_VMID_DISCH_ENABLE WM8994_VMID_DISCH /* Enabled */ #define WM8994_BIAS_SRC (1 << 1) /* Bit 1: Selects the bias current source */ -# define WM8994_BIAS_SRC_NORMAL_BIAS (0) /* Normal bias */ -# define WM8994_BIAS_SRC_STARTUP_BIAS WM8994_BIAS_SRC /* Start-Up bias */ +# define WM8994_BIAS_SRC_NORMAL_BIAS (0) /* Normal bias */ +# define WM8994_BIAS_SRC_STARTUP_BIAS WM8994_BIAS_SRC /* Start-Up bias */ #define WM8994_STARTUP_BIAS_ENA (1 << 2) /* Bit 2: Enables the Start-Up bias current generator */ #define WM8994_VMID_BUF_ENA (1 << 3) /* Bit 3: VMID Buffer Enable */ #define WM8994_VMID_RAMP_SHIFT (5) /* Bits 5-6: VMID soft start enable/slew rate control */ @@ -1036,7 +1036,7 @@ /* R512 (0x200) - AIF1 Clocking (1) */ -#define WM8994_AIF1CLK_ENA (1 << 0) /* Bit 0: AIF1CLK Enable */ +#define WM8994_AIF1CLK_ENA (1 << 0) /* Bit 0: AIF1CLK Enable */ #define WM8994_AIF1CLK_DIV (1 << 1) /* Bit 1: AIF1CLK Divider */ #define WM8994_AIF1CLK_DIV_0 (0) /* AIF1CLK/1 */ #define WM8994_AIF1CLK_DIV_1 (WM8994_AIF1CLK_DIV) /* AIF1CLK/2 */ @@ -1079,7 +1079,7 @@ */ #define WM8994_AIF1CLK_RATE_SHIFT (0) /* Bits 0-3: Selects the AIF1CLK/fs ratio */ -#define WM8994_AIF1CLK_RATE_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT) +#define WM8994_AIF1CLK_RATE_MASK (0xf << WM8994_AIF1CLK_RATE_SHIFT) #define WM8994_AIF1CLK_RATE_0 (0 << WM8994_AIF1CLK_RATE_SHIFT) /* Reserved */ #define WM8994_AIF1CLK_RATE_1 (1 << WM8994_AIF1CLK_RATE_SHIFT) /* 128 */ #define WM8994_AIF1CLK_RATE_2 (2 << WM8994_AIF1CLK_RATE_SHIFT) /* 192 */ @@ -1158,8 +1158,8 @@ /* Bits 0-2: Reserved */ #define WM8994_AIF1_FMT_SHIFT (3) /* Bits 3-4: AIF1 Digital Audio Interface Format */ -#define WM8994_AIF1_FMT_MASK (3 << WM8994_AIF1_FMT_SHIFT) -#define WM8994_AIF1_FMT_RIGHT (0 << WM8994_AIF1_FMT_SHIFT) /* Right justified */ +#define WM8994_AIF1_FMT_MASK (3 << WM8994_AIF1_FMT_SHIFT) +#define WM8994_AIF1_FMT_RIGHT (0 << WM8994_AIF1_FMT_SHIFT) /* Right justified */ #define WM8994_AIF1_FMT_LEFT (1 << WM8994_AIF1_FMT_SHIFT) /* Left justified */ #define WM8994_AIF1_FMT_I2S (2 << WM8994_AIF1_FMT_SHIFT) /* I2S Format */ #define WM8994_AIF1_FMT_DSP (3 << WM8994_AIF1_FMT_SHIFT) /* DSP Mode */ @@ -1172,10 +1172,10 @@ #define WM8994_AIF1ADC_TDM (1 << 13) /* Bit 13: AIF1 transmit (ADC) TDM control */ #define WM8994_AIF1ADC_TDM_0 (0) /* ADCDAT1 driver logic '0' when not transmit data */ #define WM8994_AIF1ADC_TDM_TRI (WM8994_AIF1ADC_TDM) /* ADCDAT1 is tri-stated when not transmit data */ -#define WM8994_AIF1ADCR_SRC (1 << 14) /* Bit 14: AIF1 Right Audio Interface Source */ +#define WM8994_AIF1ADCR_SRC (1 << 14) /* Bit 14: AIF1 Right Audio Interface Source */ #define WM8994_AIF1ADCR_LEFT_ADC (0) /* Left ADC data is output on right channel */ #define WM8994_AIF1ADCR_RIGHT_ADC (WM8994_AIF1ADCR_SRC) /* Right ADC data is output on right channel */ -#define WM8994_AIF1ADCL_SRC (1 << 15) /* Bit 15: AIF1 Left Audio Interface Source */ +#define WM8994_AIF1ADCL_SRC (1 << 15) /* Bit 15: AIF1 Left Audio Interface Source */ #define WM8994_AIF1ADCL_LEFT_ADC (0) /* Left ADC data is output on left channel */ #define WM8994_AIF1ADCL_RIGHT_ADC (WM8994_AIF1ADCL_SRC) /* Right ADC data is output on left channel */ @@ -1196,7 +1196,7 @@ #define WM8994_AIF1_MSTR_SLAVE_MODE (0) /* Slave Mode */ #define WM8994_AIF1_MSTR_MASTER_MODE (WM8994_AIF1_MSTR) /* Master Mode */ #define WM8994_AIF1_TRI (1 << 15) /* Bit 15: AIF1 Audio Interface tri-state */ -#define WM8994_AIF1_TRI_NORMAL (0) /* AIF1 pins operate normally */ +#define WM8994_AIF1_TRI_NORMAL (0) /* AIF1 pins operate normally */ #define WM8994_AIF1_TRI_TRI (WM8994_AIF1_TRI) /* Tri-state all AIF1 interface pins */ /* R771 (0x303) - AIF1 BCLK @@ -1778,7 +1778,7 @@ #define WM8994_AUDIO_FREQUENCY_96K 96000UL #define WM8994_AUDIO_FREQUENCY_192K 192000UL -#define WM8994_DEFAULT_SAMPRATE (WM8994_AUDIO_FREQUENCY_48K) +#define WM8994_DEFAULT_SAMPRATE (WM8994_AUDIO_FREQUENCY_48K) #define WM8994_DEFAULT_NCHANNELS 0 #define WM8994_DEFAULT_BPSAMP 0 diff --git a/drivers/lcd/Kconfig b/drivers/lcd/Kconfig index 5a112431b0..860a1d97f4 100644 --- a/drivers/lcd/Kconfig +++ b/drivers/lcd/Kconfig @@ -357,23 +357,23 @@ config LCD_SSD1306_CUSTOM if LCD_SSD1306_CUSTOM -config LCD_SSD1306_CUSTOM_DEV_NATIVE_XRES +config LCD_SSD1306_CUSTOM_DEV_NATIVE_XRES int "Custom LCD native X-resolution" default 128 -config LCD_SSD1306_CUSTOM_DEV_NATIVE_YRES +config LCD_SSD1306_CUSTOM_DEV_NATIVE_YRES int "Custom LCD native Y-resolution" default 32 -config LCD_SSD1306_CUSTOM_DEV_XOFFSET +config LCD_SSD1306_CUSTOM_DEV_XOFFSET int "Custom LCD X-offset" default 0 -config LCD_SSD1306_CUSTOM_DEV_PAGES +config LCD_SSD1306_CUSTOM_DEV_PAGES int "Custom LCD number of pages" default 4 -config LCD_SSD1306_CUSTOM_DEV_CMNPAD +config LCD_SSD1306_CUSTOM_DEV_CMNPAD int "Custom LCD COM configuration (cmnpad)" default 2 @@ -1584,7 +1584,7 @@ config SSD1680_FREQUENCY default 5000000 range 100000 20000000 ---help--- - Selects the SPI bus frequency used with the SSD1680 device. + Selects the SPI bus frequency used with the SSD1680 device. Max for read mode is 2.5 MHz, for write mode is 20 HHz endif # LCD_SSD1680 diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 3163dd5aa9..36e14e0403 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -128,7 +128,7 @@ config DEBUG_LP503X bool "Enable debug support for the LP503X" default n ---help--- - Enables debug support for the LP503X + Enables debug support for the LP503X endif # LP503X @@ -178,7 +178,7 @@ config WS2812_LED_COUNT range 1 65535 depends on WS2812 ---help--- - The number of ws2812s chained to this port. Although the + The number of ws2812s chained to this port. Although the driver allows up to 65,535 ws2812s the practical limit will depend on processor speed and other resources. @@ -205,5 +205,5 @@ config WS2812_FREQUENCY to the bit frequency of the ws2812s being used. Newer chips use an 800 kHz bit frequency (the default); although, some older chips run at 400 kHz. - + endmenu # LED Support diff --git a/drivers/leds/lp503x.c b/drivers/leds/lp503x.c index 2e5011b7c1..4cf4623126 100644 --- a/drivers/leds/lp503x.c +++ b/drivers/leds/lp503x.c @@ -85,7 +85,7 @@ struct lp503x_config_s config_default = #endif #ifdef CONFIG_LP503X_POWER_SAVE .enable_power_save = 1, -#else +#else .enable_power_save = 0, #endif #ifdef CONFIG_LP503X_DITHER_MODE @@ -139,7 +139,7 @@ static int lp503x_dump_registers(struct lp503x_dev_s *priv, const char *msg); #else # define lp503x_dump_registers(priv, msg); -#endif +#endif static int lp503x_reset(struct lp503x_dev_s *priv); static int lp503x_enable(struct lp503x_dev_s *priv, bool enable); static int lp503x_set_rgbbrightness(struct lp503x_dev_s *priv, int led, diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 54d385e93f..55cbee1aaa 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -147,7 +147,7 @@ config ACT8945A_SYSLEV_3800 endchoice # ACT8945A SYSLEV threshold -choice +choice prompt "ACT8945A SYSLEV mode" default ACT8945A_SYSLEV_MODE_INTERRUPT ---help--- @@ -203,7 +203,7 @@ config ACT8945A_DCDC1_APPLY_UV ---help--- If set, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If not set, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -243,7 +243,7 @@ config ACT8945A_DCDC2_NAME ---help--- This is the name used for the ACT8945A DCDC converter output 2. It is used as the consumer name when you get or put a regulator. - + config ACT8945A_DCDC2_BOOT_ON bool "Enable DCDC2" default y @@ -254,7 +254,7 @@ config ACT8945A_DCDC2_APPLY_UV ---help--- If set, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If not set, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -305,7 +305,7 @@ config ACT8945A_DCDC3_APPLY_UV ---help--- If set to 1, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If set to 0, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -356,7 +356,7 @@ config ACT8945A_LDO1_APPLY_UV ---help--- If set to 1, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If set to 0, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -411,7 +411,7 @@ config ACT8945A_LDO2_APPLY_UV ---help--- If set to 1, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If set to 0, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -466,7 +466,7 @@ config ACT8945A_LDO3_APPLY_UV ---help--- If set to 1, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If set to 0, MIN_UV and MAX_UV values will be ignored during initialisation. @@ -521,7 +521,7 @@ config ACT8945A_LDO4_APPLY_UV ---help--- If set, the driver will attempt to set the voltage nearest to MIN_UV, that is also lower than MAX_UV, during initialisation. - + If not, MIN_UV and MAX_UV values will be ignored during initialisation. diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index e5d3187821..197019b856 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -314,9 +314,9 @@ config SYSLOG_FILE_SEPARATE ---help--- If enabled, every time the file logger is re-attached, a separator will be printed in the file. - + This can be useful to easily distinguish between log entries that - belong to different log sessions (e.g. system reboot), and to + belong to different log sessions (e.g. system reboot), and to indicate that between the separated lines there may be more logs that were lost. @@ -328,10 +328,10 @@ config SYSLOG_FILE_ROTATIONS checked before opening. If it is larger than the specified limit it will be "rotated", i.e. the old file will be kept as a backup, and a new empty file will be created. - + The number of rotations specifies the number of old log files to keep. - + This option is useful to ensure that log files do not get huge after prolonged periods of system operation. diff --git a/drivers/usbmisc/fusb302.c b/drivers/usbmisc/fusb302.c index bbbf5a58b2..9022df24ea 100644 --- a/drivers/usbmisc/fusb302.c +++ b/drivers/usbmisc/fusb302.c @@ -75,7 +75,7 @@ #define SWITCHES0_VCONN_CC2 (1 << 5) #define SWITCHES0_VCONN_SHIFT (4) #define SWITCHES0_VCONN_MASK (3 << SWITCHES0_VCONN_SHIFT) -#define SWITCHES0_PULLUP_CC1 (1 << 6) +#define SWITCHES0_PULLUP_CC1 (1 << 6) #define SWITCHES0_PULLUP_CC2 (1 << 7) #define SWITCHES0_PULLUP_SHIFT (6) #define SWITCHES0_PULLUP_MASK (3 << SWITCHES0_PULLUP_SHIFT) @@ -96,7 +96,7 @@ #define MEASURE_MDAC_SHIFT (0) /* Bits 5:0 MDAC */ #define MEASURE_MDAC_MASK (0b111111 << MEASURE_MDAC_SHIFT) #define MEASURE_MDAC(n) ((uint8_t)(n)) << MEASURE_MDAC_SHIFT -#define MEASURE_VBUS_BY_MDAC (1 << 6) +#define MEASURE_VBUS_BY_MDAC (1 << 6) #define SET_MDAC(n) ((uint8_t)(n)) << MEASURE_MDAC_SHIFT) /* Slice - 0x05 */ @@ -104,14 +104,14 @@ #define MEASURE_SDAC_SHIFT (0) /* Bits 5:0 SDAC */ #define MEASURE_SDAC_MASK (0b111111 < MEASURE_SDAC_SHIFT) #define MEASURE_SDAC(n) ((uint8_t)(n)) << MEASURE_SDAC_SHIFT) -#define MEASURE_SDAC_HYS_SHIFT (6) /* Bits 7:6 SDAC hysteris */ +#define MEASURE_SDAC_HYS_SHIFT (6) /* Bits 7:6 SDAC hysteris */ #define MEASURE_SDAC_HYS_MASK (0b11 << MEASURE_SDAC_HYS_SHIFT) #define SDAC_HYS_VAL(n) ((uint8)t)(n)) << MEASURE_SDAC_HYS_SHIFT) /* Control0 - 0x06 */ #define CONTROL0_TX_START_MASK (1 << 0) -#define CONTROL0_AUTO_PRE_SHIFT (1) +#define CONTROL0_AUTO_PRE_SHIFT (1) #define CONTROL0_HOST_CUR_SHIFT (2) /* Bits 3:2 Host Current mode */ #define CONTROL0_HOST_CUR_MASK (3 << CONTROL0_HOST_CUR_SHIFT) #define HOST_CURRENT_NONE (0) /* no current */ @@ -119,8 +119,8 @@ #define HOST_CURRENT_180UA (2) /* medium power, 1.5A */ #define HOST_CURRENT_330UA (3) /* high power, 3A */ #define HOST_CURRENT(n) ((uint8_t)(n) << CONTROL0_HOST_CUR_SHIFT) -#define CONTROL0_INT_MASK (1 << 5) -#define CONTROL0_TX_FLUSH (1 << 6) +#define CONTROL0_INT_MASK (1 << 5) +#define CONTROL0_TX_FLUSH (1 << 6) /* Control1 - 0x07 */ @@ -143,7 +143,7 @@ #define CONTROL2_WAKE_EN (1 << 3) #define CONTROL2_TOG_RD_ONLY (1 << 5) #define CONTROL2_TOG_SAVE_PWR_SHIFT (6) /* Bits 7:6 */ -#define CONTROL2_TOG_SAVE_PWR_MASK (0b11 << CONTROL2_TOG_SAVE_PWR_SHIFT +#define CONTROL2_TOG_SAVE_PWR_MASK (0b11 << CONTROL2_TOG_SAVE_PWR_SHIFT #define WAIT_NONE (0b00) #define WAIT_40MS (0b01) #define WAIT_80MS (0b10) @@ -152,7 +152,7 @@ /* Control3 - 0x09 */ -#define CONTROL3_AUTO_RETRY (0) +#define CONTROL3_AUTO_RETRY (0) #define CONTROL3_N_RETRIES_SHIFT (1) /* Bits 2:1 */ #define CONTROL3_N_RETRIES_MASK (0b11 << CONTROL3_N_RETRIES_SHIFT) #define NO_RETRIES (0b00) @@ -161,8 +161,8 @@ #define THREE_RETRIES (0b11) #define SET_NUM_RETRIES(n) ((uint8_t(n) << CONTROL3_N_RETRIES_SHIFT) #define CONTROL3_AUTO_SOFTRESET (1 << 3) -#define CONTROL3_AUTO_HARDRESET (1 << 4) -#define CONTROL3_SEND_HARDRESET (1 << 6) +#define CONTROL3_AUTO_HARDRESET (1 << 4) +#define CONTROL3_SEND_HARDRESET (1 << 6) /* Mask - 0x0A */ diff --git a/fs/Kconfig b/fs/Kconfig index 2989fc6299..2bf53b20f1 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -50,7 +50,7 @@ config FS_AUTOMOUNTER_DRIVER Enabling this option will lead to registering of a character driver on FS_AUTOMOUNTER_VFS_PATH + mount point path for auto-mounter. Example: /var/mnt/sdcard0 - + config FS_AUTOMOUNTER_VFS_PATH string "Path to auto-mounter driver" default "/var" diff --git a/include/nuttx/wireless/lte/lte.h b/include/nuttx/wireless/lte/lte.h index 16afa46473..c9590d11d2 100644 --- a/include/nuttx/wireless/lte/lte.h +++ b/include/nuttx/wireless/lte/lte.h @@ -123,7 +123,7 @@ * deprecated. Use LTE_IPTYPE_V4 instead. */ -#define LTE_APN_IPTYPE_IP LTE_IPTYPE_V4 +#define LTE_APN_IPTYPE_IP LTE_IPTYPE_V4 /* Internet protocol type: IPv6 * deprecated. Use LTE_IPTYPE_V6 instead. diff --git a/libs/libc/machine/arm/armv7-a/gnu/arch_memchr.S b/libs/libc/machine/arm/armv7-a/gnu/arch_memchr.S index 4842bb29a2..338cb26f73 100644 --- a/libs/libc/machine/arm/armv7-a/gnu/arch_memchr.S +++ b/libs/libc/machine/arm/armv7-a/gnu/arch_memchr.S @@ -300,7 +300,7 @@ memchr: and r1,r1,#0xff @ Don't trust the caller to pass a char cmp r2,#16 @ If short don't bother with anything clever - blt 20f + blt 20f tst r0, #7 @ If it's already aligned skip the next bit beq 10f @@ -314,7 +314,7 @@ memchr: tst r0, #7 cbz r2, 40f @ If we run off the end, exit not found bne 5b @ If not aligned yet then do next byte - + 10: @ We are aligned, we know we have at least 8 bytes to work with push {r4,r5,r6,r7} @@ -323,7 +323,7 @@ memchr: bic r4, r2, #7 @ Number of double words to work with * 8 mvns r7, #0 @ all F's movs r3, #0 - + 15: ldrd r5,r6,[r0],#8 subs r4, r4, #8 @@ -361,7 +361,7 @@ memchr: subs r0,r0,#1 @ found bx lr -60: @ We're here because the fast path found a hit +60: @ We're here because the fast path found a hit @ now we have to track down exactly which word it was @ r0 points to the start of the double word after the one tested @ r5 has the 00/ff pattern for the first word, r6 has the chained value diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S b/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S index f50b229074..4be1d6cca2 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S @@ -300,7 +300,7 @@ memchr: and r1,r1,#0xff @ Don't trust the caller to pass a char cmp r2,#16 @ If short don't bother with anything clever - blt 20f + blt 20f tst r0, #7 @ If it's already aligned skip the next bit beq 10f @@ -314,7 +314,7 @@ memchr: tst r0, #7 cbz r2, 40f @ If we run off the end, exit not found bne 5b @ If not aligned yet then do next byte - + 10: @ We are aligned, we know we have at least 8 bytes to work with push {r4,r5,r6,r7} @@ -323,7 +323,7 @@ memchr: bic r4, r2, #7 @ Number of double words to work with * 8 mvns r7, #0 @ all F's movs r3, #0 - + 15: ldrd r5,r6,[r0],#8 subs r4, r4, #8 @@ -342,7 +342,7 @@ memchr: and r1,r1,#0xff @ r1 back to a single character and r2,r2,#7 @ Leave the count remaining as the number @ after the double words have been done - + 20: cbz r2, 40f @ 0 length or hit the end already then not found @@ -361,7 +361,7 @@ memchr: subs r0,r0,#1 @ found bx lr -60: @ We're here because the fast path found a hit +60: @ We're here because the fast path found a hit @ now we have to track down exactly which word it was @ r0 points to the start of the double word after the one tested @ r5 has the 00/ff pattern for the first word, r6 has the chained value diff --git a/libs/libc/machine/arm/armv8-m/gnu/arch_memchr.S b/libs/libc/machine/arm/armv8-m/gnu/arch_memchr.S index cd640c4c4b..ad7a3a1289 100644 --- a/libs/libc/machine/arm/armv8-m/gnu/arch_memchr.S +++ b/libs/libc/machine/arm/armv8-m/gnu/arch_memchr.S @@ -298,7 +298,7 @@ memchr: and r1,r1,#0xff @ Don't trust the caller to pass a char cmp r2,#16 @ If short don't bother with anything clever - blt 20f + blt 20f tst r0, #7 @ If it's already aligned skip the next bit beq 10f @@ -312,7 +312,7 @@ memchr: tst r0, #7 cbz r2, 40f @ If we run off the end, exit not found bne 5b @ If not aligned yet then do next byte - + 10: @ We are aligned, we know we have at least 8 bytes to work with push {r4,r5,r6,r7} @@ -321,7 +321,7 @@ memchr: bic r4, r2, #7 @ Number of double words to work with * 8 mvns r7, #0 @ all F's movs r3, #0 - + 15: ldrd r5,r6,[r0],#8 subs r4, r4, #8 @@ -340,7 +340,7 @@ memchr: and r1,r1,#0xff @ r1 back to a single character and r2,r2,#7 @ Leave the count remaining as the number @ after the double words have been done - + 20: cbz r2, 40f @ 0 length or hit the end already then not found @@ -359,7 +359,7 @@ memchr: subs r0,r0,#1 @ found bx lr -60: @ We're here because the fast path found a hit +60: @ We're here because the fast path found a hit @ now we have to track down exactly which word it was @ r0 points to the start of the double word after the one tested @ r5 has the 00/ff pattern for the first word, r6 has the chained value diff --git a/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S b/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S index bff7aa1a74..2a6aae972a 100644 --- a/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S +++ b/libs/libc/machine/renesas/rx/gnu/arch_setjmp.S @@ -83,7 +83,7 @@ _setjmp: /* save return address */ mov.l r2, 0x24[r1] - + /* return 0 */ mov #0, r1 rts diff --git a/libs/libc/stdlib/Make.defs b/libs/libc/stdlib/Make.defs index 2484d9e05a..be2833c1d9 100644 --- a/libs/libc/stdlib/Make.defs +++ b/libs/libc/stdlib/Make.defs @@ -24,7 +24,7 @@ CSRCS += lib_abs.c lib_abort.c lib_atof.c lib_atoi.c lib_getprogname.c CSRCS += lib_atol.c lib_atoll.c lib_div.c lib_ldiv.c lib_lldiv.c lib_exit.c CSRCS += lib_itoa.c lib_labs.c lib_llabs.c lib_realpath.c lib_bsearch.c CSRCS += lib_rand.c lib_rand48.c lib_qsort.c lib_srand.c lib_strtol.c -CSRCS += lib_strtoll.c lib_strtoul.c lib_strtoull.c lib_strtold.c +CSRCS += lib_strtoll.c lib_strtoul.c lib_strtoull.c lib_strtold.c CSRCS += lib_checkbase.c lib_mktemp.c lib_mkstemp.c lib_mkdtemp.c CSRCS += lib_aligned_alloc.c lib_posix_memalign.c lib_valloc.c lib_mblen.c CSRCS += lib_mbtowc.c lib_wctomb.c lib_mbstowcs.c lib_wcstombs.c lib_atexit.c diff --git a/mm/README.txt b/mm/README.txt index 9f70f9747f..2fd08be1e5 100644 --- a/mm/README.txt +++ b/mm/README.txt @@ -101,7 +101,7 @@ This directory contains the NuttX memory management logic. This include: 2.Implement xxx_malloc, xxx_free, xxx_memcpy... in source code, you can: a.Modify some arguments(e.g. extend the allocation size for redzone) - d.Check the critical arguments(e.g. pointer and length) in the range + d.Check the critical arguments(e.g. pointer and length) in the range b.Forward to the original implementation(call malloc/free/memcpy) c.Attach the context info(e.g. file and line) before return diff --git a/net/bluetooth/Kconfig b/net/bluetooth/Kconfig index 768a6396da..57fa771f2b 100644 --- a/net/bluetooth/Kconfig +++ b/net/bluetooth/Kconfig @@ -27,7 +27,7 @@ config NET_BLUETOOTH_PREALLOC_CONNS default 4 ---help--- Number of Bluetooth connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -59,7 +59,7 @@ config NET_BLUETOOTH_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_BLUETOOTH_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/can/Kconfig b/net/can/Kconfig index 3f053e7f38..b24895fd14 100644 --- a/net/can/Kconfig +++ b/net/can/Kconfig @@ -35,7 +35,7 @@ config CAN_PREALLOC_CONNS default 4 ---help--- Number of CAN connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -67,7 +67,7 @@ config CAN_MAX_CONNS ---help--- If dynamic connections allocation is selected (CAN_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/icmp/Kconfig b/net/icmp/Kconfig index 5cee9de515..6c7dd55789 100644 --- a/net/icmp/Kconfig +++ b/net/icmp/Kconfig @@ -37,7 +37,7 @@ config NET_ICMP_PREALLOC_CONNS default 4 ---help--- Number of ICMP connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -69,7 +69,7 @@ config NET_ICMP_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_ICMP_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/icmpv6/Kconfig b/net/icmpv6/Kconfig index 471204b981..d7090e35b0 100644 --- a/net/icmpv6/Kconfig +++ b/net/icmpv6/Kconfig @@ -205,7 +205,7 @@ config NET_ICMPv6_PREALLOC_CONNS default 4 ---help--- Number of ICMPv6 connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -237,7 +237,7 @@ config NET_ICMPv6_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_ICMPv6_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/ieee802154/Kconfig b/net/ieee802154/Kconfig index 9cb0716556..77dfd5bfbf 100644 --- a/net/ieee802154/Kconfig +++ b/net/ieee802154/Kconfig @@ -38,7 +38,7 @@ config NET_IEEE802154_PREALLOC_CONNS default 4 ---help--- Number of IEEE 802.15.4 connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -70,7 +70,7 @@ config NET_IEEE802154_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_IEEE802154_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/netlink/Kconfig b/net/netlink/Kconfig index 0a07a04364..4963744d59 100644 --- a/net/netlink/Kconfig +++ b/net/netlink/Kconfig @@ -27,7 +27,7 @@ config NETLINK_PREALLOC_CONNS default 4 ---help--- Number of Netlink connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -59,7 +59,7 @@ config NETLINK_MAX_CONNS ---help--- If dynamic connections allocation is selected (NETLINK_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/pkt/Kconfig b/net/pkt/Kconfig index 282a9429a9..79c600085c 100644 --- a/net/pkt/Kconfig +++ b/net/pkt/Kconfig @@ -27,7 +27,7 @@ config NET_PKT_PREALLOC_CONNS default 1 ---help--- Number of packet connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -59,7 +59,7 @@ config NET_PKT_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_PKT_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/socket/Kconfig b/net/socket/Kconfig index 153ff79cf7..6877dc3d5f 100644 --- a/net/socket/Kconfig +++ b/net/socket/Kconfig @@ -11,7 +11,7 @@ config NET_PREALLOC_DEVIF_CALLBACKS default 4 if DEFAULT_SMALL ---help--- Number of preallocated socket callbacks (all tasks). - + This number of callbacks will be pre-allocated during system boot. If dynamic callbacks allocation is enabled, more callbacks may be allocated at a later time, as the system needs them. Else this diff --git a/net/tcp/Kconfig b/net/tcp/Kconfig index 900fea25b2..996f98ffad 100644 --- a/net/tcp/Kconfig +++ b/net/tcp/Kconfig @@ -55,7 +55,7 @@ config NET_TCP_PREALLOC_CONNS default 8 ---help--- Number of TCP/IP connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -87,7 +87,7 @@ config NET_TCP_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_TCP_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/udp/Kconfig b/net/udp/Kconfig index 9239367396..a0b48ee98d 100644 --- a/net/udp/Kconfig +++ b/net/udp/Kconfig @@ -41,7 +41,7 @@ config NET_UDP_PREALLOC_CONNS default 8 ---help--- Number of UDP connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -73,7 +73,7 @@ config NET_UDP_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_UDP_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/net/usrsock/Kconfig b/net/usrsock/Kconfig index f50a366721..1ce47e40fe 100644 --- a/net/usrsock/Kconfig +++ b/net/usrsock/Kconfig @@ -30,7 +30,7 @@ config NET_USRSOCK_PREALLOC_CONNS default 6 ---help--- Number of usrsock connections (all tasks). - + This number of connections will be pre-allocated during system boot. If dynamic connections allocation is enabled, more connections may be allocated at a later time, as the system needs them. Else this @@ -65,7 +65,7 @@ config NET_USRSOCK_MAX_CONNS ---help--- If dynamic connections allocation is selected (NET_USRSOCK_ALLOC_CONNS > 0) this will limit the number of connections that can be allocated. - + This is useful in case the system is under very heavy load (or under attack), ensuring that the heap will not be exhausted. diff --git a/tools/ci/docker/linux/Dockerfile b/tools/ci/docker/linux/Dockerfile index a70ecc8d0c..925b57f7fd 100644 --- a/tools/ci/docker/linux/Dockerfile +++ b/tools/ci/docker/linux/Dockerfile @@ -140,7 +140,7 @@ RUN cd renesas-tools/source/binutils && \ chmod +x ./configure ./mkinstalldirs && \ mkdir -p /tools/renesas-tools/build/binutils && cd /tools/renesas-tools/build/binutils && \ /tools/renesas-tools/source/binutils/configure --target=rx-elf --prefix=/tools/renesas-toolchain/rx-elf-gcc --disable-werror &&\ - make && make install + make && make install ENV PATH="/tools/renesas-toolchain/rx-elf-gcc/bin:$PATH" # Install gcc @@ -153,14 +153,14 @@ RUN cd renesas-tools/source/gcc && \ /tools/renesas-tools/source/gcc/configure --target=rx-elf --prefix=/tools/renesas-toolchain/rx-elf-gcc \ --disable-shared --disable-multilib --disable-libssp --disable-libstdcxx-pch --disable-werror --enable-lto \ --enable-gold --with-pkgversion=GCC_Build_1.02 --with-newlib --enable-languages=c && \ - make && make install + make && make install ENV PATH="/tools/renesas-toolchain/rx-elf-gcc/bin:$PATH" # Install newlib RUN cd renesas-tools/source/newlib && \ chmod +x ./configure && \ mkdir -p /tools/renesas-tools/build/newlib && cd /tools/renesas-tools/build/newlib && \ - /tools/renesas-tools/source/newlib/configure --target=rx-elf --prefix=/tools/renesas-toolchain/rx-elf-gcc && \ + /tools/renesas-tools/source/newlib/configure --target=rx-elf --prefix=/tools/renesas-toolchain/rx-elf-gcc && \ make && make install RUN cd /tools/renesas-tools/build/gcc && \ make && make install diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 4806d07ff6..71f81d857a 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -37,7 +37,7 @@ /x86_64/intel64/qemu-intel64/configs/nsh -# The gcc 11.2 toolcain for MACOS maybe fail when compile +# The gcc 11.2 toolcain for MACOS maybe fail when compile # with float, disable the cibuild check for MACOS # it will be enbaled while new toolchain release diff --git a/tools/configure.bat b/tools/configure.bat index 5f40aa7b9a..d62983693b 100755 --- a/tools/configure.bat +++ b/tools/configure.bat @@ -8,9 +8,9 @@ rem this work for additional information regarding copyright ownership. The rem ASF licenses this file to you under the Apache License, Version 2.0 (the rem "License"); you may not use this file except in compliance with the rem License. You may obtain a copy of the License at -rem +rem rem http://www.apache.org/licenses/LICENSE-2.0 -rem +rem rem Unless required by applicable law or agreed to in writing, software rem distributed under the License is distributed on an "AS IS" BASIS, WITHOUT rem WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the diff --git a/tools/licensing/README.md b/tools/licensing/README.md index 76066b6a9e..977718d0b3 100644 --- a/tools/licensing/README.md +++ b/tools/licensing/README.md @@ -17,7 +17,7 @@ Steps 2 and 3 are based on heuristics. The attributions may not match the regula used so there may be misdetections. Authors on headers are easier to detect. In fact, this will pick up various false positives (non-author strings) which will have to be ignored by the user. -All of these authorship information is aggregated and in a final step, the names are used +All of these authorship information is aggregated and in a final step, the names are used to check for ICLAs, based on the ICLA databases (see below), which need to be manually downloaded. If a given author name is not matched, their email searched for in the `author_mappings.json` file, which is a dictionary of email to real name. This allows to handle users with alternative email diff --git a/tools/licensing/log2json.sh b/tools/licensing/log2json.sh index 81a28b7fa5..7236d152da 100755 --- a/tools/licensing/log2json.sh +++ b/tools/licensing/log2json.sh @@ -19,8 +19,8 @@ # ############################################################################ -# We define a replacement for the quote character (") -# since we cannot escape quote characters found inside +# We define a replacement for the quote character (") +# since we cannot escape quote characters found inside # the commit message Q='^@^' @@ -30,7 +30,7 @@ function getlog (echo -n '[' git --no-pager log --follow --simplify-merges \ --pretty=format:'{ '$Q'commit'$Q': '$Q'%H'$Q', '$Q'author'$Q': '$Q'%aN'$Q', '$Q'author-email'$Q': '$Q'%aE'$Q', '$Q'date'$Q': '$Q'%ad'$Q', '$Q'committer'$Q': '$Q'%cn'$Q', '$Q'committer-email'$Q': '$Q'%ce'$Q', '$Q'message'$Q': '$Q'%s'$Q', '$Q'body'$Q': '$Q'%b'$Q', '$Q'signed'$Q': '$Q'%G?'$Q', '$Q'signer'$Q': '$Q'%GS'$Q', '$Q'key'$Q': '$Q'%GK'$Q' },' -- "$1" - echo -n ']') | + echo -n ']') | sed -r 's|\\|\\\\|g' | # escape backquotes sed -r 's|"|\\"|g' | # replace quotes with escaped quotes tr '\r\n' ' ' | # replace newlines with spaces (otherwise strings) are broken diff --git a/tools/lwl/README.txt b/tools/lwl/README.txt index d1bfe09a22..8a6fbce227 100644 --- a/tools/lwl/README.txt +++ b/tools/lwl/README.txt @@ -79,15 +79,15 @@ Info : stm32f4x.cpu: hardware has 6 breakpoints, 4 watchpoints Info : Listening on port 3333 for gdb connections Info : accepting 'tcl' connection on tcp/6666 invalid command name "ocd_mdw" -0x20000000: 000000ff +0x20000000: 000000ff -0x20000000: 000000ff +0x20000000: 000000ff -0x20000004: 7216a318 +0x20000004: 7216a318 -0x2000000c: 994b5b1b +0x2000000c: 994b5b1b -0x2000000c: 994b5b1b +0x2000000c: 994b5b1b 0x2000000c: 994b5b1b ... diff --git a/tools/testbuild.sh b/tools/testbuild.sh index 0c18646217..0133d72f7d 100755 --- a/tools/testbuild.sh +++ b/tools/testbuild.sh @@ -220,7 +220,7 @@ function compressartifacts { pushd $target_path >/dev/null tar zcf ${target_name}.tar.gz ${target_name} - rm -rf ${target_name} + rm -rf ${target_name} popd >/dev/null }