diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 2b02b5e345..1049479892 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -54,6 +54,7 @@
 #include <nuttx/irq.h>
 #include <nuttx/wdog.h>
 #include <nuttx/wqueue.h>
+#include <nuttx/net/phy.h>
 #include <nuttx/net/mii.h>
 #include <nuttx/net/arp.h>
 #include <nuttx/net/netdev.h>
@@ -189,6 +190,40 @@
 #  endif
 #endif
 
+/* These definitions are used to enable the PHY interrupts */
+
+#if defined( CONFIG_ETH0_PHY_AM79C874)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_KS8721)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_KSZ8041)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_KSZ8051)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_KSZ8061)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_KSZ8081)
+#  define MII_INT_REG    MII_KSZ8081_INT
+#  define MII_INT_SETEN  MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN
+#  define MII_INT_CLREN  0
+#elif defined( CONFIG_ETH0_PHY_KSZ90x1)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_DP83848C)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_LAN8720)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_LAN8740)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_LAN8740A)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_LAN8742A)
+#  error missing logic
+#elif defined( CONFIG_ETH0_PHY_DM9161)
+#  error missing logic
+#else
+#  error unknown PHY
+#endif
+
 #ifdef CONFIG_STM32_ETH_PTP
 #  warning "CONFIG_STM32_ETH_PTP is not yet supported"
 #endif
@@ -2889,8 +2924,19 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
 #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
 static int stm32_phyintenable(struct stm32_ethmac_s *priv)
 {
-#warning Missing logic
-  return -ENOSYS;
+  uint16_t phyval;
+  int ret;
+
+  ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_INT_REG, &phyval);
+  if (ret == OK)
+    {
+      /* Enable link up/down interrupts */
+
+      ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG,
+                           (phyval & ~MII_INT_CLREN) | MII_INT_SETEN);
+    }
+
+  return 0;
 }
 #endif