Xtensa: Remove 'virtual' interrupt support
This commit is contained in:
Gregory Nutt
parent
23b003c649
commit
2c83d79465
@ -129,8 +129,8 @@
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#ifdef CONFIG_XTENSA_USE_OVLY
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/* Storage for overlay state */
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# define REG_OVLY (_REG_OVLY_START + 0)
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# define XCPTCONTEXT_REGS (_REG_OVLY_START + 1)
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# error Overlays not supported
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# define XCPTCONTEXT_REGS _REG_OVLY_START
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#else
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# define XCPTCONTEXT_REGS _REG_OVLY_START
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#endif
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@ -294,7 +294,7 @@ _xtensa_level2_handler:
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rsr a0, EXCSAVE_2 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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/* Save rest of interrupt context and enter RTOS. */
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/* Save rest of interrupt context. */
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s32i a2, sp, (4 * REG_A2)
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movi a2, sp /* Address of state save on stack */
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@ -1,150 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_irq.S
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Cadence Design Systems Inc.
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*
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* Copyright (c) 2006-2015 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************************/
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.file "xtensa_irq.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "xtensa_specregs.h"
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#include "xtensa_macros.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
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/* INTENABLE virtualization information. */
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.data
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.global _xtensa_intdata
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.align 8
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_xtensa_intdata:
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.global _xtensa_intenable
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.type _xtensa_intenable, @object
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_xtensa_intenable:
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.word 0 /* Virtual INTENABLE */
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.size _xtensa_intenable,4
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.global _xtensa_vprimask
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.type _xtensa_vprimask, @object
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_xtensa_vprimask:
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.word 0xffffffff /* Virtual priority mask */
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.size _xtensa_vprimask, 4
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#endif /* CONFIG_XCHAL_HAVE_INTERRUPTS */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* C Prototype:
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* irqstate_t xtensa_enable_interrupts(irqstate_t mask)
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*
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* Description:
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* Enables a set of interrupts. Does not simply set INTENABLE directly,
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* but computes it as a function of the current virtual priority.
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* Can be called from interrupt handlers.
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*
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****************************************************************************/
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.text
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.align 4
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.global xtensa_enable_interrupts
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.type xtensa_enable_interrupts, @function
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xtensa_enable_interrupts:
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ENTRY0
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#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xtensa_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xtensa_intenable */
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l32i a6, a4, 4 /* a6 = _xtensa_vprimask */
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or a5, a3, a2 /* a5 = _xtensa_intenable | mask */
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s32i a5, a4, 0 /* _xtensa_intenable |= mask */
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and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* Return zero */
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#endif
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RET0
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.size xtensa_enable_interrupts, . - xtensa_enable_interrupts
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/****************************************************************************
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* C Prototype:
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* irqstate_t xtensa_disable_interrupts(irqstate_t mask)
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*
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* Description:
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* Disables a set of interrupts. Does not simply set INTENABLE directly,
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* but computes it as a function of the current virtual priority.
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* Can be called from interrupt handlers.
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*
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****************************************************************************/
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.text
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.align 4
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.global xtensa_disable_interrupts
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.type xtensa_disable_interrupts,@function
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xtensa_disable_interrupts:
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ENTRY0
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#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
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movi a3, 0
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movi a4, _xtensa_intdata
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xsr a3, INTENABLE /* Disables all interrupts */
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rsync
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l32i a3, a4, 0 /* a3 = _xtensa_intenable */
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l32i a6, a4, 4 /* a6 = _xtensa_vprimask */
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or a5, a3, a2 /* a5 = _xtensa_intenable | mask */
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xor a5, a5, a2 /* a5 = _xtensa_intenable & ~mask */
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s32i a5, a4, 0 /* _xtensa_intenable &= ~mask */
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and a5, a5, a6 /* a5 = _xtensa_intenable & _xtensa_vprimask */
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wsr a5, INTENABLE /* Reenable interrupts */
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mov a2, a3 /* Previous mask */
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#else
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movi a2, 0 /* return zero */
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#endif
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RET0
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.size xtensa_disable_interrupts, . - xtensa_disable_interrupts
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@ -40,7 +40,7 @@ HEAD_CSRC = esp32_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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CMN_ASRCS = xtensa_context.S xtensa_irq.S xtensa_intvectors.S
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CMN_ASRCS = xtensa_context.S xtensa_intvectors.S
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CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
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CMN_CSRCS += xtensa_createstack.c xtensa_exit.c xtensa_idle.c
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CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c
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@ -308,7 +308,7 @@
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* 3 1 extern level TG0_WDT Reserved
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* 4 1 extern level WBB
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* 5 1 extern level BT Controller
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* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
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* 6 1 timer RTOS Tick RTOS Tick
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* 7 1 software Reserved Reserved
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* 8 1 extern level BLE Controller
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* 9 1 extern level
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@ -317,7 +317,7 @@
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* 12 1 extern level
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* 13 1 extern level
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* 14 7 nmi Reserved Reserved
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* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
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* 15 3 timer Internal Timer
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* 16 5 timer
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* 17 1 extern level
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* 18 1 extern level
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