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Merged in raiden00/nuttx_h7 (pull request #837)

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Initial OTG support for STM32H7 and some minor improvements

arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: add support for HSI48 clock

configs/nucleo-f207zg: add support for USB and initialize CDCACM if configured

configs/nucleo-h743zi: add support for USB and initialize CDCACM if configured

drivers/usbdev/Kconfig: fix type for USBDEV_TRACE_INITIALIDSET

configs/teensy-3.x/usbnsh/defconfig: update config according to change in USBDEV_TRACE_INITIALIDSET

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl 2019-03-10 13:24:58 +00:00 committed by Gregory Nutt
parent ffca6badfc
commit 2caf135d05
25 changed files with 13514 additions and 152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
arch/arm/src/stm32h7/Kconfig
View File

@ -161,6 +161,40 @@ config STM32H7_BDMA
select STM32H7_DMA
select ARCH_DMA
config STM32H7_OTGFS
bool "OTG FS"
default n
select USBHOST_HAVE_ASYNCH if USBHOST
config STM32H7_OTGHS
bool "OTG HS"
default n
depends on EXPERIMENTAL
select USBHOST_HAVE_ASYNCH if USBHOST
config STM32H7_OTG_SOFOUTPUT
bool "OTG SOF output"
default n
config STM32H7_OTG_USBREGEN
bool "Enable USB voltage regulator"
default n
config STM32H7_USBDEV_REGDEBUG
bool "OTG USBDEV REGDEBUG"
default n
depends on USBDEV
config STM32H7_USBHOST_REGDEBUG
bool "OTG USBHOST REGDEBUG"
default n
depends on USBHOST
config STM32H7_USBHOST_PKTDUMP
bool "OTG USBHOST PKTDUMP"
default n
depends on USBHOST
menu "STM32H7 I2C Selection"
config STM32H7_I2C1
@ -229,6 +263,10 @@ config STM32H7_SPI6
select SPI
select STM32H7_SPI
config STM32H7_SYSCFG
bool "SYSCFG"
default y
endmenu # STM32H7 SPI Selection
menu "STM32H7 U[S]ART Selection"

8
arch/arm/src/stm32h7/Make.defs
View File

@ -125,3 +125,11 @@ endif
ifeq ($(CONFIG_STM32H7_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += stm32_otgdev.c
endif
ifeq ($(CONFIG_USBHOST),y)
CHIP_CSRCS += stm32_otghost.c
endif

932
arch/arm/src/stm32h7/chip/stm32_otg.h Normal file
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@ -0,0 +1,932 @@
/************************************************************************************
* arch/arm/src/stm32h7/chip/stm32_otg.h
* based on stm32f7/chip/stm32_otg.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* General definitions */
#define OTG_EPTYPE_CTRL (0) /* Control */
#define OTG_EPTYPE_ISOC (1) /* Isochronous */
#define OTG_EPTYPE_BULK (2) /* Bulk */
#define OTG_EPTYPE_INTR (3) /* Interrupt */
#define OTG_PID_DATA0 (0)
#define OTG_PID_DATA2 (1)
#define OTG_PID_DATA1 (2)
#define OTG_PID_MDATA (3) /* Non-control */
#define OTG_PID_SETUP (3) /* Control */
/* Register Offsets ****************************************************************/
/* Core global control and status registers */
#define STM32_OTG_GOTGCTL_OFFSET 0x0000 /* Control and status register */
#define STM32_OTG_GOTGINT_OFFSET 0x0004 /* Interrupt register */
#define STM32_OTG_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */
#define STM32_OTG_GUSBCFG_OFFSET 0x000c /* USB configuration register */
#define STM32_OTG_GRSTCTL_OFFSET 0x0010 /* Reset register */
#define STM32_OTG_GINTSTS_OFFSET 0x0014 /* Core interrupt register */
#define STM32_OTG_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */
#define STM32_OTG_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */
#define STM32_OTG_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */
#define STM32_OTG_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */
#define STM32_OTG_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */
#define STM32_OTG_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */
#define STM32_OTG_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */
#define STM32_OTG_GCCFG_OFFSET 0x0038 /* General core configuration register */
#define STM32_OTG_CID_OFFSET 0x003c /* Core ID register */
#define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
#define STM32_OTG_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2))
/* Host-mode control and status registers */
#define STM32_OTG_HCFG_OFFSET 0x0400 /* Host configuration register */
#define STM32_OTG_HFIR_OFFSET 0x0404 /* Host frame interval register */
#define STM32_OTG_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */
#define STM32_OTG_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */
#define STM32_OTG_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */
#define STM32_OTG_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */
#define STM32_OTG_HPRT_OFFSET 0x0440 /* Host port control and status register */
#define STM32_OTG_CHAN_OFFSET(n) (0x500 + ((n) << 5)
#define STM32_OTG_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */
#define STM32_OTG_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */
#define STM32_OTG_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */
#define STM32_OTG_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
#define STM32_OTG_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
#define STM32_OTG_HCINT_OFFSET(n) (0x508 + ((n) << 5))
#define STM32_OTG_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
#define STM32_OTG_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
/* Device-mode control and status registers */
#define STM32_OTG_DCFG_OFFSET 0x0800 /* Device configuration register */
#define STM32_OTG_DCTL_OFFSET 0x0804 /* Device control register */
#define STM32_OTG_DSTS_OFFSET 0x0808 /* Device status register */
#define STM32_OTG_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */
#define STM32_OTG_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */
#define STM32_OTG_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */
#define STM32_OTG_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */
#define STM32_OTG_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */
#define STM32_OTG_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */
#define STM32_OTG_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */
#define STM32_OTG_DIEP_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTG_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */
#define STM32_OTG_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */
#define STM32_OTG_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */
#define STM32_OTG_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
#define STM32_OTG_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
#define STM32_OTG_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
#define STM32_OTG_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
#define STM32_OTG_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
#define STM32_OTG_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTG_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
#define STM32_OTG_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
#define STM32_OTG_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
#define STM32_OTG_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
#define STM32_OTG_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
/* Power and clock gating registers */
#define STM32_OTG_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */
/* Data FIFO (DFIFO) access registers */
#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
/* Register Addresses **************************************************************/
#define STM32_OTG_GOTGCTL (STM32_OTG_BASE+STM32_OTG_GOTGCTL_OFFSET)
#define STM32_OTG_GOTGINT (STM32_OTG_BASE+STM32_OTG_GOTGINT_OFFSET)
#define STM32_OTG_GAHBCFG (STM32_OTG_BASE+STM32_OTG_GAHBCFG_OFFSET)
#define STM32_OTG_GUSBCFG (STM32_OTG_BASE+STM32_OTG_GUSBCFG_OFFSET)
#define STM32_OTG_GRSTCTL (STM32_OTG_BASE+STM32_OTG_GRSTCTL_OFFSET)
#define STM32_OTG_GINTSTS (STM32_OTG_BASE+STM32_OTG_GINTSTS_OFFSET)
#define STM32_OTG_GINTMSK (STM32_OTG_BASE+STM32_OTG_GINTMSK_OFFSET)
#define STM32_OTG_GRXSTSR (STM32_OTG_BASE+STM32_OTG_GRXSTSR_OFFSET)
#define STM32_OTG_GRXSTSP (STM32_OTG_BASE+STM32_OTG_GRXSTSP_OFFSET)
#define STM32_OTG_GRXFSIZ (STM32_OTG_BASE+STM32_OTG_GRXFSIZ_OFFSET)
#define STM32_OTG_HNPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HNPTXFSIZ_OFFSET)
#define STM32_OTG_DIEPTXF0 (STM32_OTG_BASE+STM32_OTG_DIEPTXF0_OFFSET)
#define STM32_OTG_HNPTXSTS (STM32_OTG_BASE+STM32_OTG_HNPTXSTS_OFFSET)
#define STM32_OTG_GCCFG (STM32_OTG_BASE+STM32_OTG_GCCFG_OFFSET)
#define STM32_OTG_CID (STM32_OTG_BASE+STM32_OTG_CID_OFFSET)
#define STM32_OTG_HPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HPTXFSIZ_OFFSET)
#define STM32_OTG_DIEPTXF(n) (STM32_OTG_BASE+STM32_OTG_DIEPTXF_OFFSET(n))
/* Host-mode control and status registers */
#define STM32_OTG_HCFG (STM32_OTG_BASE+STM32_OTG_HCFG_OFFSET)
#define STM32_OTG_HFIR (STM32_OTG_BASE+STM32_OTG_HFIR_OFFSET)
#define STM32_OTG_HFNUM (STM32_OTG_BASE+STM32_OTG_HFNUM_OFFSET)
#define STM32_OTG_HPTXSTS (STM32_OTG_BASE+STM32_OTG_HPTXSTS_OFFSET)
#define STM32_OTG_HAINT (STM32_OTG_BASE+STM32_OTG_HAINT_OFFSET)
#define STM32_OTG_HAINTMSK (STM32_OTG_BASE+STM32_OTG_HAINTMSK_OFFSET)
#define STM32_OTG_HPRT (STM32_OTG_BASE+STM32_OTG_HPRT_OFFSET)
#define STM32_OTG_CHAN(n) (STM32_OTG_BASE+STM32_OTG_CHAN_OFFSET(n))
#define STM32_OTG_HCCHAR(n) (STM32_OTG_BASE+STM32_OTG_HCCHAR_OFFSET(n))
#define STM32_OTG_HCINT(n) (STM32_OTG_BASE+STM32_OTG_HCINT_OFFSET(n))
#define STM32_OTG_HCINTMSK(n) (STM32_OTG_BASE+STM32_OTG_HCINTMSK_OFFSET(n))
#define STM32_OTG_HCTSIZ(n) (STM32_OTG_BASE+STM32_OTG_HCTSIZ_OFFSET(n))
/* Device-mode control and status registers */
#define STM32_OTG_DCFG (STM32_OTG_BASE+STM32_OTG_DCFG_OFFSET)
#define STM32_OTG_DCTL (STM32_OTG_BASE+STM32_OTG_DCTL_OFFSET)
#define STM32_OTG_DSTS (STM32_OTG_BASE+STM32_OTG_DSTS_OFFSET)
#define STM32_OTG_DIEPMSK (STM32_OTG_BASE+STM32_OTG_DIEPMSK_OFFSET)
#define STM32_OTG_DOEPMSK (STM32_OTG_BASE+STM32_OTG_DOEPMSK_OFFSET)
#define STM32_OTG_DAINT (STM32_OTG_BASE+STM32_OTG_DAINT_OFFSET)
#define STM32_OTG_DAINTMSK (STM32_OTG_BASE+STM32_OTG_DAINTMSK_OFFSET)
#define STM32_OTG_DVBUSDIS (STM32_OTG_BASE+STM32_OTG_DVBUSDIS_OFFSET)
#define STM32_OTG_DVBUSPULSE (STM32_OTG_BASE+STM32_OTG_DVBUSPULSE_OFFSET)
#define STM32_OTG_DIEPEMPMSK (STM32_OTG_BASE+STM32_OTG_DIEPEMPMSK_OFFSET)
#define STM32_OTG_DIEP(n) (STM32_OTG_BASE+STM32_OTG_DIEP_OFFSET(n))
#define STM32_OTG_DIEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DIEPCTL_OFFSET(n))
#define STM32_OTG_DIEPINT(n) (STM32_OTG_BASE+STM32_OTG_DIEPINT_OFFSET(n))
#define STM32_OTG_DIEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ_OFFSET(n))
#define STM32_OTG_DTXFSTS(n) (STM32_OTG_BASE+STM32_OTG_DTXFSTS_OFFSET(n))
#define STM32_OTG_DOEP(n) (STM32_OTG_BASE+STM32_OTG_DOEP_OFFSET(n))
#define STM32_OTG_DOEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DOEPCTL_OFFSET(n))
#define STM32_OTG_DOEPINT(n) (STM32_OTG_BASE+STM32_OTG_DOEPINT_OFFSET(n))
#define STM32_OTG_DOEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ_OFFSET(n))
/* Power and clock gating registers */
#define STM32_OTG_PCGCCTL (STM32_OTG_BASE+STM32_OTG_PCGCCTL_OFFSET)
/* Data FIFO (DFIFO) access registers */
#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
/* Register Bitfield Definitions ***************************************************/
/* Core global control and status registers */
/* Control and status register */
#define OTG_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */
#define OTG_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */
#define OTG_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */
#define OTG_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */
#define OTG_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */
#define OTG_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */
#define OTG_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */
#define OTG_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */
#define OTG_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */
#define OTG_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */
#define OTG_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */
#define OTG_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */
#define OTG_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */
/* Bits 13-15: Reserved */
#define OTG_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */
#define OTG_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */
#define OTG_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */
#define OTG_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */
#define OTG_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */
/* Bits 21-31: Reserved */
/* Interrupt register */
/* Bits 1-0 Reserved */
#define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */
/* Bits 3-7: Reserved */
#define OTG_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */
#define OTG_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */
/* Bits 16-10 Reserved */
#define OTG_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */
#define OTG_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */
#define OTG_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */
#define OTG_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */
/* Bits 21-31: Reserved */
/* AHB configuration register */
#define OTG_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */
#define OTG_GAHBCFG_HBSTLEN_SHIFT (1) /* Bits 1-4: Bust length/type */
# define OTG_GAHBCFG_HBSTLEN_MASK (0xf << OTG_GAHBCFG_HBSTLEN_SHIFT)
#define OTG_GAHBCFG_DMAEN (1 << 5) /* Bit 5: DMA enable */
/* Bit 6: Reserved */
#define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */
#define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */
/* Bits 20-31: Reserved */
/* USB configuration register */
#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
#define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT)
/* Bits 3-5: Reserved */
#define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */
/* Bit 7: Reserved */
#define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */
#define OTG_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */
#define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */
#define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT)
# define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT)
/* Bit 14: Reserved */
#define OTG_GUSBCFG_PHYLPC (1 << 15) /* Bit 15: PHY low-power clock select */
/* Bit 16: Reserved */
#define OTG_GUSBCFG_ULPIFSL (1 << 17) /* Bit 17: ULPI FS/LS select */
#define OTG_GUSBCFG_ULPIAR (1 << 18) /* Bit 18: ULPI Auto-resume */
#define OTG_GUSBCFG_ULPICSM (1 << 19) /* Bit 19: ULPI clock SuspendM */
#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20) /* Bit 20: ULPI external VBUS drive */
#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21) /* Bit 21: ULPI external VBUS indicator */
#define OTG_GUSBCFG_TSPDS (1 << 22) /* Bit 22: TermSel DLine pulsing selection */
#define OTG_GUSBCFG_PCCI (1 << 23) /* Bit 23: Indicator complement */
#define OTG_GUSBCFG_PTCI (1 << 24) /* Bit 24: Indicator pass through */
#define OTG_GUSBCFG_ULPIIPD (1 << 25) /* Bit 25: ULPI interface protect disable */
#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
/* Bit 31: Reserved */
/* Reset register */
#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */
#define OTG_GRSTCTL_PSRST (1 << 1) /* Bit 1: Partial soft reset */
/* Bits 2-3 Reserved */
#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */
#define OTG_GRSTCTL_TXFNUM_MASK (31 << OTG_GRSTCTL_TXFNUM_SHIFT)
# define OTG_GRSTCTL_TXFNUM_HNONPER (0 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */
# define OTG_GRSTCTL_TXFNUM_HPER (1 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */
# define OTG_GRSTCTL_TXFNUM_HALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/
# define OTG_GRSTCTL_TXFNUM_D(n) ((n) << OTG_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */
# define OTG_GRSTCTL_TXFNUM_DALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/
/* Bits 11-29: Reserved */
#define OTG_GRSTCTL_DMAREQ (1 << 30) /* Bit 30: DMA request signal enabled */
#define OTG_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */
/* Core interrupt and Interrupt mask registers */
#define OTG_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */
# define OTG_GINTSTS_DEVMODE (0)
# define OTG_GINTSTS_HOSTMODE (OTG_GINTSTS_CMOD)
#define OTG_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */
#define OTG_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */
#define OTG_GINT_SOF (1 << 3) /* Bit 3: Start of frame */
#define OTG_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */
#define OTG_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */
#define OTG_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */
#define OTG_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */
/* Bits 8-9: Reserved */
#define OTG_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */
#define OTG_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */
#define OTG_GINT_USBRST (1 << 12) /* Bit 12: USB reset */
#define OTG_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */
#define OTG_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */
#define OTG_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */
/* Bits 16-17 Reserved */
#define OTG_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */
#define OTG_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */
#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
#define OTG_GINT_DATAFSUSP (1 << 22) /* Bit 22: Data fetch sispended */
#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */
#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */
#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */
#define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */
#define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */
#define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */
#define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */
#define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */
#define OTG_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */
#define OTG_GINT_RESERVED ((1 << 8) | (1 << 9) | (1 << 16) | (1 << 17))
/* Receive status debug read/OTG status read and pop registers (host mode) */
#define OTG_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */
#define OTG_GRXSTSH_CHNUM_MASK (15 << OTG_GRXSTSH_CHNUM_SHIFT)
#define OTG_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSH_BCNT_MASK (0x7ff << OTG_GRXSTSH_BCNT_SHIFT)
#define OTG_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSH_DPID_MASK (3 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA0 (0 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA2 (1 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA1 (2 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_MDATA (3 << OTG_GRXSTSH_DPID_SHIFT)
#define OTG_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSH_PKTSTS_MASK (15 << OTG_GRXSTSH_PKTSTS_SHIFT)
# define OTG_GRXSTSH_PKTSTS_INRECVD (2 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */
# define OTG_GRXSTSH_PKTSTS_INDONE (3 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
# define OTG_GRXSTSH_PKTSTS_DTOGERR (5 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
# define OTG_GRXSTSH_PKTSTS_HALTED (7 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
/* Bits 21-31: Reserved */
/* Receive status debug read/OTG status read and pop registers (device mode) */
#define OTG_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
#define OTG_GRXSTSD_EPNUM_MASK (15 << OTG_GRXSTSD_EPNUM_SHIFT)
#define OTG_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSD_BCNT_MASK (0x7ff << OTG_GRXSTSD_BCNT_SHIFT)
#define OTG_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSD_DPID_MASK (3 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA0 (0 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA2 (1 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA1 (2 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_MDATA (3 << OTG_GRXSTSD_DPID_SHIFT)
#define OTG_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSD_PKTSTS_MASK (15 << OTG_GRXSTSD_PKTSTS_SHIFT)
# define OTG_GRXSTSD_PKTSTS_OUTNAK (1 << OTG_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */
# define OTG_GRXSTSD_PKTSTS_OUTRECVD (2 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */
# define OTG_GRXSTSD_PKTSTS_OUTDONE (3 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */
# define OTG_GRXSTSD_PKTSTS_SETUPDONE (4 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */
# define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-26: Reserved */
#define OTG_GRXSTSH_STSPHST (17) /* Bit 27: Status phase start */
/* Bits 28-31: Reserved */
/* Receive FIFO size register */
#define OTG_GRXFSIZ_MASK (0xffff)
/* Host non-periodic transmit FIFO size register */
#define OTG_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */
#define OTG_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFSA_SHIFT)
#define OTG_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */
#define OTG_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFD_SHIFT)
# define OTG_HNPTXFSIZ_NPTXFD_MIN (16 << OTG_HNPTXFSIZ_NPTXFD_SHIFT)
# define OTG_HNPTXFSIZ_NPTXFD_MAX (256 << OTG_HNPTXFSIZ_NPTXFD_SHIFT)
/* Endpoint 0 Transmit FIFO size */
#define OTG_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */
#define OTG_DIEPTXF0_TX0FD_MASK (0xffff << OTG_DIEPTXF0_TX0FD_SHIFT)
#define OTG_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */
#define OTG_DIEPTXF0_TX0FSA_MASK (0xffff << OTG_DIEPTXF0_TX0FSA_SHIFT)
# define OTG_DIEPTXF0_TX0FSA_MIN (16 << OTG_DIEPTXF0_TX0FSA_SHIFT)
# define OTG_DIEPTXF0_TX0FSA_MAX (256 << OTG_DIEPTXF0_TX0FSA_SHIFT)
/* Non-periodic transmit FIFO/queue status register */
#define OTG_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */
#define OTG_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTG_HNPTXSTS_NPTXFSAV_SHIFT)
# define OTG_HNPTXSTS_NPTXFSAV_FULL (0 << OTG_HNPTXSTS_NPTXFSAV_SHIFT)
#define OTG_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */
#define OTG_HNPTXSTS_NPTQXSAV_MASK (0xff << OTG_HNPTXSTS_NPTQXSAV_SHIFT)
# define OTG_HNPTXSTS_NPTQXSAV_FULL (0 << OTG_HNPTXSTS_NPTQXSAV_SHIFT)
#define OTG_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
#define OTG_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTG_HNPTXSTS_NPTXQTOP_SHIFT)
# define OTG_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
# define OTG_HNPTXSTS_TYPE_MASK (3 << OTG_HNPTXSTS_TYPE_SHIFT)
# define OTG_HNPTXSTS_TYPE_INOUT (0 << OTG_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTG_HNPTXSTS_TYPE_ZLP (1 << OTG_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
# define OTG_HNPTXSTS_TYPE_HALT (3 << OTG_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
# define OTG_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT)
# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT)
/* Bit 31 Reserved */
/* General core configuration register */
#define OTG_GCCFG_DCDET (1 << 0) /* Bit 0: Data contact detection (DCD) status */
#define OTG_GCCFG_PDET (1 << 1) /* Bit 1: Primary detection (PD) status */
#define OTG_GCCFG_SDET (1 << 2) /* Bit 2: Secondary detection (SD) status */
#define OTG_GCCFG_PS2DET (1 << 3) /* Bit 3: DM pull-up detection status */
/* Bits 4-15: Reserved */
#define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */
#define OTG_GCCFG_BCDEN (1 << 17) /* Bit 17: Battery charging detector (BCD) enable */
#define OTG_GCCFG_DCDEN (1 << 18) /* Bit 18: Data contact detection (DCD) mode enable */
#define OTG_GCCFG_PDEN (1 << 19) /* Bit 19: Primary detection (PD) mode enable */
#define OTG_GCCFG_SDEN (1 << 20) /* Bit 20: Secondary detection (SD) mode enable */
#define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */
/* Bits 22-31: Reserved */
/* TODO: OTG core LPM configuration register */
/* Host periodic transmit FIFO size register */
#define OTG_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */
#define OTG_HPTXFSIZ_PTXSA_MASK (0xffff << OTG_HPTXFSIZ_PTXSA_SHIFT)
#define OTG_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */
#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff << OTG_HPTXFSIZ_PTXFD_SHIFT)
/* Device IN endpoint transmit FIFOn size register */
#define OTG_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */
#define OTG_DIEPTXF_INEPTXSA_MASK (0xffff << OTG_DIEPTXF_INEPTXSA_SHIFT)
#define OTG_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */
#define OTG_DIEPTXF_INEPTXFD_MASK (0xffff << OTG_DIEPTXF_INEPTXFD_SHIFT)
# define OTG_DIEPTXF_INEPTXFD_MIN (16 << OTG_DIEPTXF_INEPTXFD_MASK)
/* Host-mode control and status registers */
/* Host configuration register */
#define OTG_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
#define OTG_HCFG_FSLSPCS_MASK (3 << OTG_HCFG_FSLSPCS_SHIFT)
# define OTG_HCFG_FSLSPCS_FS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
# define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
# define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
/* Bits 31:3 Reserved */
/* Host frame interval register */
#define OTG_HFIR_SHIFT (0) /* Bits 0-16: Frame interval */
#define OTG_HFIR_MASK (0xffff << OTG_HFIR_SHIFT)
#define OTG_HFIR_RLDCTRL (1 << 16) /* Bit 16: Reload control */
/* Bits 17-31: Reserved */
/* Host frame number/frame time remaining register */
#define OTG_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */
#define OTG_HFNUM_FRNUM_MASK (0xffff << OTG_HFNUM_FRNUM_SHIFT)
#define OTG_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */
#define OTG_HFNUM_FTREM_MASK (0xffff << OTG_HFNUM_FTREM_SHIFT)
/* Host periodic transmit FIFO/queue status register */
#define OTG_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
#define OTG_HPTXSTS_PTXFSAVL_MASK (0xffff << OTG_HPTXSTS_PTXFSAVL_SHIFT)
# define OTG_HPTXSTS_PTXFSAVL_FULL (0 << OTG_HPTXSTS_PTXFSAVL_SHIFT)
#define OTG_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
#define OTG_HPTXSTS_PTXQSAV_MASK (0xff << OTG_HPTXSTS_PTXQSAV_SHIFT)
# define OTG_HPTXSTS_PTXQSAV_FULL (0 << OTG_HPTXSTS_PTXQSAV_SHIFT)
#define OTG_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
#define OTG_HPTXSTS_PTXQTOP_MASK (0xff << OTG_HPTXSTS_PTXQTOP_SHIFT)
# define OTG_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
# define OTG_HPTXSTS_TYPE_MASK (3 << OTG_HPTXSTS_TYPE_SHIFT)
# define OTG_HPTXSTS_TYPE_INOUT (0 << OTG_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTG_HPTXSTS_TYPE_ZLP (1 << OTG_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
# define OTG_HPTXSTS_TYPE_HALT (3 << OTG_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
# define OTG_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HPTXSTS_EPNUM_MASK (15 << OTG_HPTXSTS_EPNUM_SHIFT)
# define OTG_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HPTXSTS_CHNUM_MASK (15 << OTG_HPTXSTS_CHNUM_SHIFT)
# define OTG_HPTXSTS_ODD (1 << 31) /* Bit 31: Send in odd (vs even) frame */
/* Host all channels interrupt and all channels interrupt mask registers */
#define OTG_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */
/* Host port control and status register */
#define OTG_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
#define OTG_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
#define OTG_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
#define OTG_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
#define OTG_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
#define OTG_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
/* Bit 9: Reserved */
#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
#define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT)
# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
# define OTG_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
#define OTG_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
#define OTG_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
#define OTG_HPRT_PTCTL_MASK (15 << OTG_HPRT_PTCTL_SHIFT)
# define OTG_HPRT_PTCTL_DISABLED (0 << OTG_HPRT_PTCTL_SHIFT) /* Test mode disabled */
# define OTG_HPRT_PTCTL_J (1 << OTG_HPRT_PTCTL_SHIFT) /* Test_J mode */
# define OTG_HPRT_PTCTL_L (2 << OTG_HPRT_PTCTL_SHIFT) /* Test_K mode */
# define OTG_HPRT_PTCTL_SE0_NAK (3 << OTG_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTG_HPRT_PTCTL_PACKET (4 << OTG_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
# define OTG_HPRT_PTCTL_FORCE (5 << OTG_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
#define OTG_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
#define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT)
# define OTG_HPRT_PSPD_HS (0 << OTG_HPRT_PSPD_SHIFT) /* High speed */
# define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */
# define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */
/* Bits 19-31: Reserved */
/* Host channel-n characteristics register */
#define OTG_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_HCCHAR_MPSIZ_MASK (0x7ff << OTG_HCCHAR_MPSIZ_SHIFT)
#define OTG_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
#define OTG_HCCHAR_EPNUM_MASK (15 << OTG_HCCHAR_EPNUM_SHIFT)
#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
# define OTG_HCCHAR_EPDIR_OUT (0)
# define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR
/* Bit 16 Reserved */
#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT)
# define OTG_HCCHAR_EPTYP_CTRL (0 << OTG_HCCHAR_EPTYP_SHIFT) /* Control */
# define OTG_HCCHAR_EPTYP_ISOC (1 << OTG_HCCHAR_EPTYP_SHIFT) /* Isochronous */
# define OTG_HCCHAR_EPTYP_BULK (2 << OTG_HCCHAR_EPTYP_SHIFT) /* Bulk */
# define OTG_HCCHAR_EPTYP_INTR (3 << OTG_HCCHAR_EPTYP_SHIFT) /* Interrupt */
#define OTG_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
#define OTG_HCCHAR_MCNT_MASK (3 << OTG_HCCHAR_MCNT_SHIFT)
#define OTG_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
#define OTG_HCCHAR_DAD_MASK (0x7f << OTG_HCCHAR_DAD_SHIFT)
#define OTG_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
#define OTG_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
#define OTG_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
/* TODO: OTG host channel-n split control register */
/* Host channel-n interrupt and Host channel-0 interrupt mask registers */
#define OTG_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */
#define OTG_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */
#define OTG_HCINT_AHBERR (1 << 2) /* Bit 2: AHB error */
#define OTG_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */
#define OTG_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */
#define OTG_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */
#define OTG_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */
#define OTG_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */
#define OTG_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */
#define OTG_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */
#define OTG_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */
/* Bits 11-31: Reserved */
/* Host channel-n interrupt register */
#define OTG_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTG_HCTSIZ_XFRSIZ_SHIFT)
#define OTG_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */
#define OTG_HCTSIZ_PKTCNT_MASK (0x3ff << OTG_HCTSIZ_PKTCNT_SHIFT)
#define OTG_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */
#define OTG_HCTSIZ_DPID_MASK (3 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_DATA0 (0 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_DATA2 (1 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */
# define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */
/* Bit 31: Reserved */
/* Device configuration register */
#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT)
# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High speed */
# define OTG_DCFG_DSPD_FSHS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using HS */
# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed using internal FS PHY */
#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
/* Bit 3: Reserved */
#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
#define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT)
#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
#define OTG_DCFG_PFIVL_MASK (3 << OTG_DCFG_PFIVL_SHIFT)
# define OTG_DCFG_PFIVL_80PCT (0 << OTG_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
# define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bit 13: Reserved */
#define OTG_DCFG_XCVRDLY (1 << 14) /* Bit 14: Transceiver delay */
#define OTG_DCFG_ERRATIMY (1 << 15) /* Bit 15: Erratic error interrupt mask */
/* Bits 16-23: Reserved */
#define OTG_DCFG_PERSCHIVL_SHIFT (24) /* Bits 24-25: Periodic schedule interval */
#define OTG_DCFG_PERSCHIVL_MASK (3 << OTG_DCFG_PERSCHIVL_SHIFT)
/* Bits 26-31: Reserved */
/* Device control register */
#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */
#define OTG_TESTMODE_J (1) /* Test_J mode */
#define OTG_TESTMODE_K (2) /* Test_K mode */
#define OTG_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */
#define OTG_TESTMODE_PACKET (4) /* Test_Packet mode */
#define OTG_TESTMODE_FORCE (5) /* Test_Force_Enable */
#define OTG_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */
#define OTG_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */
#define OTG_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */
#define OTG_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */
#define OTG_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */
#define OTG_DCTL_TCTL_MASK (7 << OTG_DCTL_TCTL_SHIFT)
# define OTG_DCTL_TCTL_DISABLED (0 << OTG_DCTL_TCTL_SHIFT) /* Test mode disabled */
# define OTG_DCTL_TCTL_J (1 << OTG_DCTL_TCTL_SHIFT) /* Test_J mode */
# define OTG_DCTL_TCTL_K (2 << OTG_DCTL_TCTL_SHIFT) /* Test_K mode */
# define OTG_DCTL_TCTL_SE0_NAK (3 << OTG_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTG_DCTL_TCTL_PACKET (4 << OTG_DCTL_TCTL_SHIFT) /* Test_Packet mode */
# define OTG_DCTL_TCTL_FORCE (5 << OTG_DCTL_TCTL_SHIFT) /* Test_Force_Enable */
#define OTG_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */
#define OTG_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */
#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
/* Bits 12-17: Reserved */
#define OTG_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: Deep sleep BESL reject */
/* Bits 19-31: Reserved */
/* Device status register */
#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
#define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT)
# define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */
/* Bits 4-7: Reserved */
#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
#define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT)
#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */
#define OTG_DSTS_SOFFN_EVEN 0
#define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0
/* Bits 23-31: Reserved */
#define OTG_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: Device line status */
#define OTG_DSTS_DEVLNSTS_MASK (3 << OTG_DSTS_DEVLNSTS_SHIFT)
# define OTG_DSTS_DEVLNSTS_DP (1 << OTG_DSTS_DEVLNSTS_SHIFT)
# define OTG_DSTS_DEVLNSTS_DM (2 << OTG_DSTS_DEVLNSTS_SHIFT)
/* Bits 24-31: Reserved */
/* Device IN endpoint common interrupt mask register */
#define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
#define OTG_DIEPMSK_AHBERR (1 << 2) /* Bit 2: AHB error */
#define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */
#define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */
#define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */
/* Bit 7: Reserved */
#define OTG_DIEPMSK_TXFURM (1 << 8) /* Bit 8: FIFO underrun mask */
/* Bits 9-12: Reserved */
#define OTG_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */
/* Bits 14-31: Reserved */
/* Device OUT endpoint common interrupt mask register */
#define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */
#define OTG_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */
#define OTG_DOEPMSK_AHBERR (1 << 2) /* Bit 2: AHB error */
#define OTG_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */
#define OTG_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */
#define OTG_DOEPMSK_STSPHSRXM (1 << 5) /* Bit 5: Status phase received for control write mask */
#define OTG_DOEPMSK_B2BSTUPM (1 << 6) /* Bit 6: Back-to-back SETUP packets received mask */
/* Bit 7: Reserved */
#define OTG_DOEPMSK_OUTPKTERRM (1 << 8) /* Bit 8: Out packet error mask */
/* Bits 9-11: Reserved */
#define OTG_DOEPMSK_BERR (1 << 12) /* Bit 12: Babble error interrupt mask */
#define OTG_DOEPMSK_NAK (1 << 13) /* Bit 13: NAK interrupt mask */
#define OTG_DOEPMSK_NYET (1 << 14) /* Bit 14: NYET interrupt mask */
/* Bits 15-31: Reserved */
/* Device all endpoints interrupt and All endpoints interrupt mask registers */
#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */
#define OTG_DAINT_IEP_MASK (0xffff << OTG_DAINT_IEP_SHIFT)
# define OTG_DAINT_IEP(n) (1 << (n))
#define OTG_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */
#define OTG_DAINT_OEP_MASK (0xffff << OTG_DAINT_OEP_SHIFT)
# define OTG_DAINT_OEP(n) (1 << ((n)+16))
/* Device VBUS discharge time register */
#define OTG_DVBUSDIS_MASK (0xffff)
/* Device VBUS pulsing time register */
#define OTG_DVBUSPULSE_MASK (0xfff)
/* TODO: OTG device threshold control register */
/* Device IN endpoint FIFO empty interrupt mask register */
#define OTG_DIEPEMPMSK(n) (1 << (n))
/* TODO: OTG device each endpoint interrupt register */
/* TODO: OTG device each endpoint-1 interrupt */
/* Device control IN endpoint n control register */
#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved */
#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
# define OTG_DIEPCTL_EVEN (0)
# define OTG_DIEPCTL_ODD OTG_DIEPCTL_EONUM
# define OTG_DIEPCTL_DATA0 (0)
# define OTG_DIEPCTL_DATA1 OTG_DIEPCTL_EONUM
#define OTG_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DIEPCTL_EPTYP_MASK (3 << OTG_DIEPCTL_EPTYP_SHIFT)
# define OTG_DIEPCTL_EPTYP_CTRL (0 << OTG_DIEPCTL_EPTYP_SHIFT) /* Control */
# define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
/* Bit 20: Reserved */
#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT)
#define OTG_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */
#define OTG_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */
#define OTG_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
#define OTG_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTG_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
#define OTG_DIEPINT_AHBERR (1 << 2) /* Bit 2: AHB error */
#define OTG_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */
#define OTG_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */
#define OTG_DIEPINT_INEPNM (1 << 5) /* Bit 5: */
#define OTG_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */
#define OTG_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */
#define OTG_DIEPINT_TXFIFOUDRN (1 << 8) /* Bit 8: Transmit FIFO underrun */
/* Bits 9-10: Reserved */
#define OTG_DIEPINT_PKTDRPSTS (1 << 11) /* Bit 11: Packet dropped status */
/* Bit 12: Reserved */
#define OTG_DIEPINT_NAK (1 << 13) /* Bit 13: NAK input */
/* Bits 14-31: Reserved */
/* Device IN endpoint 0 transfer size register */
#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
#define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT)
/* Bits 21-31: Reserved, must be kept at reset value */
/* Device IN endpoint n transfer size register */
#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTG_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DIEPTSIZ_XFRSIZ_SHIFT)
#define OTG_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT)
#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
#define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT)
/* Bit 31: Reserved */
/* Device OUT endpoint TxFIFO status register */
#define OTG_DTXFSTS_MASK (0xffff)
/* Device OUT endpoint 0 control register */
#define OTG_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
#define OTG_DOEPCTL0_MPSIZ_MASK (3 << OTG_DOEPCTL0_MPSIZ_SHIFT)
# define OTG_DOEPCTL0_MPSIZ_64 (0 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
# define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved */
#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved */
#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT)
# define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved */
#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device OUT endpoint n control register */
#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved */
#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */
# define OTG_DOEPCTL_DATA0 (0)
# define OTG_DOEPCTL_DATA1 OTG_DOEPCTL_DPID
#define OTG_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */
# define OTG_DOEPCTL_EVEN (0)
# define OTG_DOEPCTL_ODD OTG_DOEPCTL_EONUM
#define OTG_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL_EPTYP_MASK (3 << OTG_DOEPCTL_EPTYP_SHIFT)
# define OTG_DOEPCTL_EPTYP_CTRL (0 << OTG_DOEPCTL_EPTYP_SHIFT) /* Control */
# define OTG_DOEPCTL_EPTYP_ISOC (1 << OTG_DOEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTG_DOEPCTL_EPTYP_BULK (2 << OTG_DOEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */
#define OTG_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */
#define OTG_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
#define OTG_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */
#define OTG_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */
#define OTG_DOEPINT_AHBERR (1 << 2) /* Bit 2: AHB error */
#define OTG_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */
#define OTG_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */
#define OTG_DOEPINT_STSPHSRXM (1 << 5) /* Bit 5: Status phase received for control write mask */
#define OTG_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */
/* Bit 7: Reserved */
#define OTG_DOEPINT_OUTPKTERRM (1 << 8) /* Bit 8: Out packet error mask */
/* Bits 9-11: Reserved */
#define OTG_DOEPINT_BERR (1 << 12) /* Bit 12: Babble error interrupt mask */
#define OTG_DOEPINT_NAK (1 << 13) /* Bit 13: NAK interrupt mask */
#define OTG_DOEPINT_NYET (1 << 14) /* Bit 14: NYET interrupt mask */
/* Bits 15-31: Reserved */
/* Device OUT endpoint-0 transfer size register */
#define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved */
#define OTG_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */
/* Bits 20-28: Reserved */
#define OTG_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
#define OTG_DOEPTSIZ0_STUPCNT_MASK (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT)
/* Bit 31: Reserved */
/* Device OUT endpoint-n transfer size register */
#define OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTG_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DOEPTSIZ_XFRSIZ_SHIFT)
#define OTG_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTG_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DOEPTSIZ_PKTCNT_SHIFT)
#define OTG_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */
#define OTG_DOEPTSIZ_STUPCNT_MASK (3 << OTG_DOEPTSIZ_STUPCNT_SHIFT)
#define OTG_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */
#define OTG_DOEPTSIZ_RXDPID_MASK (3 << OTG_DOEPTSIZ_RXDPID_SHIFT)
# define OTG_DOEPTSIZ_RXDPID_DATA0 (0 << OTG_DOEPTSIZ_RXDPID_SHIFT)
# define OTG_DOEPTSIZ_RXDPID_DATA2 (1 << OTG_DOEPTSIZ_RXDPID_SHIFT)
# define OTG_DOEPTSIZ_RXDPID_DATA1 (2 << OTG_DOEPTSIZ_RXDPID_SHIFT)
# define OTG_DOEPTSIZ_RXDPID_MDATA (3 << OTG_DOEPTSIZ_RXDPID_SHIFT)
/* Bit 31: Reserved */
/* Power and clock gating control register */
#define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */
#define OTG_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */
/* Bits 2-3: Reserved */
#define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */
#define OTG_PCGCCTL_ENL1GTG (1 << 5) /* Bit 5: PHY Suspended */
#define OTG_PCGCCTL_PHYSLEEP (1 << 6) /* Bit 6: PHY Suspended */
#define OTG_PCGCCTL_SUSP (1 << 7) /* Bit 7: PHY Suspended */
/* Bits 7-31: Reserved */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */

4
arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h
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@ -160,8 +160,8 @@
#define STM32_DMAMUX1_BASE 0x40020800 /* 0x40020800-0x40020bff DMAMUX1 */
#define STM32_ADC12_BASE 0x40022000 /* 0x40022000-0x400223ff ADC1-ADC2 */
#define STM32_EMAC_BASE 0x40028000 /* 0x40028000-0x400293ff Ethernet MAC */
#define STM32_USB1_BASE 0x40040000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
#define STM32_USB2_BASE 0x40080000 /* 0x40080000-0x400bffff USB2 OTG FS */
#define STM32_OTGHS_BASE 0x40040000 /* 0x40040000-0x4007ffff USB1 OTG HS/FS */
#define STM32_OTGFS_BASE 0x40080000 /* 0x40080000-0x400bffff USB2 OTG FS */
/* AHB2 Base Addresses **************************************************************/

16
arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h
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@ -671,17 +671,17 @@
/* USB on-the-go full-speed (OTG_FS) */
#define GPIO_OTG_FS_DM (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTG_FS_DP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTG_FS_ID (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTG_FS_SOF (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
#define GPIO_OTGFS_DM (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
#define GPIO_OTGFS_DP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN12)
#define GPIO_OTGFS_ID (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN10)
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN8)
/* USB on-the-go high-speed (OTG_HS) */
#define GPIO_OTG_HS_DM (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_OTG_HS_DP (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
#define GPIO_OTG_HS_ID (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12)
#define GPIO_OTG_HS_SOF (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN14)
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTB|GPIO_PIN15)
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN12)
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_OTG_HS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
#define GPIO_OTG_HS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)

11
arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h
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@ -109,6 +109,17 @@
/* Power control register 3 (CR3) */
#define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */
#define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */
#define STM32_PWR_CR3_LDOESCUEN (1 << 2) /* Bit 2: Supply configuration update enable */
/* Bits 3-7: Reserved */
#define STM32_PWR_CR3_VBE (1 << 8) /* Bit 8: VBAT charging enable */
#define STM32_PWR_CR3_VBRS (1 << 9) /* Bit 9: VBAT charging resistor selection */
/* Bits 10-23: Reserved */
#define STM32_PWR_CR3_USB33DEN (1 << 24) /* Bit 24: VDD33USB voltage level detector enable */
#define STM32_PWR_CR3_USBREGEN (1 << 25) /* Bit 25: USB regulator enable */
#define STM32_PWR_CR3_USB33RDY (1 << 26) /* Bit 26: USB supply ready */
/* Power CPU control register (CPUCR) */
/* Power D3 domain control register (D3CR) */

275
arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h
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@ -583,16 +583,30 @@
# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 0 */
# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) /* 1 */
/* TODO: Bit definitions for RCC_D2CCIP2R reigster */
/* Bit definitions for RCC_D2CCIP2R reigster */
/* ... */
#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */
#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT)
# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */
# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
/* ... */
#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */
# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT)
#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */
# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT)
#define RCC_D2CCIP2R_RNGSEL_SHIFT (3) /* Bits 8-9 */
# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT)
#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */
#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT)
# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 00 */
# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */
# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT)
# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT)
# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT)
# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT)
# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT)
#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */
# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT)
#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */
# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT)
/* TODO: Bit definitions for RCC_D3CCIPR reigster */
@ -665,27 +679,18 @@
/* Bit definitions for RCC_CSR register */
#define RCC_CSR_LSION_SHIFT (0ul) /* RCC CSR: LSION (Bit 0) */
#define RCC_CSR_LSION (0x1ul) /* RCC CSR: LSION (Bitfield-Mask: 0x01) */
#define RCC_CSR_LSIRDY_SHIFT (1ul) /* RCC CSR: LSIRDY (Bit 1) */
#define RCC_CSR_LSIRDY (0x2ul) /* RCC CSR: LSIRDY (Bitfield-Mask: 0x01) */
#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */
#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */
/* AHB3 peripheral reset register */
#define RCC_AHB3RSTR_MDMARST_SHIFT (0ul) /* RCC AHB3RSTR: MDMARST (Bit 0) */
#define RCC_AHB3RSTR_MDMARST (0x1ul) /* RCC AHB3RSTR: MDMARST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_DMA2DRST_SHIFT (4ul) /* RCC AHB3RSTR: DMA2DRST (Bit 4) */
#define RCC_AHB3RSTR_DMA2DRST (0x10ul) /* RCC AHB3RSTR: DMA2DRST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_JPGDECRST_SHIFT (5ul) /* RCC AHB3RSTR: JPGDECRST (Bit 5) */
#define RCC_AHB3RSTR_JPGDECRST (0x20ul) /* RCC AHB3RSTR: JPGDECRST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_FMCRST_SHIFT (12ul) /* RCC AHB3RSTR: FMCRST (Bit 12) */
#define RCC_AHB3RSTR_FMCRST (0x1000ul) /* RCC AHB3RSTR: FMCRST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_QSPIRST_SHIFT (14ul) /* RCC AHB3RSTR: QSPIRST (Bit 14) */
#define RCC_AHB3RSTR_QSPIRST (0x4000ul) /* RCC AHB3RSTR: QSPIRST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_SDMMC1RST_SHIFT (16ul) /* RCC AHB3RSTR: SDMMC1RST (Bit 16) */
#define RCC_AHB3RSTR_SDMMC1RST (0x10000ul) /* RCC AHB3RSTR: SDMMC1RST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_CPURST_SHIFT (31ul) /* RCC AHB3RSTR: CPURST (Bit 31) */
#define RCC_AHB3RSTR_CPURST (0x80000000ul) /* RCC AHB3RSTR: CPURST (Bitfield-Mask: 0x01) */
#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */
#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */
#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */
#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */
#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */
#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */
#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */
/* AHB1 peripheral reset register */
@ -695,9 +700,9 @@
/* Bits 6-14: Reserved */
#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */
/* Bits 16-24: Reserved */
#define RCC_AHB1RSTR_USB1OTGRST (1 << 25) /* RCC AHB1RSTR: USB1OTGRST */
#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */
/* Bit 26: Reserved */
#define RCC_AHB1RSTR_USB2OTGRST (1 << 27) /* RCC AHB1RSTR: USB2OTGRST */
#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */
/* Bits 28-31: Reserved */
/* AHB2 peripheral reset register */
@ -837,10 +842,9 @@
#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */
#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */
#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */
#define RCC_AHB1ENR_USB1OTGEN (1 << 25) /* RCC AHB1ENR: USB1OTGEN */
#define RCC_AHB1ENR_USB1ULPIEN (1 << 26) /* RCC AHB1ENR: USB1ULPIEN */
#define RCC_AHB1ENR_USB2OTGEN (1 << 27) /* RCC AHB1ENR: USB2OTGEN */
#define RCC_AHB1ENR_USB2ULPIEN (1 << 28) /* RCC AHB1ENR: USB2ULPIEN */
#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */
#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */
#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */
/* AHB2 Peripheral Clock enable register */
@ -968,134 +972,133 @@
/* AHB3 low power mode peripheral clock enable register */
#define RCC_AHB3LPENR_MDMALPEN (0x1ul) /* RCC AHB3LPENR: MDMALPEN */
#define RCC_AHB3LPENR_DMA2DLPEN (0x10ul) /* RCC AHB3LPENR: DMA2DLPEN */
#define RCC_AHB3LPENR_JPGDECLPEN (0x20ul) /* RCC AHB3LPENR: JPGDECLPEN */
#define RCC_AHB3LPENR_FLITFLPEN (0x100ul) /* RCC AHB3LPENR: FLITFLPEN */
#define RCC_AHB3LPENR_FMCLPEN (0x1000ul) /* RCC AHB3LPENR: FMCLPEN */
#define RCC_AHB3LPENR_QSPILPEN (0x4000ul) /* RCC AHB3LPENR: QSPILPEN */
#define RCC_AHB3LPENR_SDMMC1LPEN (0x10000ul) /* RCC AHB3LPENR: SDMMC1LPEN */
#define RCC_AHB3LPENR_D1DTCM1LPEN (0x10000000ul) /* RCC AHB3LPENR: D1DTCM1LPEN */
#define RCC_AHB3LPENR_DTCM2LPEN (0x20000000ul) /* RCC AHB3LPENR: DTCM2LPEN */
#define RCC_AHB3LPENR_ITCMLPEN (0x40000000ul) /* RCC AHB3LPENR: ITCMLPEN */
#define RCC_AHB3LPENR_AXISRAMLPEN (0x80000000ul) /* RCC AHB3LPENR: AXISRAMLPEN */
#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */
#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */
#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */
#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */
#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */
#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */
#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */
#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */
#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */
#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */
#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */
/* AHB1 low power mode peripheral clock enable register */
#define RCC_AHB1LPENR_DMA1LPEN (0x1ul) /* RCC AHB1LPENR: DMA1LPEN */
#define RCC_AHB1LPENR_DMA2LPEN (0x2ul) /* RCC AHB1LPENR: DMA2LPEN */
#define RCC_AHB1LPENR_ADC12LPEN (0x20ul) /* RCC AHB1LPENR: ADC12LPEN */
#define RCC_AHB1LPENR_ETH1MACLPEN (0x8000ul) /* RCC AHB1LPENR: ETH1MACLPEN */
#define RCC_AHB1LPENR_ETH1TXLPEN (0x10000ul) /* RCC AHB1LPENR: ETH1TXLPEN */
#define RCC_AHB1LPENR_ETH1RXLPEN (0x20000ul) /* RCC AHB1LPENR: ETH1RXLPEN */
#define RCC_AHB1LPENR_USB1OTGLPEN (0x2000000ul) /* RCC AHB1LPENR: USB1OTGLPEN */
#define RCC_AHB1LPENR_USB1ULPILPEN (0x4000000ul) /* RCC AHB1LPENR: USB1ULPILPEN */
#define RCC_AHB1LPENR_USB2OTGLPEN (0x8000000ul) /* RCC AHB1LPENR: USB2OTGLPEN */
#define RCC_AHB1LPENR_USB2ULPILPEN (0x10000000ul) /* RCC AHB1LPENR: USB2ULPILPEN */
#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */
#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */
#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */
#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */
#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */
#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */
#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */
#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */
#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */
/* AHB2 low power mode peripheral clock enable register */
#define RCC_AHB2LPENR_CAMITFLPEN (0x1ul) /* RCC AHB2LPENR: CAMITFLPEN */
#define RCC_AHB2LPENR_CRYPTLPEN (0x10ul) /* RCC AHB2LPENR: CRYPTLPEN */
#define RCC_AHB2LPENR_HASHLPEN (0x20ul) /* RCC AHB2LPENR: HASHLPEN */
#define RCC_AHB2LPENR_SDMMC2LPEN (0x200ul) /* RCC AHB2LPENR: SDMMC2LPEN */
#define RCC_AHB2LPENR_RNGLPEN (0x40ul) /* RCC AHB2LPENR: RNGLPEN */
#define RCC_AHB2LPENR_SRAM1LPEN (0x20000000ul) /* RCC AHB2LPENR: SRAM1LPEN */
#define RCC_AHB2LPENR_SRAM2LPEN (0x40000000ul) /* RCC AHB2LPENR: SRAM2LPEN */
#define RCC_AHB2LPENR_SRAM3LPEN (0x80000000ul) /* RCC AHB2LPENR: SRAM3LPEN */
#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */
#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */
#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */
#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */
#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */
#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */
#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */
#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */
/* AHB4 low power mode peripheral clock enable register*/
#define RCC_AHB4LPENR_GPIOALPEN (0x1ul) /* RCC AHB4LPENR: GPIOALPEN */
#define RCC_AHB4LPENR_GPIOBLPEN (0x2ul) /* RCC AHB4LPENR: GPIOBLPEN */
#define RCC_AHB4LPENR_GPIOCLPEN (0x4ul) /* RCC AHB4LPENR: GPIOCLPEN */
#define RCC_AHB4LPENR_GPIODLPEN (0x8ul) /* RCC AHB4LPENR: GPIODLPEN */
#define RCC_AHB4LPENR_GPIOELPEN (0x10ul) /* RCC AHB4LPENR: GPIOELPEN */
#define RCC_AHB4LPENR_GPIOFLPEN (0x20ul) /* RCC AHB4LPENR: GPIOFLPEN */
#define RCC_AHB4LPENR_GPIOGLPEN (0x40ul) /* RCC AHB4LPENR: GPIOGLPEN */
#define RCC_AHB4LPENR_GPIOHLPEN (0x80ul) /* RCC AHB4LPENR: GPIOHLPEN */
#define RCC_AHB4LPENR_GPIOILPEN (0x100ul) /* RCC AHB4LPENR: GPIOILPEN */
#define RCC_AHB4LPENR_GPIOJLPEN (0x200ul) /* RCC AHB4LPENR: GPIOJLPEN */
#define RCC_AHB4LPENR_GPIOKLPEN (0x400ul) /* RCC AHB4LPENR: GPIOKLPEN */
#define RCC_AHB4LPENR_CRCLPEN (0x80000ul) /* RCC AHB4LPENR: CRCLPEN */
#define RCC_AHB4LPENR_BDMALPEN (0x200000ul) /* RCC AHB4LPENR: BDMALPEN */
#define RCC_AHB4LPENR_ADC3LPEN (0x1000000ul) /* RCC AHB4LPENR: ADC3LPEN */
#define RCC_AHB4LPENR_BKPRAMLPEN (0x10000000ul) /* RCC AHB4LPENR: BKPRAMLPEN */
#define RCC_AHB4LPENR_SRAM4LPEN (0x20000000ul) /* RCC AHB4LPENR: SRAM4LPEN */
#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */
#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */
#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */
#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */
#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */
#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */
#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */
#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */
#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */
#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */
#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */
#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */
#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */
#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */
#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */
#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */
/* APB3 low power mode peripheral clock enable register */
#define RCC_APB3LPENR_LTDCLPEN (0x8ul) /* RCC APB3LPENR: LTDCLPEN */
#define RCC_APB3LPENR_WWDG1LPEN (0x40ul) /* RCC APB3LPENR: WWDG1LPEN */
#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */
#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */
/* APB1 L low power mode peripheral clock enable register */
#define RCC_APB1LLPENR_TIM2LPEN (0x1ul) /* RCC APB1LLPENR: TIM2LPEN */
#define RCC_APB1LLPENR_TIM3LPEN (0x2ul) /* RCC APB1LLPENR: TIM3LPEN */
#define RCC_APB1LLPENR_TIM4LPEN (0x4ul) /* RCC APB1LLPENR: TIM4LPEN */
#define RCC_APB1LLPENR_TIM5LPEN (0x8ul) /* RCC APB1LLPENR: TIM5LPEN */
#define RCC_APB1LLPENR_TIM6LPEN (0x10ul) /* RCC APB1LLPENR: TIM6LPEN */
#define RCC_APB1LLPENR_TIM7LPEN (0x20ul) /* RCC APB1LLPENR: TIM7LPEN */
#define RCC_APB1LLPENR_TIM12LPEN (0x40ul) /* RCC APB1LLPENR: TIM12LPEN */
#define RCC_APB1LLPENR_TIM13LPEN (0x80ul) /* RCC APB1LLPENR: TIM13LPEN */
#define RCC_APB1LLPENR_TIM14LPEN (0x100ul) /* RCC APB1LLPENR: TIM14LPEN */
#define RCC_APB1LLPENR_LPTIM1LPEN (0x200ul) /* RCC APB1LLPENR: LPTIM1LPEN */
#define RCC_APB1LLPENR_SPI2LPEN (0x4000ul) /* RCC APB1LLPENR: SPI2LPEN */
#define RCC_APB1LLPENR_SPI3LPEN (0x8000ul) /* RCC APB1LLPENR: SPI3LPEN */
#define RCC_APB1LLPENR_SPDIFRXLPEN (0x10000ul) /* RCC APB1LLPENR: SPDIFRXLPEN */
#define RCC_APB1LLPENR_USART2LPEN (0x20000ul) /* RCC APB1LLPENR: USART2LPEN */
#define RCC_APB1LLPENR_USART3LPEN (0x40000ul) /* RCC APB1LLPENR: USART3LPEN */
#define RCC_APB1LLPENR_UART4LPEN (0x80000ul) /* RCC APB1LLPENR: UART4LPEN */
#define RCC_APB1LLPENR_UART5LPEN (0x100000ul) /* RCC APB1LLPENR: UART5LPEN */
#define RCC_APB1LLPENR_I2C1LPEN (0x200000ul) /* RCC APB1LLPENR: I2C1LPEN */
#define RCC_APB1LLPENR_I2C2LPEN (0x400000ul) /* RCC APB1LLPENR: I2C2LPEN */
#define RCC_APB1LLPENR_I2C3LPEN (0x800000ul) /* RCC APB1LLPENR: I2C3LPEN */
#define RCC_APB1LLPENR_HDMICECLPEN (0x8000000ul) /* RCC APB1LLPENR: HDMICECLPEN */
#define RCC_APB1LLPENR_DAC1LPEN (0x20000000ul) /* RCC APB1LLPENR: DAC1LPEN */
#define RCC_APB1LLPENR_USART7LPEN (0x40000000ul) /* RCC APB1LLPENR: USART7LPEN */
#define RCC_APB1LLPENR_USART8LPEN (0x80000000ul) /* RCC APB1LLPENR: USART8LPEN */
#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */
#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */
#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */
#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */
#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */
#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */
#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */
#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */
#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */
#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */
#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */
#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */
#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */
#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */
#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */
#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */
#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */
#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */
#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */
#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */
#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */
#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */
#define RCC_APB1LLPENR_USART7LPEN (1 << 30) /* RCC APB1LLPENR: USART7LPEN */
#define RCC_APB1LLPENR_USART8LPEN (1 << 31) /* RCC APB1LLPENR: USART8LPEN */
/* APB1 H low power mode peripheral clock enable register */
#define RCC_APB1HLPENR_CRSLPEN (0x2ul) /* RCC APB1HLPENR: CRSLPEN */
#define RCC_APB1HLPENR_SWPLPEN (0x4ul) /* RCC APB1HLPENR: SWPLPEN */
#define RCC_APB1HLPENR_OPAMPLPEN (0x10ul) /* RCC APB1HLPENR: OPAMPLPEN */
#define RCC_APB1HLPENR_MDIOSLPEN (0x20ul) /* RCC APB1HLPENR: MDIOSLPEN */
#define RCC_APB1HLPENR_FDCANLPEN (0x100ul) /* RCC APB1HLPENR: FDCANLPEN */
#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */
#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */
#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */
#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */
#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */
/* APB2 low power mode peripheral clock enable register */
#define RCC_APB2LPENR_TIM1LPEN (0x1ul) /* RCC APB2LPENR: TIM1LPEN */
#define RCC_APB2LPENR_TIM8LPEN (0x2ul) /* RCC APB2LPENR: TIM8LPEN */
#define RCC_APB2LPENR_USART1LPEN (0x10ul) /* RCC APB2LPENR: USART1LPEN */
#define RCC_APB2LPENR_USART6LPEN (0x20ul) /* RCC APB2LPENR: USART6LPEN */
#define RCC_APB2LPENR_SPI1LPEN (0x1000ul) /* RCC APB2LPENR: SPI1LPEN */
#define RCC_APB2LPENR_SPI4LPEN (0x2000ul) /* RCC APB2LPENR: SPI4LPEN */
#define RCC_APB2LPENR_TIM15LPEN (0x10000ul) /* RCC APB2LPENR: TIM15LPEN */
#define RCC_APB2LPENR_TIM16LPEN (0x20000ul) /* RCC APB2LPENR: TIM16LPEN */
#define RCC_APB2LPENR_TIM17LPEN (0x40000ul) /* RCC APB2LPENR: TIM17LPEN */
#define RCC_APB2LPENR_SPI5LPEN (0x100000ul) /* RCC APB2LPENR: SPI5LPEN */
#define RCC_APB2LPENR_SAI1LPEN (0x400000ul) /* RCC APB2LPENR: SAI1LPEN */
#define RCC_APB2LPENR_SAI2LPEN (0x800000ul) /* RCC APB2LPENR: SAI2LPEN */
#define RCC_APB2LPENR_SAI3LPEN (0x1000000ul) /* RCC APB2LPENR: SAI3LPEN */
#define RCC_APB2LPENR_DFSDM1LPEN (0x10000000ul) /* RCC APB2LPENR: DFSDM1LPEN */
#define RCC_APB2LPENR_HRTIMLPEN (0x20000000ul) /* RCC APB2LPENR: HRTIMLPEN */
#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */
#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */
#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */
#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */
#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */
#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */
#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */
#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */
#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */
#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */
#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */
#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */
#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */
#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */
/* APB4 low power mode peripheral clock enable register */
#define RCC_APB4LPENR_SYSCFGLPEN (0x2ul) /* RCC APB4LPENR: SYSCFGLPEN */
#define RCC_APB4LPENR_LPUART1LPEN (0x8ul) /* RCC APB4LPENR: LPUART1LPEN */
#define RCC_APB4LPENR_SPI6LPEN (0x20ul) /* RCC APB4LPENR: SPI6LPEN */
#define RCC_APB4LPENR_I2C4LPEN (0x80ul) /* RCC APB4LPENR: I2C4LPEN */
#define RCC_APB4LPENR_LPTIM2LPEN (0x200ul) /* RCC APB4LPENR: LPTIM2LPEN */
#define RCC_APB4LPENR_LPTIM3LPEN (0x400ul) /* RCC APB4LPENR: LPTIM3LPEN */
#define RCC_APB4LPENR_LPTIM4LPEN (0x800ul) /* RCC APB4LPENR: LPTIM4LPEN */
#define RCC_APB4LPENR_LPTIM5LPEN (0x1000ul) /* RCC APB4LPENR: LPTIM5LPEN */
#define RCC_APB4LPENR_COMP12LPEN (0x4000ul) /* RCC APB4LPENR: COMP12LPEN */
#define RCC_APB4LPENR_VREFLPEN (0x8000ul) /* RCC APB4LPENR: VREFLPEN */
#define RCC_APB4LPENR_RTCAPBLPEN (0x10000ul) /* RCC APB4LPENR: RTCAPBLPEN */
#define RCC_APB4LPENR_SAI4LPEN (0x200000ul) /* RCC APB4LPENR: SAI4LPEN */
#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */
#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */
#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */
#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */
#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */
#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */
#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */
#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */
#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */
#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */
#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */
#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */
#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H */

144
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@ -0,0 +1,144 @@
/************************************************************************************
* arch/arm/src/stm32h7/stm32_otg.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_OTG_H
#define __ARCH_ARM_SRC_STM32H7_STM32_OTG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "chip.h"
#include "chip/stm32_otg.h"
#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#if defined(CONFIG_STM32H7_OTGFS)
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
# define STM32_OTG_BASE STM32_OTGFS_BASE /* OTG FS */
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
# define GPIO_OTG_DM GPIO_OTGFS_DM
# define GPIO_OTG_DP GPIO_OTGFS_DP
# define GPIO_OTG_ID GPIO_OTGFS_ID
# define GPIO_OTG_SOF GPIO_OTGFS_SOF
# define STM32_OTG_FIFO_SIZE 4096
#endif
#if defined(CONFIG_STM32H7_OTGHS)
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
# define STM32_OTG_BASE STM32_OTGHS_BASE /* OTG HS/FS */
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
# define GPIO_OTG_DM GPIO_OTGHS_DM
# define GPIO_OTG_DP GPIO_OTGHS_DP
# define GPIO_OTG_ID GPIO_OTGHS_ID
# define GPIO_OTG_SOF GPIO_OTGHS_SOF
# define STM32_OTG_FIFO_SIZE 4096
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_otgfshost_initialize
*
* Description:
* Initialize USB host device controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than USB host controller, then
* this identifies which controller is being initializeed. Normally, this
* is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order
* to initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already connected.
*
****************************************************************************/
#ifdef CONFIG_USBHOST
struct usbhost_connection_s;
FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller);
#endif
/************************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver
* is used. This function is called whenever the USB enters or leaves suspend
* mode. This is an opportunity for the board logic to shutdown clocks, power,
* etc. while the USB is suspended.
*
************************************************************************************/
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_STM32H7_OTGFS */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */

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arch/arm/src/stm32h7/stm32_otghost.c Normal file
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202
arch/arm/src/stm32h7/stm32_usbhost.h Normal file
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@ -0,0 +1,202 @@
/************************************************************************************
* arch/arm/src/stm32h7/stm32_usbhost.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H
#define __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H
/* STM32 USB OTG Host Driver Support
*
* Pre-requisites
*
* CONFIG_USBHOST - Enable general USB host support
* CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block
* or
* CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block
* CONFIG_STM32H7_SYSCFG - Needed
*
* Options:
*
* CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
* Default 128 (512 bytes)
* CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
* in 32-bit words. Default 96 (384 bytes)
* CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
* words. Default 96 (384 bytes)
* CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever
* want to do that?
*
* CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access
* debug. Depends on CONFIG_DEBUG_FEATURES.
*/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \
defined(CONFIG_USBHOST)
#ifdef HAVE_USBHOST_TRACE
enum usbhost_trace1codes_e
{
__TRACE1_BASEVALUE = 0, /* This will force the first value to be 1 */
OTG_TRACE1_DEVDISCONN, /* OTG ERROR: Host Port Device disconnected */
OTG_TRACE1_IRQATTACH, /* OTG ERROR: Failed to attach IRQ */
OTG_TRACE1_TRNSFRFAILED, /* OTG ERROR: Host Port Transfer Failed */
OTG_TRACE1_SENDSETUP, /* OTG ERROR: sendsetup() failed with: */
OTG_TRACE1_SENDDATA, /* OTG ERROR: senddata() failed with: */
OTG_TRACE1_RECVDATA, /* OTG ERROR: recvdata() failed with: */
#ifdef HAVE_USBHOST_TRACE_VERBOSE
OTG_VTRACE1_CONNECTED, /* OTG Host Port connected */
OTG_VTRACE1_DISCONNECTED, /* OTG Host Port disconnected */
OTG_VTRACE1_GINT, /* OTG Handling Interrupt. Entry Point */
OTG_VTRACE1_GINT_SOF, /* OTG Handle the start of frame interrupt */
OTG_VTRACE1_GINT_RXFLVL, /* OTG Handle the RxFIFO non-empty interrupt */
OTG_VTRACE1_GINT_NPTXFE, /* OTG Handle the non-periodic TxFIFO empty interrupt */
OTG_VTRACE1_GINT_PTXFE, /* OTG Handle the periodic TxFIFO empty interrupt */
OTG_VTRACE1_GINT_HC, /* OTG Handle the host channels interrupt */
OTG_VTRACE1_GINT_HPRT, /* OTG Handle the host port interrupt */
OTG_VTRACE1_GINT_HPRT_POCCHNG, /* OTG HPRT: Port Over-Current Change*/
OTG_VTRACE1_GINT_HPRT_PCDET, /* OTG HPRT: Port Connect Detect */
OTG_VTRACE1_GINT_HPRT_PENCHNG, /* OTG HPRT: Port Enable Changed */
OTG_VTRACE1_GINT_HPRT_LSDEV, /* OTG HPRT: Low Speed Device Connected */
OTG_VTRACE1_GINT_HPRT_FSDEV, /* OTG HPRT: Full Speed Device Connected */
OTG_VTRACE1_GINT_HPRT_LSFSSW, /* OTG HPRT: Host Switch: LS -> FS */
OTG_VTRACE1_GINT_HPRT_FSLSSW, /* OTG HPRT: Host Switch: FS -> LS */
OTG_VTRACE1_GINT_DISC, /* OTG Handle the disconnect detected interrupt */
OTG_VTRACE1_GINT_IPXFR, /* OTG Handle the incomplete periodic transfer */
#endif
__TRACE1_NSTRINGS, /* Separates the format 1 from the format 2 strings */
OTG_TRACE2_CLIP, /* OTG CLIP: chidx: buflen: */
#ifdef HAVE_USBHOST_TRACE_VERBOSE
OTG_VTRACE2_CHANWAKEUP_IN, /* OTG IN Channel wake up with result */
OTG_VTRACE2_CHANWAKEUP_OUT, /* OTG OUT Channel wake up with result */
OTG_VTRACE2_CTRLIN, /* OTG CTRLIN */
OTG_VTRACE2_CTRLOUT, /* OTG CTRLOUT */
OTG_VTRACE2_INTRIN, /* OTG INTRIN */
OTG_VTRACE2_INTROUT, /* OTG INTROUT */
OTG_VTRACE2_BULKIN, /* OTG BULKIN */
OTG_VTRACE2_BULKOUT, /* OTG BULKOUT */
OTG_VTRACE2_ISOCIN, /* OTG ISOCIN */
OTG_VTRACE2_ISOCOUT, /* OTG ISOCOUT */
OTG_VTRACE2_STARTTRANSFER, /* OTG EP buflen */
OTG_VTRACE2_CHANCONF_CTRL_IN,
OTG_VTRACE2_CHANCONF_CTRL_OUT,
OTG_VTRACE2_CHANCONF_INTR_IN,
OTG_VTRACE2_CHANCONF_INTR_OUT,
OTG_VTRACE2_CHANCONF_BULK_IN,
OTG_VTRACE2_CHANCONF_BULK_OUT,
OTG_VTRACE2_CHANCONF_ISOC_IN,
OTG_VTRACE2_CHANCONF_ISOC_OUT,
OTG_VTRACE2_CHANHALT, /* Channel halted. chidx: , reason: */
#endif
__TRACE2_NSTRINGS /* Total number of enumeration values */
};
# define TRACE1_FIRST ((int)__TRACE1_BASEVALUE + 1)
# define TRACE1_INDEX(id) ((int)(id) - TRACE1_FIRST)
# define TRACE1_NSTRINGS TRACE1_INDEX(__TRACE1_NSTRINGS)
# define TRACE2_FIRST ((int)__TRACE1_NSTRINGS + 1)
# define TRACE2_INDEX(id) ((int)(id) - TRACE2_FIRST)
# define TRACE2_NSTRINGS TRACE2_INDEX(__TRACE2_NSTRINGS)
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/***********************************************************************************
* Name: stm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be
* each platform that implements the STM32 OTG FS host interface
*
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
* or, if 5 V are available on the application board, a basic power switch, must
* be added externally to drive the 5 V VBUS line. The external charge pump can
* be driven by any GPIO output. When the application decides to power on VBUS
* using the chosen GPIO, it must also set the port power bit in the host port
* control and status register (PPWR bit in OTG_FS_HPRT).
*
* "The application uses this field to control power to this port, and the core
* clears this bit on an overcurrent condition."
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
***********************************************************************************/
void stm32_usbhost_vbusdrive(int iface, bool enable);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */

44
arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
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@ -152,6 +152,24 @@ static inline void rcc_enableahb1(void)
regval |= RCC_AHB1ENR_DMA2EN;
#endif
#ifdef CONFIG_STM32H7_OTGFS
/* USB OTG FS clock enable */
regval |= RCC_AHB1ENR_OTGFSEN;
#endif
#ifdef CONFIG_STM32H7_OTGHS
#ifdef BOARD_ENABLE_USBOTG_HSULPI
/* Enable clocking for USB OTG HS and external PHY */
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#else
/* Enable only clocking for USB OTG HS */
regval |= RCC_AHB1ENR_OTGHSEN;
#endif
#endif
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
@ -424,9 +442,11 @@ static inline void rcc_enableapb4(void)
regval = getreg32(STM32_RCC_APB4ENR);
#ifdef CONFIG_STM32H7_SYSCFG
/* System configuration controller clock enable */
regval |= RCC_APB4ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32H7_I2C4
/* I2C4 clock enable */
@ -509,6 +529,21 @@ static void stm32_stdclockconfig(void)
}
#endif
#define CONFIG_STM32H7_HSI48
#ifdef CONFIG_STM32H7_HSI48
/* Enable HSI48 */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSI48ON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI48 is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_HSI48RDY) == 0)
{
}
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
@ -693,6 +728,15 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_D3CCIPR);
#endif
/* Configure USB source clock */
#if defined(STM32_RCC_D2CCIP2R_USBSRC)
regval = getreg32(STM32_RCC_D2CCIP2R);
regval &= ~RCC_D2CCIP2R_USBSEL_MASK;
regval |= STM32_RCC_D2CCIP2R_USBSRC;
putreg32(regval, STM32_RCC_D2CCIP2R);
#endif
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
/* Low speed internal clock source LSI */

4
configs/nucleo-f207zg/src/Makefile
View File

@ -48,6 +48,10 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += stm32_buttons.c
endif
ifeq ($(CONFIG_STM32_OTGFS),y)
CSRCS += stm32_usb.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
CSRCS += stm32_appinitialize.c
endif

23
configs/nucleo-f207zg/src/nucleo-f207zg.h
View File

@ -84,6 +84,29 @@
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
/* USB OTG FS
*
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
* PG6 OTG_FS_PowerSwitchOn
* PG7 OTG_FS_Overcurrent
*/
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
#ifdef CONFIG_USBHOST
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
GPIO_SPEED_100MHz|GPIO_PUSHPULL| \
GPIO_PORTG|GPIO_PIN7)
#else
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
#endif
/* PWM */
#define NUCLEOF207ZG_PWMTIMER 1

6
configs/nucleo-f207zg/src/stm32_boot.c
View File

@ -69,6 +69,12 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST)
/* Initialize USB */
stm32_usbinitialize();
#endif
}
/****************************************************************************

12
configs/nucleo-f207zg/src/stm32_bringup.c
View File

@ -92,6 +92,18 @@ int stm32_bringup(void)
}
#endif
#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
/* Initialize CDCACM */
syslog(LOG_INFO, "Initialize CDCACM device\n");
ret = cdcacm_initialize(0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret);
}
#endif
UNUSED(ret);
return OK;
}

331
configs/nucleo-f207zg/src/stm32_usb.c Normal file
View File

@ -0,0 +1,331 @@
/************************************************************************************
* configs/nucleo-f207zg/src/stm32_usb.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_otgfs.h"
#include "nucleo-f207zg.h"
#ifdef CONFIG_STM32_OTGFS
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
# define HAVE_USB 1
#else
# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
# undef HAVE_USB
#endif
#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO
# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100
#endif
#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE
# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024
#endif
/************************************************************************************
* Private Data
************************************************************************************/
#ifdef CONFIG_USBHOST
static struct usbhost_connection_s *g_usbconn;
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: usbhost_waiter
*
* Description:
* Wait for USB devices to be connected.
*
************************************************************************************/
#ifdef CONFIG_USBHOST
static int usbhost_waiter(int argc, char *argv[])
{
struct usbhost_hubport_s *hport;
uinfo("Running\n");
for (;;)
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
(void)CONN_ENUMERATE(g_usbconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup USB-related
* GPIO pins for the nucleo-144 board.
*
************************************************************************************/
void stm32_usbinitialize(void)
{
/* The OTG FS has an internal soft pull-up. No GPIO configuration is required */
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32_OTGFS
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/***********************************************************************************
* Name: stm32_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
***********************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_usbhost_initialize(void)
{
int pid;
#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \
defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE)
int ret;
#endif
/* First, register all of the class drivers needed to support the drivers
* that we care about:
*/
uinfo("Register class drivers\n");
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub class support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB mass storage class class */
ret = usbhost_msc_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Initialize the HID keyboard class */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID keyboard class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDMOUSE
/* Initialize the HID mouse class */
ret = usbhost_mouse_init();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID mouse class\n");
}
#endif
/* Then get an instance of the USB host interface */
uinfo("Initialize USB host\n");
g_usbconn = stm32_otgfshost_initialize(0);
if (g_usbconn)
{
/* Start a thread to handle device connection. */
uinfo("Start usbhost_waiter\n");
pid = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO,
CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE,
(main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
return -ENODEV;
}
#endif
/***********************************************************************************
* Name: stm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be
* each platform that implements the STM32 OTG FS host interface
*
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
* or, if 5 V are available on the application board, a basic power switch, must
* be added externally to drive the 5 V VBUS line. The external charge pump can
* be driven by any GPIO output. When the application decides to power on VBUS
* using the chosen GPIO, it must also set the port power bit in the host port
* control and status register (PPWR bit in OTG_FS_HPRT).
*
* "The application uses this field to control power to this port, and the core
* clears this bit on an overcurrent condition."
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
***********************************************************************************/
#ifdef CONFIG_USBHOST
void stm32_usbhost_vbusdrive(int iface, bool enable)
{
DEBUGASSERT(iface == 0);
/* Set the Power Switch by driving the active low enable pin */
stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
}
#endif
/************************************************************************************
* Name: stm32_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
* Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
************************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
{
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
}
#endif
/************************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
* used. This function is called whenever the USB enters or leaves suspend mode.
* This is an opportunity for the board logic to shutdown clocks, power, etc.
* while the USB is suspended.
*
************************************************************************************/
#ifdef CONFIG_USBDEV
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
{
uinfo("resume: %d\n", resume);
}
#endif
#endif /* CONFIG_STM32_OTGFS */

12
configs/nucleo-h743zi/include/board.h
View File

@ -111,9 +111,9 @@
*
* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
*
* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
*/
#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
@ -212,7 +212,7 @@
#define STM32_RCC_D2CCIP3R_I2C4SRC RCC_D2CCIP3R_I2C4SEL_HSI
/* SPI123 clock source - PLL1 */
/* SPI123 clock source - PLL1Q */
#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
@ -224,6 +224,10 @@
#define STM32_RCC_D3CCIP1R_SPI6SRC RCC_D3CCIP1R_SPI6SEL_PCLK4
/* USB 1 and 2 clock source - HSI48 */
#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
/* FLASH wait states
*
* ------------ ---------- -----------

4
configs/nucleo-h743zi/src/Makefile
View File

@ -52,6 +52,10 @@ ifeq ($(CONFIG_STM32H7_SPI),y)
CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32H7_OTGFS),y)
CSRCS += stm32_usb.c
endif
ifeq ($(CONFIG_SENSORS_LSM6DSL),y)
CSRCS += stm32_lsm6dsl.c
endif

45
configs/nucleo-h743zi/src/nucleo-h743zi.h
View File

@ -49,6 +49,16 @@
* Pre-processor Definitions
************************************************************************************/
/* procfs File System */
#ifdef CONFIG_FS_PROCFS
# ifdef CONFIG_NSH_PROC_MOUNTPOINT
# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
# else
# define STM32_PROCFS_MOUNTPOINT "/proc"
# endif
#endif
/* Configuration ********************************************************************/
/* LED
*
@ -82,6 +92,29 @@
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
/* USB OTG FS
*
* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
* PG6 OTG_FS_PowerSwitchOn
* PG7 OTG_FS_Overcurrent
*/
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
#ifdef CONFIG_USBHOST
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
GPIO_SPEED_100MHz|GPIO_PUSHPULL| \
GPIO_PORTG|GPIO_PIN7)
#else
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
#endif
/* X-NUCLEO IKS01A2 */
#define GPIO_LPS22HB_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10)
@ -146,6 +179,18 @@ void stm32_spidev_initialize(void);
int stm32_adc_setup(void);
#endif
/************************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup USB-related
* GPIO pins for the nucleo-144 board.
*
************************************************************************************/
#ifdef CONFIG_STM32H7_OTGFS
void stm32_usbinitialize(void);
#endif
/*****************************************************************************
* Name: stm32_lsm6dsl_initialize

6
configs/nucleo-h743zi/src/stm32_boot.c
View File

@ -70,6 +70,12 @@ void stm32_boardinitialize(void)
board_autoled_initialize();
#endif
#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST)
/* Initialize USB */
stm32_usbinitialize();
#endif
#ifdef CONFIG_STM32H7_SPI
/* Configure SPI chip selects */

12
configs/nucleo-h743zi/src/stm32_bringup.c
View File

@ -138,5 +138,17 @@ int stm32_bringup(void)
}
#endif /* CONFIG_WL_NRF24L01 */
#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE)
/* Initialize CDCACM */
syslog(LOG_INFO, "Initialize CDCACM device\n");
ret = cdcacm_initialize(0, NULL);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret);
}
#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */
return OK;
}

331
configs/nucleo-h743zi/src/stm32_usb.c Normal file
View File

@ -0,0 +1,331 @@
/************************************************************************************
* configs/nucleo-h743zi/src/stm32_usb.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include "up_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_otg.h"
#include "nucleo-h743zi.h"
#ifdef CONFIG_STM32H7_OTGFS
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
# define HAVE_USB 1
#else
# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
# undef HAVE_USB
#endif
#ifndef CONFIG_NUCLEOH743ZI_USBHOST_PRIO
# define CONFIG_NUCLEOH743ZI_USBHOST_PRIO 100
#endif
#ifndef CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE
# define CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE 1024
#endif
/************************************************************************************
* Private Data
************************************************************************************/
#ifdef CONFIG_USBHOST
static struct usbhost_connection_s *g_usbconn;
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: usbhost_waiter
*
* Description:
* Wait for USB devices to be connected.
*
************************************************************************************/
#ifdef CONFIG_USBHOST
static int usbhost_waiter(int argc, char *argv[])
{
struct usbhost_hubport_s *hport;
uinfo("Running\n");
for (;;)
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
(void)CONN_ENUMERATE(g_usbconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
#endif
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: stm32_usbinitialize
*
* Description:
* Called from stm32_usbinitialize very early in inialization to setup USB-related
* GPIO pins for the nucleo-144 board.
*
************************************************************************************/
void stm32_usbinitialize(void)
{
/* The OTG FS has an internal soft pull-up. No GPIO configuration is required */
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
#ifdef CONFIG_STM32H7_OTGFS
stm32_configgpio(GPIO_OTGFS_VBUS);
stm32_configgpio(GPIO_OTGFS_PWRON);
stm32_configgpio(GPIO_OTGFS_OVER);
#endif
}
/***********************************************************************************
* Name: stm32_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
***********************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_usbhost_initialize(void)
{
int pid;
#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \
defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE)
int ret;
#endif
/* First, register all of the class drivers needed to support the drivers
* that we care about:
*/
uinfo("Register class drivers\n");
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub class support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB mass storage class class */
ret = usbhost_msc_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Initialize the HID keyboard class */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID keyboard class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDMOUSE
/* Initialize the HID mouse class */
ret = usbhost_mouse_init();
if (ret != OK)
{
uerr("ERROR: Failed to register the HID mouse class\n");
}
#endif
/* Then get an instance of the USB host interface */
uinfo("Initialize USB host\n");
g_usbconn = stm32_otgfshost_initialize(0);
if (g_usbconn)
{
/* Start a thread to handle device connection. */
uinfo("Start usbhost_waiter\n");
pid = kthread_create("usbhost", CONFIG_NUCLEOH743ZI_USBHOST_PRIO,
CONFIG_NUCLEOH743ZI_USBHOST_STACKSIZE,
(main_t)usbhost_waiter, (FAR char * const *)NULL);
return pid < 0 ? -ENOEXEC : OK;
}
return -ENODEV;
}
#endif
/***********************************************************************************
* Name: stm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be
* each platform that implements the STM32 OTG FS host interface
*
* "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump
* or, if 5 V are available on the application board, a basic power switch, must
* be added externally to drive the 5 V VBUS line. The external charge pump can
* be driven by any GPIO output. When the application decides to power on VBUS
* using the chosen GPIO, it must also set the port power bit in the host port
* control and status register (PPWR bit in OTG_FS_HPRT).
*
* "The application uses this field to control power to this port, and the core
* clears this bit on an overcurrent condition."
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
***********************************************************************************/
#ifdef CONFIG_USBHOST
void stm32_usbhost_vbusdrive(int iface, bool enable)
{
DEBUGASSERT(iface == 0);
/* Set the Power Switch by driving the active low enable pin */
stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable);
}
#endif
/************************************************************************************
* Name: stm32_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition is
* detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument provided for the interrupt handler
*
* Returned Value:
* Zero (OK) is returned on success. Otherwise, a negated errno value is returned
* to indicate the nature of the failure.
*
************************************************************************************/
#ifdef CONFIG_USBHOST
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
{
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
}
#endif
/************************************************************************************
* Name: stm32_usbsuspend
*
* Description:
* Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is
* used. This function is called whenever the USB enters or leaves suspend mode.
* This is an opportunity for the board logic to shutdown clocks, power, etc.
* while the USB is suspended.
*
************************************************************************************/
#ifdef CONFIG_USBDEV
void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
{
uinfo("resume: %d\n", resume);
}
#endif
#endif /* CONFIG_STM32_OTGFS */

2
configs/teensy-3.x/usbnsh/defconfig
View File

@ -62,7 +62,7 @@ CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USBDEV=y
CONFIG_USBDEV_BUSPOWERED=y
CONFIG_USBDEV_TRACE=y
CONFIG_USBDEV_TRACE_INITIALIDSET=y
CONFIG_USBDEV_TRACE_INITIALIDSET=0xff
CONFIG_USBMONITOR=y
CONFIG_USBMONITOR_TRACECLASS=y
CONFIG_USBMONITOR_TRACECONTROLLER=y

2
drivers/usbdev/Kconfig
View File

@ -119,7 +119,7 @@ config USBDEV_TRACE_STRINGS
#endif
config USBDEV_TRACE_INITIALIDSET
bool "Initial enable bits"
int "Initial enable bits"
default 0
---help---
This is the set of initial USB features that are enabled at boot