LPC23xx: Several fixes for typos from Lizhuoyi
This commit is contained in:
Gregory Nutt
parent
c40c8d1924
commit
2d3f0f01a0
@ -130,22 +130,27 @@ config LPC2378_UART2
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default n
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select ARCH_HAVE_UART2
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config LPC2378_UART3
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bool "UART3"
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default n
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select ARCH_HAVE_UART3
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config LPC2378_USBDEV
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bool "USB Device"
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default n
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depends on USBDEV
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config LPC2378_IC0
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config LPC2378_I2C0
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bool "I2C0"
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default n
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select I2C
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config LPC2378_IC1
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config LPC2378_I2C1
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bool "I2C1"
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default n
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select I2C
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config LPC2378_IC2
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config LPC2378_I2C2
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bool "I2C2"
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default n
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select I2C
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@ -121,7 +121,9 @@
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#define TMR1_BASE_ADDR 0xE0008000
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#define TMR2_BASE_ADDR 0xE0070000
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#define TMR3_BASE_ADDR 0xE0074000
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/* Timer 0/1/2/3 register offsets */
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#define TMR_IR_OFFSET 0x00 /* RW:Interrupt Register */
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#define TMR_TCR_OFFSET 0x04 /* RW: Timer Control Register */
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#define TMR_TC_OFFSET 0x08 /* RW: Timer Counter */
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@ -141,11 +143,14 @@
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#define TMR_CTCR_OFFSET 0x70 /* RW: Count Control Register */
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/* Universal Asynchronous Receiver Transmitter Base Addresses */
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#define UART0_BASE_ADDR 0xE000C000
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#define UART1_BASE_ADDR 0xE0010000
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#define UART2_BASE_ADDR 0xE0078000
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#define UART3_BASE_ADDR 0xE007C000
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/* UART 0/1/2/3 Register Offsets */
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#define UART_RBR_OFFSET 0x00 /* R: Receive Buffer Register (DLAB=0) */
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#define UART_THR_OFFSET 0x00 /* W: Transmit Holding Register (DLAB=0) */
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#define UART_DLL_OFFSET 0x00 /* W: Divisor Latch Register (LSB, DLAB=1) */
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@ -162,10 +167,12 @@
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#define UART_FDR_OFFSET 0x28 /* RW: Fractional Divider Register */
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#define UART_TER_OFFSET 0x30 /* RW: Transmit Enable Register */
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/* Pulse Width Modulation Base Address */
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#define PWM1_BASE_ADDR 0xE0018000
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/* PWM register offsets */
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#define PWM_IR_OFFSET 0x00 /* Interrupt Register */
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#define PWM_TCR_OFFSET 0x04 /* Timer Control Register */
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#define PWM_TC_OFFSET 0x08 /* Timer Counter */
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@ -190,10 +197,13 @@
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#define PWM_CTCR_OFFSET 0x70
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/* I2C Base Addresses */
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#define I2C0_BASE_ADDR 0xE001C000
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#define I2C1_BASE_ADDR 0xE005C000
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#define I2C2_BASE_ADDR 0xE0080000
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/* I2C 0/1/2 register offsets */
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#define I2C_CONSET_OFFSET 0x00 /* Control Set Register */
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#define I2C_STAT_OFFSET 0x04 /* Status Register */
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#define I2C_DAT_OFFSET 0x08 /* Data Register */
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@ -216,12 +226,11 @@
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#define PINSEL9_OFFSET 0x24 /* Pin function select register 9 */
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#define PINSEL10_OFFSET 0x28 /* Pin function select register 10 */
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/* Analog to Digital (AD) Base Address */
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#define ADC0_BASE_ADDR 0xE0034000
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/* Analog to Digital (AD) Converter registger offsets */
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/* Analog to Digital (AD) Converter register offsets */
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#define AD_ADCR_OFFSET 0x00 /* A/D Control Register */
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#define AD_ADGDR_OFFSET 0x04 /* A/D Global Data Register (only one common register!) */
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@ -242,6 +251,7 @@
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#define DAC_BASE_ADDR 0xE006C000
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/* Digital to Analog (DAC) reister offset */
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//#define DACR_OFFSET 0x00
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/* SPI0 register offsets */
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@ -267,9 +277,12 @@
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//~ #define SPI1_ICR_OFFSET 0x20 /* Interrupt Clear Register */
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/* SSP Base Addresses */
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#define SSP0_BASE_ADDR 0xE0068000
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#define SSP1_BASE_ADDR 0xE0030000
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/* SSP 0/1 register offsets */
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#define SSP_CR0_OFFSET 0x00 /* Control Register 0 */
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#define SSP_CR1_OFFSET 0x04 /* Control Register 1 */
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#define SSP_DR_OFFSET 0x08 /* Data Register */
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@ -282,8 +295,11 @@
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#define SSP_DMACR_OFFSET 0x24 /* DMA Control Register */
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/* Real Time Clock Base Address */
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#define RTC_BASE_ADDR 0xE0024000
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/* RTC register offsets */
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#define RTC_ILR_OFFSET 0x00 /* Interrupt Location Register */
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#define RTC_CTC_OFFSET 0x04 /* Clock Tick Counter */
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#define RTC_CCR_OFFSET 0x08 /* Clock Control Register */
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@ -312,9 +328,9 @@
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#define RTC_PREINT_OFFSET 0x80 /* Prescale Value Register (integer) */
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#define RTC_PREFRAC_OFFSET 0x84 /* Prescale Value Register (fraction) */
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/* Watchdog */
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//~ WDG_BASE_ADDR 0xE0000000
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#define WDMOD_OFFSET 0x00
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#define WDTC_OFFSET 0x04
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#define WDFEED_OFFSET 0x08
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@ -323,6 +339,7 @@
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/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
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//~ CAN_ACCEPT_BASE_ADDR 0xE003C000
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#define CAN_AFMR_OFFSET 0x00
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#define CAN_SFF_SA_OFFSET 0x04
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#define CAN_SFF_GRP_SA_OFFSET 0x08
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@ -392,8 +409,9 @@
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#define CAN2TDB3_OFFSET 0x5C
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/* MultiMedia Card Interface(MCI) Controller */
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/* MultiMedia Card Interface(MCI) ontroller */
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//~ MCI_BASE_ADDR 0xE008C000
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#define MCI_POWER_OFFSET 0x00
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#define MCI_CLOCK_OFFSET 0x04
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#define MCI_ARGUMENT_OFFSET 0x08
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@ -430,6 +448,7 @@
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/* General-purpose DMA Controller */
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/* DMA_BASE_ADDR 0xFFE04000 */
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#define GPDMA_INT_STAT_OFFSET 0x4000
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#define GPDMA_INT_TCSTAT_OFFSET 0x4004
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#define GPDMA_INT_TCCLR_OFFSET 0x4008
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@ -443,26 +462,31 @@
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#define GPDMA_SOFT_LBREQ_OFFSET 0x4028
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#define GPDMA_SOFT_LSREQ_OFFSET 0x402C
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#define GPDMA_CONFIG_OFFSET 0x4030
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#define GPDMA_SYNC_OFFSET 0x4034
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#define GPDMA_SYNC_OFFSET 0x0x4034
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/* DMA channel 0 registers */
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#define GPDMA_CH0_SRC_OFFSET 0x4100
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#define GPDMA_CH0_DEST_OFFSET 0x4104
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#define GPDMA_CH0_LLI_OFFSET 0x4108
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#define GPDMA_CH0_CTRL_OFFSET 0x410C
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#define GPDMA_CH0_CFG_OFFSET 0x4110
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/* DMA channel 1 registers */
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#define GPDMA_CH1_SRC_OFFSET 0x4120
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#define GPDMA_CH1_DEST_OFFSET 0x4124
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#define GPDMA_CH1_LLI_OFFSET 0x4128
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#define GPDMA_CH1_CTRL_OFFSET 0x412C
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#define GPDMA_CH1_CFG_OFFSET 0x4130
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/* USB Controller */
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#define USB_INT_BASE_ADDR 0xE01FC1C0
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#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
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/* USB Device Interrupt Registers */
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#define USB_INT_STAT_OFFSET 0x00
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#define USB_INT_EN_OFFSET 0x04
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#define USB_INT_CLR_OFFSET 0x08
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@ -477,15 +501,18 @@
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#define USB_EP_INT_PRIO_OFFSET 0x40
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/* USB Device Endpoint Realization Registers */
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#define USB_REALIZE_EP_OFFSET 0x44
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#define USB_EP_INDEX_OFFSET 0x48
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#define USB_MAXPACKET_SIZE_OFFSET 0x4C
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/* USB Device Command Reagisters */
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#define USB_CMD_CODE_OFFSET 0x10
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#define USB_CMD_DATA_OFFSET 0x14
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/* USB Device Data Transfer Registers */
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#define USB_RX_DATA_OFFSET 0x18
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#define USB_TX_DATA_OFFSET 0x1C
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#define USB_RX_PLENGTH_OFFSET 0x20
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@ -493,6 +520,7 @@
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#define USB_USB_CTRL_OFFSET 0x28
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/* USB Device DMA Registers */
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#define USB_DMA_REQ_STAT_OFFSET 0x50
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#define USB_DMA_REQ_CLR_OFFSET 0x54
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#define USB_DMA_REQ_SET_OFFSET 0x58
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@ -513,24 +541,33 @@
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#define USB_SYS_ERR_INT_SET_OFFSET 0xC0
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/* System Control Block(SCB) modules include Memory Accelerator Module,
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Phase Locked Loop, VPB divider, Power Control, External Interrupt,
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Reset, and Code Security/Debugging */
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* Phase Locked Loop, VPB divider, Power Control, External Interrupt,
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* Reset, and Code Security/Debugging
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*/
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#define SCB_BASE_ADDR 0xE01FC000
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/* Memory Accelerator Module (MAM) Regiser */
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#define SCB_MAMCR (*(volatile uint32_t*)(0xE01FC000))
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#define SCB_MAMTIM (*(volatile uint32_t*)(0xE01FC004))
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#define SCB_MEMMAP (*(volatile uint32_t*)(0xE01FC040))
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/* Phase Locked Loop (PLL) Register */
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#define SCB_PLLCON (*(volatile uint32_t*)(0xE01FC080))
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#define SCB_PLLCFG (*(volatile uint32_t*)(0xE01FC084))
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#define SCB_PLLSTAT (*(volatile uint32_t*)(0xE01FC088))
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#define SCB_PLLFEED (*(volatile uint32_t*)(0xE01FC08C))
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/* Power Control register */
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#define SCB_PCON (*(volatile uint32_t*)(0xE01FC0C0))
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#define SCB_PCONP (*(volatile uint32_t*)(0xE01FC0C4))
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#define SCB_PCONP_OFFSET 0x0C4
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/* Clock Divider Register */
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#define SCB_CCLKCFG (*(volatile uint32_t*)(0xE01FC104))
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#define SCB_USBCLKCFG (*(volatile uint32_t*)(0xE01FC108))
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#define SCB_CLKSRCSEL (*(volatile uint32_t*)(0xE01FC10C))
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@ -538,24 +575,31 @@ Reset, and Code Security/Debugging */
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#define SCB_PCLKSEL1 (*(volatile uint32_t*)(0xE01FC1AC))
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#define SCB_PCLKSEL0_OFFSET (0x1A8)
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#define SCB_PCLKSEL1_OFFSET (0x1AC)
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/* External Interrupt register */
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#define SCB_EXTINT (*(volatile uint32_t*)(0xE01FC140))
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#define SCB_INTWAKE (*(volatile uint32_t*)(0xE01FC144))
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#define SCB_EXTMODE (*(volatile uint32_t*)(0xE01FC148))
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#define SCB_EXTPOLAR (*(volatile uint32_t*)(0xE01FC14C))
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/* Reser Source Indentification register */
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/* Reser Source Identification register */
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#define SCB_RSIR (*(volatile uint32_t*)(0xE01FC180))
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/* RSID, code security protection */
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#define SCB_CSPR (*(volatile uint32_t*)(0xE01FC184))
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#define SCB_AHBCFG1 (*(volatile uint32_t*)(0xE01FC188))
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#define SCB_AHBCFG2 (*(volatile uint32_t*)(0xE01FC18C))
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/* System Controls and Status Register */
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#define SCB_SCS (*(volatile uint32_t*)(0xE01FC1A0))
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//~ /* External Memory Controller (EMC) definitions */
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/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
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are for LPC24xx only. */
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#define STATIC_MEM0_BASE 0x80000000
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@ -570,6 +614,7 @@ are for LPC24xx only. */
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/* External Memory Controller (EMC) */
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//~ #define EMC_BASE_ADDR 0xFFE08000
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#define EMC_CTRL_OFFSET 0x000
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#define EMC_STAT_OFFSET 0x004
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#define EMC_CONFIG_OFFSET 0x008
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@ -600,6 +645,7 @@ are for LPC24xx only. */
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#define EMC_DYN_RASCAS3_OFFSET 0x184
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/* static RAM access registers */
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#define EMC_STA_CFG0_OFFSET 0x200
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#define EMC_STA_WAITWEN0_OFFSET 0x204
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#define EMC_STA_WAITOEN0_OFFSET 0x208
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@ -624,7 +670,7 @@ are for LPC24xx only. */
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#define EMC_STA_WAITWR2_OFFSET 0x254
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#define EMC_STA_WAITTURN2_OFFSET 0x258
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#define EMC_STA_CFG3 0x260
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#define EMC_STA_CFG3_OFFSET 0x260
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#define EMC_STA_WAITWEN3_OFFSET 0x264
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#define EMC_STA_WAITOEN3_OFFSET 0x268
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#define EMC_STA_WAITRD3_OFFSET 0x26C
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@ -635,6 +681,7 @@ are for LPC24xx only. */
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#define EMC_STA_EXT_WAIT_OFFSET 0x880
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/* GPIO register offsets WORD access */
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#define GPIO0_PIN_OFFSET 0x00 /* Pin Value Register */
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#define GPIO0_SET_OFFSET 0x04 /* Pin Output Set Register */
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#define GPIO0_DIR_OFFSET 0x08 /* Pin Direction Register */
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@ -645,8 +692,11 @@ are for LPC24xx only. */
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#define GPIO1_CLR_OFFSET 0x1c /* Pin Output Clear Register */
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/* Fast I0 Base Address */
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#define FIO_BASE_ADDR 0x3FFFC000
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/* FIO register offsets WORD access */
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#define FIO0_DIR_OFFSET 0x00 /* Fast GPIO Port Direction Register */
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#define FIO0_MASK_OFFSET 0x10 /* Fast GPIO Mask Register */
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#define FIO0_PIN_OFFSET 0x14 /* Fast GPIO Pin Value Register */
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@ -677,7 +727,6 @@ are for LPC24xx only. */
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#define FIO4_SET_OFFSET 0x98 /* Fast GPIO Port Output Set Register */
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#define FIO4_CLR_OFFSET 0x9c /* Fast GPIO Port Output Clear Register */
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/* FIO register offsets HALF-WORD access */
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#define FIO0MASKL_OFFSET 0x10 /* Fast IO Mask Lower HALF-WORD */
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@ -740,7 +789,6 @@ are for LPC24xx only. */
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#define FIO3DIRU_OFFSET 0x62
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#define FIO4DIRU_OFFSET 0x82
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/* FIO register offsets BYTE access */
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#define FIO0DIR0_OFFSET 0x00
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@ -876,7 +924,6 @@ are for LPC24xx only. */
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#define VIC_PROTECTION_OFFSET 0x020 /* Protection Enable Register */
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#define VIC_PRIORITY_MASK_OFFSET 0x024 /* Priority Mask Register */
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//~ #define LPC23XX_VIC_BASE 0xfffff000 /* Vectored Interrupt Controller (VIC) Base */
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#define VIC_ADDRESS_OFFSET 0xF00 /* RW: Vector Address Register */
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@ -913,8 +960,8 @@ are for LPC24xx only. */
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#define VIC_VECTADDR30_OFFSET 0x178 /* RW: Vector Address 30 Register */
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#define VIC_VECTADDR31_OFFSET 0x17c /* RW: Vector Address 31 Register */
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/*VICVectPriority */
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#define VIC_VECTPRIORITY0_OFFSET 0x200 /* RW: Vector Control 0 Register */
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#define VIC_VECTPRIORITY1_OFFSET 0x204 /* RW: Vector Control 1 Register */
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#define VIC_VECTPRIORITY2_OFFSET 0x208 /* RW: Vector Control 2 Register */
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@ -377,7 +377,7 @@ static int i2c_interrupt (int irq, FAR void *context)
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/* Reference UM10360 19.10.5 */
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uint32_t state = getreg32(priv->base + I2C_STAT_OFFSET);
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putreg32(I2C_CONCLR_SIC, priv->base + 2C_CONCLR_OFFSET);
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putreg32(I2C_CONCLR_SIC, priv->base + I2C_CONCLR_OFFSET);
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priv->state = state;
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state &= 0xf8;
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