sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

STM32F107 OTG FS clock presecaler cannot be configurated after the USB clock is enabled

Browse Source
This commit is contained in:
Gregory Nutt 2013-12-26 10:45:21 -06:00
parent 515fad9616
commit 2d92d7825d
2 changed files with 21 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
View File

@ -164,7 +164,10 @@
# define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */ # define RCC_CFGR_PLLMUL_CLKx15 (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
# define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */ # define RCC_CFGR_PLLMUL_CLKx16 (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
#ifndef CONFIG_STM32_VALUELINE #ifndef CONFIG_STM32_VALUELINE
# define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB/OTG FS prescaler */ # define RCC_CFGR_USBPRE (1 << 22) /* Bit 22: USB FS prescaler */
#endif
#ifdef CONFIG_STM32_CONNECTIVITYLINE
# define RCC_CFGR_OTGFSPRE (1 << 22) /* Bit 22: OTG FS prescaler */
#endif #endif
#define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */ #define RCC_CFGR_MCO_SHIFT (24) /* Bits 27-24: Microcontroller Clock Output */
#define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT) #define RCC_CFGR_MCO_MASK (15 << RCC_CFGR_MCO_SHIFT)

25
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@ -114,6 +114,18 @@ static inline void rcc_enableahb(void)
{ {
uint32_t regval; uint32_t regval;
#if defined(CONFIG_STM32_CONNECTIVITYLINE) && defined(CONFIG_STM32_OTGFS)
/* USB clock divider for USB OTG FS. This bit must be valid before
* enabling the USB clock in the RCC_AHBENR register. This bit can't be
* reset if the USB clock is enabled.
*/
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_OTGFSPRE;
regval |= STM32_CFGR_OTGFSPRE;
putreg32(regval, STM32_RCC_CFGR);
#endif
/* Always enable FLITF clock and SRAM clock */ /* Always enable FLITF clock and SRAM clock */
regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN; regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN;
@ -176,16 +188,13 @@ static inline void rcc_enableahb(void)
static inline void rcc_enableapb1(void) static inline void rcc_enableapb1(void)
{ {
uint32_t regval; uint32_t regval;
#ifdef CONFIG_STM32_USB
#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_OTGFS) /* USB clock divider for USB FS device. This bit must be valid before
/* USB clock divider for USB FD device or USB OTG FS (OTGFS naming for this * enabling the USB clock in the RCC_APB1ENR register. This bit can't be
* bit is different, but it is the same bit. * reset if the USB clock is enabled.
*
* This bit must be valid before enabling the either the USB clock in the
* RCC_APB1ENR register ro the OTG FS clock in the AHBENR reigser. This
* bit can’t be reset if the USB clock is enabled.
*/ */
regval = getreg32(STM32_RCC_CFGR); regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_USBPRE; regval &= ~RCC_CFGR_USBPRE;
regval |= STM32_CFGR_USBPRE; regval |= STM32_CFGR_USBPRE;