Adding LPC315x support to header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3645 42af7a65-404d-4744-a932-0658087f49c3
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@ -67,7 +67,7 @@
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#define LPC31_IRQ_I2STX1 13 /* IRQ14: I2S1 Transmit */
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#define LPC31_IRQ_I2SRX0 14 /* IRQ15: I2S0 Receive */
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#define LPC31_IRQ_I2SRX1 15 /* IRQ16: I2S1 Receive */
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/* IRQ17: Reserved */
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/* IRQ17: Reserved */
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#define LPC31_IRQ_LCD 17 /* IRQ18: LCD Interface */
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#define LPC31_IRQ_SPISMS 18 /* IRQ19: SPI SMS */
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#define LPC31_IRQ_SPITX 19 /* IRQ20: SPI Transmit */
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/lpc31xx/chip.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -47,6 +47,30 @@
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* Pre-processor Definitions
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************************************************************************************/
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#if defined(CONFIG_ARCH_CHIP_LPC3130)
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# undef HAVE_INTSRAM1 /* 96Kb internal SRAM */
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# define LPC31_NDMACH 12 /* 12 DMA channels */
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# undef HAVE_AESENGINE /* No AES engine */
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#elif defined(CONFIG_ARCH_CHIP_LPC3131)
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# define HAVE_INTSRAM1 1 /* 192Kb internal SRAM */
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# define LPC31_NDMACH 12 /* 12 DMA channels */
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# undef HAVE_AESENGINE /* No AES engine */
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#elif defined(CONFIG_ARCH_CHIP_LPC3152)
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# define HAVE_INTSRAM1 1 /* 192Kb internal SRAM */
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# define LPC31_NDMACH 12 /* 12 DMA channels */
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# undef HAVE_AESENGINE /* No AES engine */
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#elif defined(CONFIG_ARCH_CHIP_LPC3152)
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# define HAVE_INTSRAM1 1 /* 192Kb internal SRAM */
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# define LPC31_NDMACH 12 /* 12 DMA channels */
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# define HAVE_AESENGINE 1 /* AES engine */
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# undef HAVE_AESENGINE /* No AES engine */
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#else
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# error "Unsupported LPC31XX architecture"
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# undef HAVE_INTSRAM1 /* No INTSRAM1 */
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# define LPC31_NDMACH 0 /* No DMA channels */
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# undef HAVE_AESENGINE /* No AES engine */
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -1,7 +1,7 @@
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/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_dma.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -41,6 +41,8 @@
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lpc31_memorymap.h"
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/************************************************************************************************
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@ -68,19 +70,19 @@
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#define LPC31_DMACHAN10_OFFSET 0x140
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#define LPC31_DMACHAN11_OFFSET 0x160
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#define LPC31_DMACHAN_ALT_OFFSET(n) (0x200+((n)*0x020))
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#define LPC31_DMACHAN_ALT_OFFSET(n) (0x200+((n)*0x010))
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#define LPC31_DMACHAN0_ALT_OFFSET 0x200
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#define LPC31_DMACHAN1_ALT_OFFSET 0x220
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#define LPC31_DMACHAN2_ALT_OFFSET 0x240
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#define LPC31_DMACHAN3_ALT_OFFSET 0x260
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#define LPC31_DMACHAN4_ALT_OFFSET 0x280
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#define LPC31_DMACHAN5_ALT_OFFSET 0x2a0
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#define LPC31_DMACHAN6_ALT_OFFSET 0x2c0
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#define LPC31_DMACHAN7_ALT_OFFSET 0x2e0
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#define LPC31_DMACHAN8_ALT_OFFSET 0x300
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#define LPC31_DMACHAN9_ALT_OFFSET 0x320
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#define LPC31_DMACHAN10_ALT_OFFSET 0x340
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#define LPC31_DMACHAN11_ALT_OFFSET 0x360
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#define LPC31_DMACHAN1_ALT_OFFSET 0x210
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#define LPC31_DMACHAN2_ALT_OFFSET 0x220
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#define LPC31_DMACHAN3_ALT_OFFSET 0x230
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#define LPC31_DMACHAN4_ALT_OFFSET 0x240
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#define LPC31_DMACHAN5_ALT_OFFSET 0x250
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#define LPC31_DMACHAN6_ALT_OFFSET 0x260
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#define LPC31_DMACHAN7_ALT_OFFSET 0x270
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#define LPC31_DMACHAN8_ALT_OFFSET 0x280
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#define LPC31_DMACHAN9_ALT_OFFSET 0x290
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#define LPC31_DMACHAN10_ALT_OFFSET 0x2a0
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#define LPC31_DMACHAN11_ALT_OFFSET 0x2b0
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/* DMA channel virtual base addresses ***********************************************************/
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@ -41,6 +41,7 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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@ -50,37 +51,37 @@
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#define LPC31_FIRST_PSECTION 0x00000000 /* Beginning of the physical address space */
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#define LPC31_SHADOWSPACE_PSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
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/* 0x00001000-0xff027fff: Reserved */
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/* 0x00001000-0xff027fff: Reserved */
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#define LPC31_INTSRAM_PSECTION 0x11028000 /* Internal SRAM 0+1 192Kb */
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# define LPC31_INTSRAM0_PADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
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# define LPC31_INTSRAM1_PADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
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/* 0x11058000-11ffffffff: Reserved */
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/* 0x11058000-11ffffffff: Reserved */
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#define LPC31_INTSROM0_PSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
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/* 0x12020000-0x12ffffff: Reserved */
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/* 0x12020000-0x12ffffff: Reserved */
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#define LPC31_APB01_PSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB1 16Kb */
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# define LPC31_APB0_PADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
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# define LPC31_APB1_PADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
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/* 0x1300c000-0x14ffffff: Reserved */
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/* 0x1300c000-0x14ffffff: Reserved */
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#define LPC31_APB2_PSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
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#define LPC31_APB3_PSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
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#define LPC31_APB4MPMC_PSECTION 0x17000000 /* 8Kb */
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# define LPC31_APB4_PADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
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# define LPC31_MPMC_PADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
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/* 0x17009000-0x17ffffff: Reserved */
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/* 0x17009000-0x17ffffff: Reserved */
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#define LPC31_MCI_PSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
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/* 0x18000900-0x18ffffff: Reserved */
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/* 0x18000900-0x18ffffff: Reserved */
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#define LPC31_USBOTG_PSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
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/* 0x19001000-0x1fffffff: Reserved */
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/* 0x19001000-0x1fffffff: Reserved */
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#define LPC31_EXTSRAM_PSECTION 0x20000000 /* 64-128Kb */
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# define LPC31_EXTSRAM0_PADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
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# define LPC31_EXTSRAM1_PADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
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#define LPC31_EXTSDRAM0_PSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
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/* 0x40000000-0x5fffffff: Reserved */
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/* 0x40000000-0x5fffffff: Reserved */
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#define LPC31_INTC_PSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
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/* 0x60001000-0x6fffffff: Reserved */
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/* 0x60001000-0x6fffffff: Reserved */
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#define LPC31_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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/* 0x70000800-0xffffffff: Reserved */
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#ifdef CONFIG_LPC31_EXTNAND /* End of the physical address space */
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/* 0x70000800-0xffffffff: Reserved */
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#ifdef CONFIG_LPC31_EXTNAND /* End of the physical address space */
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# define LPC31_LAST_PSECTION (LPC31_NAND_PSECTION + (1 << 20))
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#else
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# define LPC31_LAST_PSECTION (LPC31_INTC_PSECTION + (1 << 20))
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@ -94,7 +95,7 @@
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#define LPC31_APB0_SYSCREG_OFFSET 0x00002800 /* SYSCREG block */
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#define LPC31_APB0_IOCONFIG_OFFSET 0x00003000 /* IOCONFIG */
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#define LPC31_APB0_GCU_OFFSET 0x00004000 /* GCU */
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/* 0x00005000 Reserved */
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#define LPC31_APB0_OTP_OFFSET 0x00005000 /* USB OTG */
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#define LPC31_APB0_RNG_OFFSET 0x00006000 /* RNG */
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#define LPC31_APB1_TIMER0_OFFSET 0x00000000 /* TIMER0 */
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@ -107,21 +108,21 @@
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#define LPC31_APB2_PCM_OFFSET 0x00000000 /* PCM */
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#define LPC31_APB2_LCD_OFFSET 0x00000400 /* LCD */
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/* 0x00000800 Reserved */
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/* 0x00000800 Reserved */
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#define LPC31_APB2_UART_OFFSET 0x00001000 /* UART */
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#define LPC31_APB2_SPI_OFFSET 0x00002000 /* SPI */
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/* 0x00003000 Reserved */
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/* 0x00003000 Reserved */
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#define LPC31_APB3_I2SCONFIG_OFFSET 0x00000000 /* I2S System Configuration */
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#define LPC31_APB3_I2STX0_OFFSET 0x00000080 /* I2S TX0 */
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#define LPC31_APB3_I2STX1_OFFSET 0x00000100 /* I2S TX1 */
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#define LPC31_APB3_I2SRX0_OFFSET 0x00000180 /* I2S RX0 */
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#define LPC31_APB3_I2SRX1_OFFSET 0x00000200 /* I2S RX1 */
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/* 0x00000280 Reserved */
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/* 0x00000280 Reserved */
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#define LPC31_APB4_DMA_OFFSET 0x00000000 /* DMA */
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#define LPC31_APB4_NAND_OFFSET 0x00000800 /* NAND FLASH Controller */
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/* 0x00001000 Reserved */
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/* 0x00001000 Reserved */
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/* Sizes of memory regions in bytes */
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@ -141,12 +142,10 @@
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#define LPC31_INTC_SIZE (4*1024)
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#define LPC31_NAND_SIZE (2*1024)
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#if defined(CONFIG_ARCH_CHIP_LPC3131)
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#ifdef HAVE_INTSRAM1
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# define LPC31_ISRAM_SIZE (LPC31_INTSRAM0_SIZE+LPC31_INTSRAM1_SIZE)
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#elif defined(CONFIG_ARCH_CHIP_LPC3130)
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# define LPC31_ISRAM_SIZE LPC31_INTSRAM0_SIZE
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#else
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# error "Unsupported LPC31XX architecture"
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# define LPC31_ISRAM_SIZE LPC31_INTSRAM0_SIZE
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#endif
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/* Convert size in bytes to number of sections (in Mb). */
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@ -234,7 +233,7 @@
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# define LPC31_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
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# define LPC31_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
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#
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# ifdef CONFIG_LPC31_EXTNAND /* End of the virtual address space */
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# ifdef CONFIG_LPC31_EXTNAND /* End of the virtual address space */
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# define LPC31_LAST_VSECTION (LPC31_NAND_VSECTION + (1 << 20))
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# else
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# define LPC31_LAST_VSECTION (LPC31_INTC_VSECTION + (1 << 20))
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@ -258,7 +257,8 @@
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/* Determine the address of the MMU page table. We will try to place that page
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* table at the beginng of ISRAM0 if the vectors are at the high address, 0xffff:0000
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* or at the end of ISRAM1 (or ISRAM0 on a LPC3130) if the vectors are at 0x0000:0000
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* or at the end of ISRAM1 (or ISRAM0 if ISRAM1 is not available in this architecture)
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* if the vectors are at 0x0000:0000
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*
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* Or... the user may specify the address of the page table explicitly be defining
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* CONFIG_PGTABLE_VADDR and CONFIG_PGTABLE_PADDR in the configuration or board.h file.
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@ -307,10 +307,11 @@
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# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
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/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
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* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a LPC3130)
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* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a ISRAM1 is
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* not available in this architecture)
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*/
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# if CONFIG_ARCH_CHIP_LPC3131
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# ifdef HAVE_INTSRAM1
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# define PGTABLE_BASE_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
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# define PGTABLE_BASE_VADDR (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
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# else
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@ -328,10 +329,10 @@
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# endif
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# else
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/* Otherwise, ISRAM1 (or ISRAM0 for the LPC3130) will be mapped so that
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* the end of the SRAM region will provide memory for the vectors. The page
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* table will then be places at the first 16Kb of ISRAM0 (which will be in
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* the shadow memory region.
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/* Otherwise, ISRAM1 (or ISRAM0 for the is ISRAM1 is not available in this
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* architecture) will be mapped so that the end of the SRAM region will
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* provide memory for the vectors. The page table will then be places at
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* the first 16Kb of ISRAM0 (which will be in the shadow memory region).
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*/
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# define PGTABLE_BASE_PADDR LPC31_SHADOWSPACE_PSECTION
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@ -388,7 +389,7 @@
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# define LPC31_VECTOR_VADDR 0x00000000
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# define LPC31_VECTOR_VCOARSE 0x00000000
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#else /* Vectors located at 0xffff:0000 -- this probably does not work */
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# if CONFIG_ARCH_CHIP_LPC3131
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# ifdef HAVE_INTSRAM1
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# define LPC31_VECTOR_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
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# define LPC31_VECTOR_VSRAM (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
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# else
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@ -1,7 +1,7 @@
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/************************************************************************************************
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* arch/arm/src/lpc31xx/lpc31_nand.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -73,7 +73,17 @@
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#define LPC31_NAND_IRQSTATUS2_OFFSET 0x48 /* Interrrupt status register (second 32-bits) */
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#define LPC31_NAND_IRQMASK3_OFFSET 0x4c /* Interrupt mask register (second 32-bits) */
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#define LPC31_NAND_IRQSTATUSRAW2_OFFSET 0x50 /* Unmasked register status (second 32-bits) */
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#define LPC31_NAND_AESKEY1_OFFSET 0x54 /* First word of 128-bit AES key (LPC3154 only) */
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#define LPC31_NAND_AESKEY2_OFFSET 0x58 /* Second word of 128-bit AES key (LPC3154 only) */
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#define LPC31_NAND_AESKEY3_OFFSET 0x5c /* Third word of 128-bit AES key (LPC3154 only) */
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#define LPC31_NAND_AESKEY4_OFFSET 0x60 /* Fourth word of 128-bit AES key (LPC3154 only) */
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#define LPC31_NAND_AESIV1_OFFSET 0x64 /* First word of 128-bit initial AES value (LPC3154 only) */
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#define LPC31_NAND_AESIV2_OFFSET 0x68 /* Second word of 128-bit initial AES value (LPC3154 only) */
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#define LPC31_NAND_AESIV3_OFFSET 0x6c /* Third word of 128-bit initial AES value (LPC3154 only) */
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#define LPC31_NAND_AESIV4_OFFSET 0x70 /* Fourth word of 128-bit initial AES value (LPC3154 only) */
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#define LPC31_NAND_AESSTATE_OFFSET 0x74 /* Register to display AES state (LPC3154 only) */
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#define LPC31_NAND_ECCERRSTATUS_OFFSET 0x78 /* ECC error status register */
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#define LPC31_NAND_AESFROMAHB_OFFSET 0x7c /* Enable AES engine from AHB */
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/* NAND FLASH controller register (virtual) addresses *******************************************/
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#define LPC31_NAND_IRQSTATUS2 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUS2_OFFSET)
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#define LPC31_NAND_IRQMASK3 (LPC31_NAND_VBASE+LPC31_NAND_IRQMASK3_OFFSET)
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#define LPC31_NAND_IRQSTATUSRAW2 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUSRAW2_OFFSET)
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#define LPC31_NAND_AESKEY1 (LPC31_NAND_VBASE+LPC31_NAND_AESKEY1_OFFSET)
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#define LPC31_NAND_AESKEY2 (LPC31_NAND_VBASE+LPC31_NAND_AESKEY2_OFFSET)
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#define LPC31_NAND_AESKEY3 (LPC31_NAND_VBASE+LPC31_NAND_AESKEY3_OFFSET)
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#define LPC31_NAND_AESKEY4 (LPC31_NAND_VBASE+LPC31_NAND_AESKEY4_OFFSET)
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#define LPC31_NAND_AESIV1 (LPC31_NAND_VBASE+LPC31_NAND_AESIV1_OFFSET)
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#define LPC31_NAND_AESIV2 (LPC31_NAND_VBASE+LPC31_NAND_AESIV2_OFFSET)
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#define LPC31_NAND_AESIV3 (LPC31_NAND_VBASE+LPC31_NAND_AESIV3_OFFSET)
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#define LPC31_NAND_AESIV4 (LPC31_NAND_VBASE+LPC31_NAND_AESIV4_OFFSET)
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#define LPC31_NAND_AESSTATE (LPC31_NAND_VBASE+LPC31_NAND_AESSTATE_OFFSET)
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#define LPC31_NAND_ECCERRSTATUS (LPC31_NAND_VBASE+LPC31_NAND_ECCERRSTATUS_OFFSET)
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#define LPC31_NAND_AESFROMAHB (LPC31_NAND_VBASE+LPC31_NAND_AESFROMAHB_OFFSET)
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/* NAND FLASH controller register bit definitions ***********************************************/
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/* NandIRQStatus1 register description (NandIRQStatus1, address 0x17000800) */
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@ -130,6 +150,9 @@
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#define NAND_IRQSTATUS1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */
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#define NAND_IRQSTATUS1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */
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#define NAND_IRQSTATUS1_RAM1AESDONE (1 << 1) /* Bit 1: RAM 1 AES done (LPC3154 only) */
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#define NAND_IRQSTATUS1_RAM0AESDONE (1 << 0) /* Bit 0: RAM 0 AES done (LPC3154 only) */
|
||||
|
||||
/* NandIRQMask1 register description (NandIRQMask1, address 0x17000804) */
|
||||
|
||||
#define NAND_IRQIRQMASK1_MNANDRYBN3 (1 << 31) /* Bit 31: mNAND_RYBN3 positive edge */
|
||||
@ -161,6 +184,9 @@
|
||||
#define NAND_IRQIRQMASK1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */
|
||||
#define NAND_IRQIRQMASK1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */
|
||||
|
||||
#define NAND_IRQIRQMASK1_RAM1AESDONE (1 << 1) /* Bit 1: RAM 1 AES done (LPC3154 only) */
|
||||
#define NAND_IRQIRQMASK1_RAM0AESDONE (1 << 0) /* Bit 0: RAM 0 AES done (LPC3154 only) */
|
||||
|
||||
/* NandIRQStatusRaw1 register description (NandIRQStatusRaw1, address 0x17000808) */
|
||||
|
||||
#define NAND_IRQSTATUSRAW1_MNANDRYBN3 (1 << 31) /* Bit 31: mNAND_RYBN3 positive edge */
|
||||
@ -192,6 +218,9 @@
|
||||
#define NAND_IRQSTATUSRAW1_RAM15ERR (1 << 5) /* Bit 5: RAM 1 decoded with 5 error */
|
||||
#define NAND_IRQSTATUSRAW1_RAM1UNCORR (1 << 4) /* Bit 4: RAM 1 uncorrectable */
|
||||
|
||||
#define NAND_IRQSTATUSRAW1_RAM1AESDONE (1 << 1) /* Bit 1: RAM 1 AES done (LPC3154 only) */
|
||||
#define NAND_IRQSTATUSRAW1_RAM0AESDONE (1 << 0) /* Bit 0: RAM 0 AES done (LPC3154 only) */
|
||||
|
||||
/* NandConfig register description (NandConfig, address 0x1700080c) */
|
||||
|
||||
#define NAND_CONFIG_ECC_MODE (1 << 12) /* Bit 12: ECC mode 0 */
|
||||
@ -209,6 +238,7 @@
|
||||
# define NAND_CONFIG_LC_2WAITSTATES (2 << NAND_CONFIG_LC_SHIFT)
|
||||
#define NAND_CONFIG_ES (1 << 4) /* Bit 4: Endianess setting */
|
||||
#define NAND_CONFIG_DE (1 << 3) /* Bit 3: DMA external enable */
|
||||
#define NAND_CONFIG_AO (1 << 2) /* Bit 2: AES on (LPC3154 only) */
|
||||
#define NAND_CONFIG_WD (1 << 1) /* Bit 1: Wide device */
|
||||
#define NAND_CONFIG_EC (1 << 0) /* Bit 0: ECC on */
|
||||
|
||||
@ -355,14 +385,30 @@
|
||||
#define NAND_IRQSTATUSRAW2_RAM1BUSY (1 << 1) /* Bit 1: RAM1 access while busy */
|
||||
#define NAND_IRQSTATUSRAW2_RAM0BUSY (1 << 0) /* Bit 0: RAM0 access while busy */
|
||||
|
||||
/* NandECCErrStatus register description (NandECCErrStatus, address 0x1700 0878) */
|
||||
/* First-fourth words of 128-bit AES key (32-bit values, no bit fields -- LPC3154 only) */
|
||||
/* First-fourth words of 128-bit initial AES value (32-bit values, no bit fields -- LPC3154 only) */
|
||||
|
||||
/* Register to display AES state (LPC3154 only) */
|
||||
|
||||
#define NAND_AESSTATE_SHIFT (0) /* Bits 0-1: AES state */
|
||||
#define NAND_AESSTATE_MASK (3 << NAND_AESSTATE_SHIFT)
|
||||
# define NAND_AESSTATE_BUSY (0 << NAND_AESSTATE_SHIFT) /* AES state machine busy */
|
||||
# define NAND_AESSTATE_KEYSETUP (1 << NAND_AESSTATE_SHIFT) /* AES key setup needed */
|
||||
# define NAND_AESSTATE_IDLE (3 << NAND_AESSTATE_SHIFT) /* AES module is IDLE */
|
||||
|
||||
/* NandECCErrStatus register description (NandECCErrStatus, address 0x1700 0878) */
|
||||
|
||||
#define NAND_ECCERRSTATUS_NERR1_SHIFT (4) /* Bits 4-7: Number of errors in RAM1 */
|
||||
#define NAND_ECCERRSTATUS_NERR1_MASK (0x0f << NAND_ECCERRSTATUS_NERR1_SHIFT)
|
||||
#define NAND_ECCERRSTATUS_NERR0_SHIFT (0) /* Bits 0-3: Number of errors in RAM0 */
|
||||
#define NAND_ECCERRSTATUS_NERR0_MASK (0x0f << NAND_ECCERRSTATUS_NERR0_SHIFT)
|
||||
|
||||
/* Enable AES engine from AHB */
|
||||
|
||||
#define NAND_AESFROMAHB_MODE (1 << 7) /* Bit 7: Set AES from AHB mode */
|
||||
#define NAND_AESFROMAHB_DECRYPTRAM1 (1 << 1) /* Bit 1: Decrypt RAM1 */
|
||||
#define NAND_AESFROMAHB_DECRYPTRAM0 (1 << 0) /* Bit 0: Decrypt RAM0 */
|
||||
|
||||
/************************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************************/
|
||||
|
||||
@ -1,11 +1,12 @@
|
||||
/*******************************************************************************
|
||||
* arch/arm/src/lpc31xx/lpc31_usbdev.c
|
||||
*
|
||||
* Author: Davide Hewson
|
||||
* Authors: David Hewson
|
||||
* Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Part of the NuttX OS and based, in part, on the LPC2148 USB driver:
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -396,8 +397,10 @@ static int lpc31_epdisable(FAR struct usbdev_ep_s *ep);
|
||||
static FAR struct usbdev_req_s *lpc31_epallocreq(FAR struct usbdev_ep_s *ep);
|
||||
static void lpc31_epfreereq(FAR struct usbdev_ep_s *ep,
|
||||
FAR struct usbdev_req_s *);
|
||||
#ifdef CONFIG_ARCH_USBDEV_DMA
|
||||
static void *lpc31_epallocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes);
|
||||
static void lpc313_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
|
||||
#endif
|
||||
static int lpc31_epsubmit(FAR struct usbdev_ep_s *ep,
|
||||
struct usbdev_req_s *req);
|
||||
static int lpc31_epcancel(FAR struct usbdev_ep_s *ep,
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/************************************************************************************************
|
||||
* arch/arm/src/lpc31xx/lpc31_usbotg.h
|
||||
*
|
||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -254,8 +254,8 @@
|
||||
# define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */
|
||||
# define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */
|
||||
# define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */
|
||||
#define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */
|
||||
#define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */
|
||||
#define USBDEV_USBCMD_ATDTW (1 << 12) /* Bit 12: Add dTD trip wire */
|
||||
#define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */
|
||||
#define USBDEV_USBCMD_RS (1 << 0) /* Bit 0: 0 Run/Stop */
|
||||
|
||||
@ -338,7 +338,7 @@
|
||||
|
||||
/* Frame index register FRINDEX (address 0x1900014c) -- Host Mode */
|
||||
|
||||
#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-(n+2): Frame list current index */
|
||||
#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-13: Frame list current index */
|
||||
#define USBHOST_FRINDEX_FLI_MASK(n) (0x7ff << ((n)+USBHOST_FRINDEX_FLI_SHIFT-1)
|
||||
#define USBHOST_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
|
||||
#define USBHOST_FRINDEX_CUFN_MASK (7 << USBHOST_FRINDEX_CUFN_SHIFT)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user