diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index 30e92dd257..e12fdcd735 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -309,6 +309,11 @@ config ESP32C3_WIRELESS config ESP32C3_AES_ACCELERATOR bool "AES Accelerator" default n +config ESP32C3_SHA_ACCELERATOR + bool "SHA Accelerator" + default n + ---help--- + Enable ESP32-C3 SHA accelerator support. config ESP32C3_BIGNUM_ACCELERATOR bool "BIGNUM Accelerator" @@ -840,6 +845,14 @@ config ESP32C3_AES_ACCELERATOR_TEST default n endmenu # AES accelerator +menu "SHA accelerator" + depends on ESP32C3_SHA_ACCELERATOR + +config ESP32C3_SHA_ACCELERATOR_TEST + bool "SHA accelerator test" + default n + +endmenu # ESP32C3_SHA_ACCELERATOR menu "RSA Accelerate Configuration" depends on ESP32C3_RSA_ACCELERATOR diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index 7a47f31cf5..3de23757f9 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -117,6 +117,10 @@ ifeq ($(CONFIG_ESP32C3_RSA_ACCELERATOR),y) CHIP_CSRCS += esp32c3_rsa.c endif +ifeq ($(CONFIG_ESP32C3_SHA_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_sha.c +endif + ifeq ($(CONFIG_ESP32C3_FREERUN),y) CHIP_CSRCS += esp32c3_freerun.c endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.c b/arch/risc-v/src/esp32c3/esp32c3_sha.c new file mode 100644 index 0000000000..773ad237ec --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_sha.c @@ -0,0 +1,1715 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_sha.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR + +#include +#include +#include +#include +#include +#include +#include + +#include "riscv_arch.h" +#include "hardware/esp32c3_sha.h" +#include "hardware/esp32c3_system.h" + +#include "esp32c3_sha.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i)] = (unsigned char) ((n) >> 24); \ + (b)[(i) + 1] = (unsigned char) ((n) >> 16); \ + (b)[(i) + 2] = (unsigned char) ((n) >> 8); \ + (b)[(i) + 3] = (unsigned char) ((n)); \ +} + +#define GET_UINT64_BE(n,b,i) \ +{ \ + (n) = ((uint64_t) (b)[(i)] << 56) \ + | ((uint64_t) (b)[(i) + 1] << 48) \ + | ((uint64_t) (b)[(i) + 2] << 40) \ + | ((uint64_t) (b)[(i) + 3] << 32) \ + | ((uint64_t) (b)[(i) + 4] << 24) \ + | ((uint64_t) (b)[(i) + 5] << 16) \ + | ((uint64_t) (b)[(i) + 6] << 8) \ + | ((uint64_t) (b)[(i) + 7]); \ +} + +#define PUT_UINT64_BE(n,b,i) \ +{ \ + (b)[(i)] = (uint8_t) ((n) >> 56); \ + (b)[(i) + 1] = (uint8_t) ((n) >> 48); \ + (b)[(i) + 2] = (uint8_t) ((n) >> 40); \ + (b)[(i) + 3] = (uint8_t) ((n) >> 32); \ + (b)[(i) + 4] = (uint8_t) ((n) >> 24); \ + (b)[(i) + 5] = (uint8_t) ((n) >> 16); \ + (b)[(i) + 6] = (uint8_t) ((n) >> 8); \ + (b)[(i) + 7] = (uint8_t) ((n)); \ +} + +#define SHR(x,n) ((x) >> (n)) +#define ROTR(x,n) (SHR((x),(n)) | ((x) << (64 - (n)))) + +#define S0(x) (ROTR(x, 1) ^ ROTR(x, 8) ^ SHR(x, 7)) +#define S1(x) (ROTR(x,19) ^ ROTR(x,61) ^ SHR(x, 6)) + +#define S2(x) (ROTR(x,28) ^ ROTR(x,34) ^ ROTR(x,39)) +#define S3(x) (ROTR(x,14) ^ ROTR(x,18) ^ ROTR(x,41)) + +#define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) +#define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) + +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += temp1; \ + (h) = temp1 + temp2; \ + } while(0) + +#define SHA1_BLK_SIZE (20) +#define SHA2_BLK_SIZE (32) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_sha_inited; +static sem_t g_sha_sem = SEM_INITIALIZER(1); +static const unsigned char esp32c3_sha_padding[64] = +{ + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const uint64_t K[80] = +{ + UINT64_C(0x428a2f98d728ae22), UINT64_C(0x7137449123ef65cd), + UINT64_C(0xb5c0fbcfec4d3b2f), UINT64_C(0xe9b5dba58189dbbc), + UINT64_C(0x3956c25bf348b538), UINT64_C(0x59f111f1b605d019), + UINT64_C(0x923f82a4af194f9b), UINT64_C(0xab1c5ed5da6d8118), + UINT64_C(0xd807aa98a3030242), UINT64_C(0x12835b0145706fbe), + UINT64_C(0x243185be4ee4b28c), UINT64_C(0x550c7dc3d5ffb4e2), + UINT64_C(0x72be5d74f27b896f), UINT64_C(0x80deb1fe3b1696b1), + UINT64_C(0x9bdc06a725c71235), UINT64_C(0xc19bf174cf692694), + UINT64_C(0xe49b69c19ef14ad2), UINT64_C(0xefbe4786384f25e3), + UINT64_C(0x0fc19dc68b8cd5b5), UINT64_C(0x240ca1cc77ac9c65), + UINT64_C(0x2de92c6f592b0275), UINT64_C(0x4a7484aa6ea6e483), + UINT64_C(0x5cb0a9dcbd41fbd4), UINT64_C(0x76f988da831153b5), + UINT64_C(0x983e5152ee66dfab), UINT64_C(0xa831c66d2db43210), + UINT64_C(0xb00327c898fb213f), UINT64_C(0xbf597fc7beef0ee4), + UINT64_C(0xc6e00bf33da88fc2), UINT64_C(0xd5a79147930aa725), + UINT64_C(0x06ca6351e003826f), UINT64_C(0x142929670a0e6e70), + UINT64_C(0x27b70a8546d22ffc), UINT64_C(0x2e1b21385c26c926), + UINT64_C(0x4d2c6dfc5ac42aed), UINT64_C(0x53380d139d95b3df), + UINT64_C(0x650a73548baf63de), UINT64_C(0x766a0abb3c77b2a8), + UINT64_C(0x81c2c92e47edaee6), UINT64_C(0x92722c851482353b), + UINT64_C(0xa2bfe8a14cf10364), UINT64_C(0xa81a664bbc423001), + UINT64_C(0xc24b8b70d0f89791), UINT64_C(0xc76c51a30654be30), + UINT64_C(0xd192e819d6ef5218), UINT64_C(0xd69906245565a910), + UINT64_C(0xf40e35855771202a), UINT64_C(0x106aa07032bbd1b8), + UINT64_C(0x19a4c116b8d2d0c8), UINT64_C(0x1e376c085141ab53), + UINT64_C(0x2748774cdf8eeb99), UINT64_C(0x34b0bcb5e19b48a8), + UINT64_C(0x391c0cb3c5c95a63), UINT64_C(0x4ed8aa4ae3418acb), + UINT64_C(0x5b9cca4f7763e373), UINT64_C(0x682e6ff3d6b2b8a3), + UINT64_C(0x748f82ee5defb2fc), UINT64_C(0x78a5636f43172f60), + UINT64_C(0x84c87814a1f0ab72), UINT64_C(0x8cc702081a6439ec), + UINT64_C(0x90befffa23631e28), UINT64_C(0xa4506cebde82bde9), + UINT64_C(0xbef9a3f7b2c67915), UINT64_C(0xc67178f2e372532b), + UINT64_C(0xca273eceea26619c), UINT64_C(0xd186b8c721c0c207), + UINT64_C(0xeada7dd6cde0eb1e), UINT64_C(0xf57d4f7fee6ed178), + UINT64_C(0x06f067aa72176fba), UINT64_C(0x0a637dc5a2c898a6), + UINT64_C(0x113f9804bef90dae), UINT64_C(0x1b710b35131c471b), + UINT64_C(0x28db77f523047d84), UINT64_C(0x32caab7b40c72493), + UINT64_C(0x3c9ebe0a15c9bebc), UINT64_C(0x431d67c49c100d4c), + UINT64_C(0x4cc5d4becb3e42b6), UINT64_C(0x597f299cfc657e2a), + UINT64_C(0x5fcb6fab3ad6faec), UINT64_C(0x6c44198c4a475817) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_sha1_block + * + * Description: + * Performs SHA1 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA1 context + * data - Input message to be hashed on single block + * len - Length of the input message on single block + * buf - Input message to be hashed on multiple blocks + * buf_len - Length of the input message on multiple blocks + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha1_block(struct esp32c3_sha1_context_s *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + uint32_t *data_words = NULL; + size_t blk_len = 0; + size_t blk_word_len = 0; + int num_block = 0; + int i; + int j; + + blk_len = 64; + blk_word_len = blk_len / 4; + num_block = len / blk_len; + + putreg32(ctx->mode, SHA_MODE_REG); + + if (buf_len != 0) + { + data_words = (uint32_t *)buf; + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + for (j = 0; j < num_block; j++) + { + data_words = (uint32_t *)(data + blk_len * j); + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < 5; i ++) + { + ctx->state[i] = getreg32(SHA_H_0_REG + i * 4); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_block + * + * Description: + * Performs SHA256 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA256 context + * data - Input message to be hashed on single block + * len - Length of the input message on single block + * buf - Input message to be hashed on multiple blocks + * buf_len - Length of the input message on multiple blocks + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha256_block(struct esp32c3_sha256_context_s *ctx, + const uint8_t *data, size_t len, + uint8_t *buf, size_t buf_len) +{ + uint32_t *data_words = NULL; + size_t blk_len = 0; + size_t blk_word_len = 0; + int num_block = 0; + int i; + int j; + + blk_len = 64; + blk_word_len = blk_len / 4; + num_block = len / blk_len; + + putreg32(ctx->mode, SHA_MODE_REG); + + if (buf_len != 0) + { + data_words = (uint32_t *)buf; + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + for (j = 0; j < num_block; j++) + { + data_words = (uint32_t *)(data + blk_len * j); + + while (getreg32(SHA_BUSY_REG)) + { + } + + for (i = 0; i < blk_word_len; i++) + { + putreg32(data_words[i], SHA_M_0_REG + i * 4); + } + + if (ctx->first_block) + { + putreg32(1, SHA_START_REG); + } + else + { + putreg32(1, SHA_CONTINUE_REG); + } + + ctx->first_block = false; + } + + while (getreg32(SHA_BUSY_REG)) + { + } + + if (ctx->mode == ESP32C3_SHA2_256) + { + num_block = 8; + } + else + { + num_block = 7; + } + + for (i = 0; i < num_block; i ++) + { + ctx->state[i] = getreg32(SHA_H_0_REG + i * 4); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_block + * + * Description: + * Performs SHA512 on multiple blocks at a time. + * + * Input Parameters: + * ctx - The SHA512 context + * data - Input message to be hashed + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +static int esp32c3_sha512_block(struct esp32c3_sha512_context_s *ctx, + const uint8_t *data) +{ + int i; + int j; + uint64_t temp1, temp2, W[80]; + uint64_t A, B, C, D, E, F, G, H; + + for (i = 0; i < 16; i++) + { + GET_UINT64_BE(W[i], data, i << 3); + } + + for (; i < 80; i++) + { + W[i] = S1(W[i - 2]) + W[i - 7] + S0(W[i - 15]) + W[i - 16]; + } + + A = ctx->state[0]; + B = ctx->state[1]; + C = ctx->state[2]; + D = ctx->state[3]; + E = ctx->state[4]; + F = ctx->state[5]; + G = ctx->state[6]; + H = ctx->state[7]; + i = 0; + j = 0; + + do + { + P(A, B, C, D, E, F, G, H, W[i++], K[j++]); + P(H, A, B, C, D, E, F, G, W[i++], K[j++]); + P(G, H, A, B, C, D, E, F, W[i++], K[j++]); + P(F, G, H, A, B, C, D, E, W[i++], K[j++]); + P(E, F, G, H, A, B, C, D, W[i++], K[j++]); + P(D, E, F, G, H, A, B, C, W[i++], K[j++]); + P(C, D, E, F, G, H, A, B, W[i++], K[j++]); + P(B, C, D, E, F, G, H, A, W[i++], K[j++]); + } + while (i < 80); + + ctx->state[0] += A; + ctx->state[1] += B; + ctx->state[2] += C; + ctx->state[3] += D; + ctx->state[4] += E; + ctx->state[5] += F; + ctx->state[6] += G; + ctx->state[7] += H; + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_sha1_init + * + * Description: + * Initializes a SHA-1 context. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha1_init(struct esp32c3_sha1_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha1_starts + * + * Description: + * Starts a SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha1_starts(struct esp32c3_sha1_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); + ctx->mode = ESP32C3_SHA1_1; + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha1_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_update(struct esp32c3_sha1_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + int ret; + size_t fill; + uint32_t left; + uint32_t len; + uint32_t local_len = 0; + int i; + + if (!ilen || (input == NULL)) + { + return OK; + } + + left = ctx->total[0] & 0x3f; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= UINT32_MAX; + + if (ctx->total[0] < ilen) + { + ctx->total[1]++; + } + + if (left && ilen >= fill) + { + memcpy((void *) (ctx->buffer + left), input, fill); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + if (len || local_len) + { + ret = nxsem_wait(&g_sha_sem); + if (ret < 0) + { + return ret; + } + + if (ctx->sha_state == ESP32C3_SHA_STATE_INIT) + { + ctx->first_block = true; + + ctx->sha_state = ESP32C3_SHA_STATE_IN_PROCESS; + } + else if (ctx->sha_state == ESP32C3_SHA_STATE_IN_PROCESS) + { + ctx->first_block = false; + for (i = 0; i < 5; i++) + { + putreg32(ctx->state[i], SHA_H_0_REG + i * 4); + } + } + + ret = esp32c3_sha1_block(ctx, input, len, ctx->buffer, local_len); + ret |= nxsem_post(&g_sha_sem); + + if (ret != 0) + { + return ret; + } + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input + len, ilen - len); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha1_finish + * + * Description: + * Finishes the SHA-1 operation, + * and writes the result to the output buffer. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * output - The SHA-1 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_finish(struct esp32c3_sha1_context_s *ctx, + unsigned char output[20]) +{ + int ret; + uint32_t last; + uint32_t padn; + uint32_t high; + uint32_t low; + unsigned char msglen[8]; + + high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msglen, 0); + PUT_UINT32_BE(low, msglen, 4); + + last = ctx->total[0] & 0x3f; + padn = (last < 56) ? (56 - last) : (120 - last); + + ret = esp32c3_sha1_update(ctx, esp32c3_sha_padding, padn); + if (ret != 0) + { + return ret; + } + + ret = esp32c3_sha1_update(ctx, msglen, 8); + if (ret != 0) + { + return ret; + } + + memcpy(output, ctx->state, SHA1_BLK_SIZE); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha1_free + * + * Description: + * Clears a SHA-1 context. + * + * Input Parameters: + * ctx - The SHA-1 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha1_free(struct esp32c3_sha1_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha256_init + * + * Description: + * Initializes a SHA-256 context. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha256_init(struct esp32c3_sha256_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha256_starts + * + * Description: + * Starts a SHA-224 or SHA-256 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * is224 - Determines which function to use + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha256_starts(struct esp32c3_sha256_context_s *ctx, bool is224) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); + + if (is224) + { + ctx->mode = ESP32C3_SHA2_224; + } + else + { + ctx->mode = ESP32C3_SHA2_256; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-224 or SHA-256 + * checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_update(struct esp32c3_sha256_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + int ret = 0; + size_t fill; + uint32_t left; + uint32_t len; + uint32_t local_len = 0; + int i; + + if (ilen == 0) + { + return OK; + } + + left = ctx->total[0] & 0x3f; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= UINT32_MAX; + + if (ctx->total[0] < ilen) + { + ctx->total[1]++; + } + + /* Check if any data pending from previous call to this API */ + + if (left && ilen >= fill) + { + memcpy((void *) (ctx->buffer + left), input, fill); + + input += fill; + ilen -= fill; + left = 0; + local_len = 64; + } + + len = (ilen / 64) * 64; + + if (len || local_len) + { + ret = nxsem_wait(&g_sha_sem); + if (ret < 0) + { + return ret; + } + + if (ctx->sha_state == ESP32C3_SHA_STATE_INIT) + { + ctx->first_block = true; + ctx->sha_state = ESP32C3_SHA_STATE_IN_PROCESS; + } + else if (ctx->sha_state == ESP32C3_SHA_STATE_IN_PROCESS) + { + ctx->first_block = false; + int block_num = (ctx->mode == ESP32C3_SHA2_224) ? 7 : 8; + for (i = 0; i < block_num; i++) + { + putreg32(ctx->state[i], SHA_H_0_REG + i * 4); + } + } + + ret = esp32c3_sha256_block(ctx, input, len, ctx->buffer, local_len); + ret |= nxsem_post(&g_sha_sem); + + if (ret != 0) + { + return ret; + } + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input + len, ilen - len); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha256_finish + * + * Description: + * Finishes the SHA-224 or SHA-256 operation, and writes the result to + * the output buffer. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * output - The SHA-256 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_finish(struct esp32c3_sha256_context_s *ctx, + unsigned char output[32]) +{ + int ret; + uint32_t last; + uint32_t padn; + uint32_t high; + uint64_t low; + unsigned char msglen[8]; + + high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msglen, 0); + PUT_UINT32_BE(low, msglen, 4); + + last = ctx->total[0] & 0x3f; + padn = (last < 56) ? (56 - last) : (120 - last); + + ret = esp32c3_sha256_update(ctx, esp32c3_sha_padding, padn); + if (ret != 0) + { + return ret; + } + + ret = esp32c3_sha256_update(ctx, msglen, 8); + if (ret != 0) + { + return ret; + } + + memcpy(output, ctx->state, SHA2_BLK_SIZE); + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha256_free + * + * Description: + * Clears a SHA-256 context. + * + * Input Parameters: + * ctx - The SHA-256 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha256_free(struct esp32c3_sha256_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha256_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha512_init + * + * Description: + * Initializes a SHA-512 context. + * + * Input Parameters: + * ctx - The SHA-512 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha512_init(struct esp32c3_sha512_context_s *ctx) +{ + memset(ctx, 0, sizeof(struct esp32c3_sha512_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha512_starts + * + * Description: + * Starts a SHA-384 or SHA-512 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-512 context to initialize + * is384 - Determines which function to use + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_starts(struct esp32c3_sha512_context_s *ctx, bool is384) +{ + int ret = 0; + + if (is384) + { + ctx->mode = ESP32C3_SHA3_384; + + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = UINT64_C(0xcbbb9d5dc1059ed8); + ctx->state[1] = UINT64_C(0x629a292a367cd507); + ctx->state[2] = UINT64_C(0x9159015a3070dd17); + ctx->state[3] = UINT64_C(0x152fecd8f70e5939); + ctx->state[4] = UINT64_C(0x67332667ffc00b31); + ctx->state[5] = UINT64_C(0x8eb44a8768581511); + ctx->state[6] = UINT64_C(0xdb0c2e0d64f98fa7); + ctx->state[7] = UINT64_C(0x47b5481dbefa4fa4); + } + else + { + ctx->mode = ESP32C3_SHA3_512; + + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = UINT64_C(0x6a09e667f3bcc908); + ctx->state[1] = UINT64_C(0xbb67ae8584caa73b); + ctx->state[2] = UINT64_C(0x3c6ef372fe94f82b); + ctx->state[3] = UINT64_C(0xa54ff53a5f1d36f1); + ctx->state[4] = UINT64_C(0x510e527fade682d1); + ctx->state[5] = UINT64_C(0x9b05688c2b3e6c1f); + ctx->state[6] = UINT64_C(0x1f83d9abfb41bd6b); + ctx->state[7] = UINT64_C(0x5be0cd19137e2179); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32c3_sha512_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-384 or SHA-512 + * checksum calculation. + * + * Input Parameters: + * ctx - The SHA-512 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_update(struct esp32c3_sha512_context_s *ctx, + const unsigned char *input, + size_t ilen) +{ + size_t fill; + uint32_t left; + const uint8_t *input_buffer = (const uint8_t *)input; + + left = (uint32_t) (ctx->total[0] & 0x7f); + fill = 128 - left; + + ctx->total[0] += (uint64_t)ilen; + + if (ctx->total[0] < (uint64_t)ilen) + { + ctx->total[1]++; + } + + if (left && ilen >= fill) + { + memcpy(ctx->buffer + left, input_buffer, fill); + + esp32c3_sha512_block(ctx, ctx->buffer); + + input_buffer += fill; + ilen -= fill; + left = 0; + } + + while (ilen >= 128) + { + esp32c3_sha512_block(ctx, input_buffer); + + input_buffer += 128; + ilen -= 128; + } + + if (ilen > 0) + { + memcpy((void *) (ctx->buffer + left), input_buffer, ilen); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_finish + * + * Description: + * Finishes the SHA-384 or SHA-512 operation, and writes the result to + * the output buffer. + * + * Input Parameters: + * ctx - The SHA-512 context to use + * output - The SHA-512 checksum result + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha512_finish(struct esp32c3_sha512_context_s *ctx, + unsigned char output[64]) +{ + uint8_t used; + uint64_t high; + uint64_t low; + uint8_t *output_buffer = (uint8_t *)output; + + used = ctx->total[0] & 0x7f; + ctx->buffer[used++] = 0x80; + + if (used <= 112) + { + memset(ctx->buffer + used, 0, 112 - used); + } + else + { + memset(ctx->buffer + used, 0, 128 - used); + esp32c3_sha512_block(ctx, ctx->buffer); + memset(ctx->buffer, 0, 112); + } + + high = (ctx->total[0] >> 61) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT64_BE(high, ctx->buffer, 112); + PUT_UINT64_BE(low, ctx->buffer, 120); + + esp32c3_sha512_block(ctx, ctx->buffer); + + PUT_UINT64_BE(ctx->state[0], output_buffer, 0); + PUT_UINT64_BE(ctx->state[1], output_buffer, 8); + PUT_UINT64_BE(ctx->state[2], output_buffer, 16); + PUT_UINT64_BE(ctx->state[3], output_buffer, 24); + PUT_UINT64_BE(ctx->state[4], output_buffer, 32); + PUT_UINT64_BE(ctx->state[5], output_buffer, 40); + + if (ctx->mode == ESP32C3_SHA3_512) + { + PUT_UINT64_BE(ctx->state[6], output_buffer, 48); + PUT_UINT64_BE(ctx->state[7], output_buffer, 56); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32c3_sha512_free + * + * Description: + * Clears a SHA-512 context. + * + * Input Parameters: + * ctx - The SHA-512 context to clear + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha512_free(struct esp32c3_sha512_context_s *ctx) +{ + if (ctx == NULL) + { + return; + } + + memset(ctx, 0, sizeof(struct esp32c3_sha1_context_s)); +} + +/**************************************************************************** + * Name: esp32c3_sha_init + * + * Description: + * Initialize ESP32-C3 SHA hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha_init(void) +{ + if (!g_sha_inited) + { + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_CRYPTO_SHA_CLK_EN); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_SHA_RST, 0); + g_sha_inited = true; + } + else + { + return -EBUSY; + } + + return OK; +} + +#endif + +/**************************************************************************** + * Test Functions + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32c3_sha1_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha1_self_test(bool verbose) +{ + int i; + int j; + int buflen; + int ret = 0; + unsigned char buf[1024]; + unsigned char sha1sum[20]; + struct esp32c3_sha1_context_s ctx; + + /* FIPS-180-1 test vectors */ + + const unsigned char sha1_test_buf[3][57] = + { + { + "abc" + }, + + { + "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + }, + + { + "" + } + }; + + const size_t sha1_test_buflen[3] = + { + 3, 56, 1000 + }; + + const unsigned char sha1_test_sum[3][20] = + { + { + 0xa9, 0x99, 0x3e, 0x36, 0x47, 0x06, 0x81, 0x6a, 0xba, 0x3e, + 0x25, 0x71, 0x78, 0x50, 0xc2, 0x6c, 0x9c, 0xd0, 0xd8, 0x9d + }, + + { + 0x84, 0x98, 0x3e, 0x44, 0x1c, 0x3b, 0xd2, 0x6e, 0xba, 0xae, + 0x4a, 0xa1, 0xf9, 0x51, 0x29, 0xe5, 0xe5, 0x46, 0x70, 0xf1 + }, + + { + 0x34, 0xaa, 0x97, 0x3c, 0xd4, 0xc4, 0xda, 0xa4, 0xf6, 0x1e, + 0xeb, 0x2b, 0xdb, 0xad, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6f + } + }; + + esp32c3_sha1_init(&ctx); + + for (i = 0; i < 3; i++) + { + if (verbose) + { + syslog(LOG_INFO, " SHA-1 test #%d: ", i + 1); + } + + ret = esp32c3_sha1_starts(&ctx); + if (ret != 0) + { + goto fail; + } + + if (i == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha1_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha1_update(&ctx, + sha1_test_buf[i], + sha1_test_buflen[i]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha1_finish(&ctx, sha1sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha1sum, sha1_test_sum[i], 20) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha1_free(&ctx); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha256_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha256_self_test(bool verbose) +{ + int i; + int j; + int k; + int buflen; + int ret = 0; + unsigned char *buf; + unsigned char sha256sum[32]; + struct esp32c3_sha256_context_s ctx; + + /* FIPS-180-2 test vectors */ + + const unsigned char sha256_test_buf[3][57] = + { + { + "abc" + }, + + { + "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + }, + + { + "" + } + }; + + const size_t sha256_test_buflen[3] = + { + 3, 56, 1000 + }; + + const unsigned char sha256_test_sum[6][32] = + { + /* SHA-224 test vectors */ + + { + 0x23, 0x09, 0x7d, 0x22, 0x34, 0x05, 0xd8, 0x22, + 0x86, 0x42, 0xa4, 0x77, 0xbd, 0xa2, 0x55, 0xb3, + 0x2a, 0xad, 0xbc, 0xe4, 0xbd, 0xa0, 0xb3, 0xf7, + 0xe3, 0x6c, 0x9d, 0xa7 + }, + + { + 0x75, 0x38, 0x8b, 0x16, 0x51, 0x27, 0x76, 0xcc, + 0x5d, 0xba, 0x5d, 0xa1, 0xfd, 0x89, 0x01, 0x50, + 0xb0, 0xc6, 0x45, 0x5c, 0xb4, 0xf5, 0x8b, 0x19, + 0x52, 0x52, 0x25, 0x25 + }, + + { + 0x20, 0x79, 0x46, 0x55, 0x98, 0x0c, 0x91, 0xd8, + 0xbb, 0xb4, 0xc1, 0xea, 0x97, 0x61, 0x8a, 0x4b, + 0xf0, 0x3f, 0x42, 0x58, 0x19, 0x48, 0xb2, 0xee, + 0x4e, 0xe7, 0xad, 0x67 + }, + + /* SHA-256 test vectors */ + + { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, + 0x41, 0x41, 0x40, 0xde, 0x5d, 0xae, 0x22, 0x23, + 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad + }, + + { + 0x24, 0x8d, 0x6a, 0x61, 0xd2, 0x06, 0x38, 0xb8, + 0xe5, 0xc0, 0x26, 0x93, 0x0c, 0x3e, 0x60, 0x39, + 0xa3, 0x3c, 0xe4, 0x59, 0x64, 0xff, 0x21, 0x67, + 0xf6, 0xec, 0xed, 0xd4, 0x19, 0xdb, 0x06, 0xc1 + }, + + { + 0xcd, 0xc7, 0x6e, 0x5c, 0x99, 0x14, 0xfb, 0x92, + 0x81, 0xa1, 0xc7, 0xe2, 0x84, 0xd7, 0x3e, 0x67, + 0xf1, 0x80, 0x9a, 0x48, 0xa4, 0x97, 0x20, 0x0e, + 0x04, 0x6d, 0x39, 0xcc, 0xc7, 0x11, 0x2c, 0xd0 + } + }; + + buf = calloc(1024, sizeof(unsigned char)); + if (NULL == buf) + { + if (verbose) + { + syslog(LOG_INFO, "Buffer allocation failed\n"); + } + + return (1); + } + + esp32c3_sha256_init(&ctx); + + for (i = 0; i < 6; i++) + { + j = i % 3; + k = i < 3; + + if (verbose) + { + syslog(LOG_INFO, " SHA-%d test #%d: ", 256 - k * 32, j + 1); + } + + ret = esp32c3_sha256_starts(&ctx, k); + if (ret != 0) + { + goto fail; + } + + if (j == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha256_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha256_update(&ctx, + sha256_test_buf[j], + sha256_test_buflen[j]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha256_finish(&ctx, sha256sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha256sum, sha256_test_sum[i], 32 - k * 4) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha256_free(&ctx); + free(buf); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha512_self_test + * + * Description: + * Checkup routine + * + * Input Parameters: + * verbose - The result output or not + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp32c3_sha512_self_test(bool verbose) +{ + int i; + int j; + int k; + int buflen; + int ret = 0; + unsigned char *buf; + unsigned char sha512sum[64]; + struct esp32c3_sha512_context_s ctx; + + /* FIPS-180-2 test vectors */ + + const unsigned char sha512_test_buf[3][113] = + { + { + "abc" + }, + + { + "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" + "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" + }, + + { + "" + } + }; + + const size_t sha512_test_buflen[3] = + { + 3, 112, 1000 + }; + + const unsigned char sha512_test_sum[6][64] = + { + /* SHA-384 test vectors */ + + { + 0xcb, 0x00, 0x75, 0x3f, 0x45, 0xa3, 0x5e, 0x8b, + 0xb5, 0xa0, 0x3d, 0x69, 0x9a, 0xc6, 0x50, 0x07, + 0x27, 0x2c, 0x32, 0xab, 0x0e, 0xde, 0xd1, 0x63, + 0x1a, 0x8b, 0x60, 0x5a, 0x43, 0xff, 0x5b, 0xed, + 0x80, 0x86, 0x07, 0x2b, 0xa1, 0xe7, 0xcc, 0x23, + 0x58, 0xba, 0xec, 0xa1, 0x34, 0xc8, 0x25, 0xa7 + }, + + { + 0x09, 0x33, 0x0c, 0x33, 0xf7, 0x11, 0x47, 0xe8, + 0x3d, 0x19, 0x2f, 0xc7, 0x82, 0xcd, 0x1b, 0x47, + 0x53, 0x11, 0x1b, 0x17, 0x3b, 0x3b, 0x05, 0xd2, + 0x2f, 0xa0, 0x80, 0x86, 0xe3, 0xb0, 0xf7, 0x12, + 0xfc, 0xc7, 0xc7, 0x1a, 0x55, 0x7e, 0x2d, 0xb9, + 0x66, 0xc3, 0xe9, 0xfa, 0x91, 0x74, 0x60, 0x39 + }, + + { + 0x9d, 0x0e, 0x18, 0x09, 0x71, 0x64, 0x74, 0xcb, + 0x08, 0x6e, 0x83, 0x4e, 0x31, 0x0a, 0x4a, 0x1c, + 0xed, 0x14, 0x9e, 0x9c, 0x00, 0xf2, 0x48, 0x52, + 0x79, 0x72, 0xce, 0xc5, 0x70, 0x4c, 0x2a, 0x5b, + 0x07, 0xb8, 0xb3, 0xdc, 0x38, 0xec, 0xc4, 0xeb, + 0xae, 0x97, 0xdd, 0xd8, 0x7f, 0x3d, 0x89, 0x85 + }, + + /* SHA-512 test vectors */ + + { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, + 0xcc, 0x41, 0x73, 0x49, 0xae, 0x20, 0x41, 0x31, + 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, + 0x21, 0x92, 0x99, 0x2a, 0x27, 0x4f, 0xc1, 0xa8, + 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, + 0x2a, 0x9a, 0xc9, 0x4f, 0xa5, 0x4c, 0xa4, 0x9f + }, + + { + 0x8e, 0x95, 0x9b, 0x75, 0xda, 0xe3, 0x13, 0xda, + 0x8c, 0xf4, 0xf7, 0x28, 0x14, 0xfc, 0x14, 0x3f, + 0x8f, 0x77, 0x79, 0xc6, 0xeb, 0x9f, 0x7f, 0xa1, + 0x72, 0x99, 0xae, 0xad, 0xb6, 0x88, 0x90, 0x18, + 0x50, 0x1d, 0x28, 0x9e, 0x49, 0x00, 0xf7, 0xe4, + 0x33, 0x1b, 0x99, 0xde, 0xc4, 0xb5, 0x43, 0x3a, + 0xc7, 0xd3, 0x29, 0xee, 0xb6, 0xdd, 0x26, 0x54, + 0x5e, 0x96, 0xe5, 0x5b, 0x87, 0x4b, 0xe9, 0x09 + }, + + { + 0xe7, 0x18, 0x48, 0x3d, 0x0c, 0xe7, 0x69, 0x64, + 0x4e, 0x2e, 0x42, 0xc7, 0xbc, 0x15, 0xb4, 0x63, + 0x8e, 0x1f, 0x98, 0xb1, 0x3b, 0x20, 0x44, 0x28, + 0x56, 0x32, 0xa8, 0x03, 0xaf, 0xa9, 0x73, 0xeb, + 0xde, 0x0f, 0xf2, 0x44, 0x87, 0x7e, 0xa6, 0x0a, + 0x4c, 0xb0, 0x43, 0x2c, 0xe5, 0x77, 0xc3, 0x1b, + 0xeb, 0x00, 0x9c, 0x5c, 0x2c, 0x49, 0xaa, 0x2e, + 0x4e, 0xad, 0xb2, 0x17, 0xad, 0x8c, 0xc0, 0x9b + } + }; + + buf = calloc(1024, sizeof(unsigned char)); + if (NULL == buf) + { + if (verbose) + { + syslog(LOG_INFO, "Buffer allocation failed\n"); + } + + return (1); + } + + esp32c3_sha512_init(&ctx); + + for (i = 0; i < 6; i++) + { + j = i % 3; + k = i < 3; + + if (verbose) + { + syslog(LOG_INFO, " SHA-%d test #%d: ", 512 - k * 128, j + 1); + } + + ret = esp32c3_sha512_starts(&ctx, k); + if (ret != 0) + { + goto fail; + } + + if (j == 2) + { + memset(buf, 'a', buflen = 1000); + + for (j = 0; j < 1000; j++) + { + ret = esp32c3_sha512_update(&ctx, buf, buflen); + if (ret != 0) + { + goto fail; + } + } + } + else + { + ret = esp32c3_sha512_update(&ctx, + sha512_test_buf[j], + sha512_test_buflen[j]); + if (ret != 0) + { + goto fail; + } + } + + ret = esp32c3_sha512_finish(&ctx, sha512sum); + if (ret != 0) + { + goto fail; + } + + if (memcmp(sha512sum, sha512_test_sum[i], 64 - k * 16) != 0) + { + ret = 1; + goto fail; + } + + if (verbose) + { + syslog(LOG_INFO, "passed\n"); + } + } + + if (verbose) + { + syslog(LOG_INFO, "\n"); + } + + goto exit; + +fail: + if (verbose) + { + syslog(LOG_INFO, "failed\n"); + } + +exit: + esp32c3_sha512_free(&ctx); + free(buf); + + return (ret); +} + +/**************************************************************************** + * Name: esp32c3_sha_main + ****************************************************************************/ + +int esp32c3_sha_main(int argc, char *argv[]) +{ + int ret = 0; + + syslog(LOG_INFO, "----- BEGIN TEST -----\n"); + + esp32c3_sha_init(); + + ret = esp32c3_sha1_self_test(true); + if (ret) + { + goto test_end; + } + + ret = esp32c3_sha256_self_test(true); + if (ret) + { + goto test_end; + } + + ret = esp32c3_sha512_self_test(true); + if (ret) + { + goto test_end; + } + +test_end: + syslog(LOG_INFO, "----- END TEST -----\n"); + + syslog(LOG_INFO, "\n"); + + syslog(LOG_INFO, "----- RESULT: %s -----\n", + !ret ? "SUCCESS" : "FAILED"); + + return OK; +} + +#endif diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.h b/arch/risc-v/src/esp32c3/esp32c3_sha.h new file mode 100644 index 0000000000..962204c30a --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp32c3_sha.h @@ -0,0 +1,121 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum esp32c3_sha_type_e +{ + ESP32C3_SHA1_1 = 0, + ESP32C3_SHA2_224, + ESP32C3_SHA2_256, + ESP32C3_SHA3_384, + ESP32C3_SHA3_512, + ESP32C3_SHA_TYPE_MAX +}; + +enum esp32c3_sha_state_e +{ + ESP32C3_SHA_STATE_INIT, + ESP32C3_SHA_STATE_IN_PROCESS +}; + +/* SHA-1 context structure */ + +struct esp32c3_sha1_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[5]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-256 context structure */ + +struct esp32c3_sha256_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[8]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-512 context structure */ + +struct esp32c3_sha512_context_s +{ + uint64_t total[2]; /* number of bytes processed */ + uint64_t state[8]; /* intermediate digest state */ + uint8_t buffer[128]; /* data block being processed */ + + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/**************************************************************************** + * Name: esp32c3_sha_init + * + * Description: + * Initialize ESP32-C3 SHA hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h new file mode 100644 index 0000000000..f4d8189834 --- /dev/null +++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h @@ -0,0 +1,938 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SHA_MODE_REG register + * Defines the algorithm of SHA accelerator + */ + +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) + +/* SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the SHA algorithm. + */ + +#define SHA_MODE 0x00000007 +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007 +#define SHA_MODE_S 0 + +/* SHA_T_STRING_REG register + * String content register for calculating initial Hash Value (only + * effective for SHA-512/t) + */ + +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) + +/* SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_STRING 0xFFFFFFFF +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFF +#define SHA_T_STRING_S 0 + +/* SHA_T_LENGTH_REG register + * String length register for calculating initial Hash Value (only effective + * for SHA-512/t) + */ + +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) + +/* SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_LENGTH 0x0000003F +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003F +#define SHA_T_LENGTH_S 0 + +/* SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ + +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) + +/* SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Defines the DMA-SHA block number. + */ + +#define SHA_DMA_BLOCK_NUM 0x0000003F +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003F +#define SHA_DMA_BLOCK_NUM_S 0 + +/* SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ + +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) + +/* SHA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start Typical SHA calculation. + */ + +#define SHA_START (BIT(0)) +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x00000001 +#define SHA_START_S 0 + +/* SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ + +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) + +/* SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ + +#define SHA_CONTINUE (BIT(0)) +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x00000001 +#define SHA_CONTINUE_S 0 + +/* SHA_BUSY_REG register + * Indicates if SHA Accelerator is busy or not + */ + +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) + +/* SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Indicates the states of SHA accelerator. + * #1'h0: idle + * #1'h1: busy + */ + +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001 +#define SHA_BUSY_STATE_S 0 + +/* SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ + +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) + +/* SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001 +#define SHA_DMA_START_S 0 + +/* SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ + +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) + +/* SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001 +#define SHA_DMA_CONTINUE_S 0 + +/* SHA_INT_CLEAR_REG register + * DMA-SHA interrupt clear register + */ + +#define SHA_INT_CLEAR_REG (DR_REG_SHA_BASE + 0x24) + +/* SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clears DMA-SHA interrupt. + */ + +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001 +#define SHA_CLEAR_INTERRUPT_S 0 + +/* SHA_INT_ENA_REG register + * DMA-SHA interrupt enable register + */ + +#define SHA_INT_ENA_REG (DR_REG_SHA_BASE + 0x28) + +/* SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Enables DMA-SHA interrupt. + */ + +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001 +#define SHA_INTERRUPT_ENA_S 0 + +/* SHA_DATE_REG register + * Version control register. + */ + +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) + +/* SHA_DATE : R/W; bitpos: [29:0]; default: 538510338; + * Version control register + */ + +#define SHA_DATE 0x3FFFFFFF +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFF +#define SHA_DATE_S 0 + +/* SHA_H_0_REG register + * Hash value + */ + +#define SHA_H_0_REG (DR_REG_SHA_BASE + 0x40) + +/* SHA_H_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the Hash value. + */ + +#define SHA_H_0 0xFFFFFFFF +#define SHA_H_0_M (SHA_H_0_V << SHA_H_0_S) +#define SHA_H_0_V 0xFFFFFFFF +#define SHA_H_0_S 0 + +/* SHA_H_1_REG register + * Hash value + */ + +#define SHA_H_1_REG (DR_REG_SHA_BASE + 0x44) + +/* SHA_H_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the Hash value. + */ + +#define SHA_H_1 0xFFFFFFFF +#define SHA_H_1_M (SHA_H_1_V << SHA_H_1_S) +#define SHA_H_1_V 0xFFFFFFFF +#define SHA_H_1_S 0 + +/* SHA_H_2_REG register + * Hash value + */ + +#define SHA_H_2_REG (DR_REG_SHA_BASE + 0x48) + +/* SHA_H_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the Hash value. + */ + +#define SHA_H_2 0xFFFFFFFF +#define SHA_H_2_M (SHA_H_2_V << SHA_H_2_S) +#define SHA_H_2_V 0xFFFFFFFF +#define SHA_H_2_S 0 + +/* SHA_H_3_REG register + * Hash value + */ + +#define SHA_H_3_REG (DR_REG_SHA_BASE + 0x4c) + +/* SHA_H_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the Hash value. + */ + +#define SHA_H_3 0xFFFFFFFF +#define SHA_H_3_M (SHA_H_3_V << SHA_H_3_S) +#define SHA_H_3_V 0xFFFFFFFF +#define SHA_H_3_S 0 + +/* SHA_H_4_REG register + * Hash value + */ + +#define SHA_H_4_REG (DR_REG_SHA_BASE + 0x50) + +/* SHA_H_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the Hash value. + */ + +#define SHA_H_4 0xFFFFFFFF +#define SHA_H_4_M (SHA_H_4_V << SHA_H_4_S) +#define SHA_H_4_V 0xFFFFFFFF +#define SHA_H_4_S 0 + +/* SHA_H_5_REG register + * Hash value + */ + +#define SHA_H_5_REG (DR_REG_SHA_BASE + 0x54) + +/* SHA_H_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the Hash value. + */ + +#define SHA_H_5 0xFFFFFFFF +#define SHA_H_5_M (SHA_H_5_V << SHA_H_5_S) +#define SHA_H_5_V 0xFFFFFFFF +#define SHA_H_5_S 0 + +/* SHA_H_6_REG register + * Hash value + */ + +#define SHA_H_6_REG (DR_REG_SHA_BASE + 0x58) + +/* SHA_H_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the Hash value. + */ + +#define SHA_H_6 0xFFFFFFFF +#define SHA_H_6_M (SHA_H_6_V << SHA_H_6_S) +#define SHA_H_6_V 0xFFFFFFFF +#define SHA_H_6_S 0 + +/* SHA_H_7_REG register + * Hash value + */ + +#define SHA_H_7_REG (DR_REG_SHA_BASE + 0x5c) + +/* SHA_H_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the Hash value. + */ + +#define SHA_H_7 0xFFFFFFFF +#define SHA_H_7_M (SHA_H_7_V << SHA_H_7_S) +#define SHA_H_7_V 0xFFFFFFFF +#define SHA_H_7_S 0 + +/* SHA_H_8_REG register + * Hash value + */ + +#define SHA_H_8_REG (DR_REG_SHA_BASE + 0x60) + +/* SHA_H_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the Hash value. + */ + +#define SHA_H_8 0xFFFFFFFF +#define SHA_H_8_M (SHA_H_8_V << SHA_H_8_S) +#define SHA_H_8_V 0xFFFFFFFF +#define SHA_H_8_S 0 + +/* SHA_H_9_REG register + * Hash value + */ + +#define SHA_H_9_REG (DR_REG_SHA_BASE + 0x64) + +/* SHA_H_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the Hash value. + */ + +#define SHA_H_9 0xFFFFFFFF +#define SHA_H_9_M (SHA_H_9_V << SHA_H_9_S) +#define SHA_H_9_V 0xFFFFFFFF +#define SHA_H_9_S 0 + +/* SHA_H_10_REG register + * Hash value + */ + +#define SHA_H_10_REG (DR_REG_SHA_BASE + 0x68) + +/* SHA_H_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the Hash value. + */ + +#define SHA_H_10 0xFFFFFFFF +#define SHA_H_10_M (SHA_H_10_V << SHA_H_10_S) +#define SHA_H_10_V 0xFFFFFFFF +#define SHA_H_10_S 0 + +/* SHA_H_11_REG register + * Hash value + */ + +#define SHA_H_11_REG (DR_REG_SHA_BASE + 0x6c) + +/* SHA_H_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the Hash value. + */ + +#define SHA_H_11 0xFFFFFFFF +#define SHA_H_11_M (SHA_H_11_V << SHA_H_11_S) +#define SHA_H_11_V 0xFFFFFFFF +#define SHA_H_11_S 0 + +/* SHA_H_12_REG register + * Hash value + */ + +#define SHA_H_12_REG (DR_REG_SHA_BASE + 0x70) + +/* SHA_H_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the Hash value. + */ + +#define SHA_H_12 0xFFFFFFFF +#define SHA_H_12_M (SHA_H_12_V << SHA_H_12_S) +#define SHA_H_12_V 0xFFFFFFFF +#define SHA_H_12_S 0 + +/* SHA_H_13_REG register + * Hash value + */ + +#define SHA_H_13_REG (DR_REG_SHA_BASE + 0x74) + +/* SHA_H_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the Hash value. + */ + +#define SHA_H_13 0xFFFFFFFF +#define SHA_H_13_M (SHA_H_13_V << SHA_H_13_S) +#define SHA_H_13_V 0xFFFFFFFF +#define SHA_H_13_S 0 + +/* SHA_H_14_REG register + * Hash value + */ + +#define SHA_H_14_REG (DR_REG_SHA_BASE + 0x78) + +/* SHA_H_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the Hash value. + */ + +#define SHA_H_14 0xFFFFFFFF +#define SHA_H_14_M (SHA_H_14_V << SHA_H_14_S) +#define SHA_H_14_V 0xFFFFFFFF +#define SHA_H_14_S 0 + +/* SHA_H_15_REG register + * Hash value + */ + +#define SHA_H_15_REG (DR_REG_SHA_BASE + 0x7c) + +/* SHA_H_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the Hash value. + */ + +#define SHA_H_15 0xFFFFFFFF +#define SHA_H_15_M (SHA_H_15_V << SHA_H_15_S) +#define SHA_H_15_V 0xFFFFFFFF +#define SHA_H_15_S 0 + +/* SHA_M_0_REG register + * Message + */ + +#define SHA_M_0_REG (DR_REG_SHA_BASE + 0x80) + +/* SHA_M_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the message. + */ + +#define SHA_M_0 0xFFFFFFFF +#define SHA_M_0_M (SHA_M_0_V << SHA_M_0_S) +#define SHA_M_0_V 0xFFFFFFFF +#define SHA_M_0_S 0 + +/* SHA_M_1_REG register + * Message + */ + +#define SHA_M_1_REG (DR_REG_SHA_BASE + 0x84) + +/* SHA_M_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the message. + */ + +#define SHA_M_1 0xFFFFFFFF +#define SHA_M_1_M (SHA_M_1_V << SHA_M_1_S) +#define SHA_M_1_V 0xFFFFFFFF +#define SHA_M_1_S 0 + +/* SHA_M_2_REG register + * Message + */ + +#define SHA_M_2_REG (DR_REG_SHA_BASE + 0x88) + +/* SHA_M_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the message. + */ + +#define SHA_M_2 0xFFFFFFFF +#define SHA_M_2_M (SHA_M_2_V << SHA_M_2_S) +#define SHA_M_2_V 0xFFFFFFFF +#define SHA_M_2_S 0 + +/* SHA_M_3_REG register + * Message + */ + +#define SHA_M_3_REG (DR_REG_SHA_BASE + 0x8c) + +/* SHA_M_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the message. + */ + +#define SHA_M_3 0xFFFFFFFF +#define SHA_M_3_M (SHA_M_3_V << SHA_M_3_S) +#define SHA_M_3_V 0xFFFFFFFF +#define SHA_M_3_S 0 + +/* SHA_M_4_REG register + * Message + */ + +#define SHA_M_4_REG (DR_REG_SHA_BASE + 0x90) + +/* SHA_M_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the message. + */ + +#define SHA_M_4 0xFFFFFFFF +#define SHA_M_4_M (SHA_M_4_V << SHA_M_4_S) +#define SHA_M_4_V 0xFFFFFFFF +#define SHA_M_4_S 0 + +/* SHA_M_5_REG register + * Message + */ + +#define SHA_M_5_REG (DR_REG_SHA_BASE + 0x94) + +/* SHA_M_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the message. + */ + +#define SHA_M_5 0xFFFFFFFF +#define SHA_M_5_M (SHA_M_5_V << SHA_M_5_S) +#define SHA_M_5_V 0xFFFFFFFF +#define SHA_M_5_S 0 + +/* SHA_M_6_REG register + * Message + */ + +#define SHA_M_6_REG (DR_REG_SHA_BASE + 0x98) + +/* SHA_M_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the message. + */ + +#define SHA_M_6 0xFFFFFFFF +#define SHA_M_6_M (SHA_M_6_V << SHA_M_6_S) +#define SHA_M_6_V 0xFFFFFFFF +#define SHA_M_6_S 0 + +/* SHA_M_7_REG register + * Message + */ + +#define SHA_M_7_REG (DR_REG_SHA_BASE + 0x9c) + +/* SHA_M_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the message. + */ + +#define SHA_M_7 0xFFFFFFFF +#define SHA_M_7_M (SHA_M_7_V << SHA_M_7_S) +#define SHA_M_7_V 0xFFFFFFFF +#define SHA_M_7_S 0 + +/* SHA_M_8_REG register + * Message + */ + +#define SHA_M_8_REG (DR_REG_SHA_BASE + 0xa0) + +/* SHA_M_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the message. + */ + +#define SHA_M_8 0xFFFFFFFF +#define SHA_M_8_M (SHA_M_8_V << SHA_M_8_S) +#define SHA_M_8_V 0xFFFFFFFF +#define SHA_M_8_S 0 + +/* SHA_M_9_REG register + * Message + */ + +#define SHA_M_9_REG (DR_REG_SHA_BASE + 0xa4) + +/* SHA_M_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the message. + */ + +#define SHA_M_9 0xFFFFFFFF +#define SHA_M_9_M (SHA_M_9_V << SHA_M_9_S) +#define SHA_M_9_V 0xFFFFFFFF +#define SHA_M_9_S 0 + +/* SHA_M_10_REG register + * Message + */ + +#define SHA_M_10_REG (DR_REG_SHA_BASE + 0xa8) + +/* SHA_M_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the message. + */ + +#define SHA_M_10 0xFFFFFFFF +#define SHA_M_10_M (SHA_M_10_V << SHA_M_10_S) +#define SHA_M_10_V 0xFFFFFFFF +#define SHA_M_10_S 0 + +/* SHA_M_11_REG register + * Message + */ + +#define SHA_M_11_REG (DR_REG_SHA_BASE + 0xac) + +/* SHA_M_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the message. + */ + +#define SHA_M_11 0xFFFFFFFF +#define SHA_M_11_M (SHA_M_11_V << SHA_M_11_S) +#define SHA_M_11_V 0xFFFFFFFF +#define SHA_M_11_S 0 + +/* SHA_M_12_REG register + * Message + */ + +#define SHA_M_12_REG (DR_REG_SHA_BASE + 0xb0) + +/* SHA_M_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the message. + */ + +#define SHA_M_12 0xFFFFFFFF +#define SHA_M_12_M (SHA_M_12_V << SHA_M_12_S) +#define SHA_M_12_V 0xFFFFFFFF +#define SHA_M_12_S 0 + +/* SHA_M_13_REG register + * Message + */ + +#define SHA_M_13_REG (DR_REG_SHA_BASE + 0xb4) + +/* SHA_M_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the message. + */ + +#define SHA_M_13 0xFFFFFFFF +#define SHA_M_13_M (SHA_M_13_V << SHA_M_13_S) +#define SHA_M_13_V 0xFFFFFFFF +#define SHA_M_13_S 0 + +/* SHA_M_14_REG register + * Message + */ + +#define SHA_M_14_REG (DR_REG_SHA_BASE + 0xb8) + +/* SHA_M_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the message. + */ + +#define SHA_M_14 0xFFFFFFFF +#define SHA_M_14_M (SHA_M_14_V << SHA_M_14_S) +#define SHA_M_14_V 0xFFFFFFFF +#define SHA_M_14_S 0 + +/* SHA_M_15_REG register + * Message + */ + +#define SHA_M_15_REG (DR_REG_SHA_BASE + 0xbc) + +/* SHA_M_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the message. + */ + +#define SHA_M_15 0xFFFFFFFF +#define SHA_M_15_M (SHA_M_15_V << SHA_M_15_S) +#define SHA_M_15_V 0xFFFFFFFF +#define SHA_M_15_S 0 + +/* SHA_M_16_REG register + * Message + */ + +#define SHA_M_16_REG (DR_REG_SHA_BASE + 0xc0) + +/* SHA_M_16 : R/W; bitpos: [31:0]; default: 0; + * Stores the 16th 32-bit piece of the message. + */ + +#define SHA_M_16 0xFFFFFFFF +#define SHA_M_16_M (SHA_M_16_V << SHA_M_16_S) +#define SHA_M_16_V 0xFFFFFFFF +#define SHA_M_16_S 0 + +/* SHA_M_17_REG register + * Message + */ + +#define SHA_M_17_REG (DR_REG_SHA_BASE + 0xc4) + +/* SHA_M_17 : R/W; bitpos: [31:0]; default: 0; + * Stores the 17th 32-bit piece of the message. + */ + +#define SHA_M_17 0xFFFFFFFF +#define SHA_M_17_M (SHA_M_17_V << SHA_M_17_S) +#define SHA_M_17_V 0xFFFFFFFF +#define SHA_M_17_S 0 + +/* SHA_M_18_REG register + * Message + */ + +#define SHA_M_18_REG (DR_REG_SHA_BASE + 0xc8) + +/* SHA_M_18 : R/W; bitpos: [31:0]; default: 0; + * Stores the 18th 32-bit piece of the message. + */ + +#define SHA_M_18 0xFFFFFFFF +#define SHA_M_18_M (SHA_M_18_V << SHA_M_18_S) +#define SHA_M_18_V 0xFFFFFFFF +#define SHA_M_18_S 0 + +/* SHA_M_19_REG register + * Message + */ + +#define SHA_M_19_REG (DR_REG_SHA_BASE + 0xcc) + +/* SHA_M_19 : R/W; bitpos: [31:0]; default: 0; + * Stores the 19th 32-bit piece of the message. + */ + +#define SHA_M_19 0xFFFFFFFF +#define SHA_M_19_M (SHA_M_19_V << SHA_M_19_S) +#define SHA_M_19_V 0xFFFFFFFF +#define SHA_M_19_S 0 + +/* SHA_M_20_REG register + * Message + */ + +#define SHA_M_20_REG (DR_REG_SHA_BASE + 0xd0) + +/* SHA_M_20 : R/W; bitpos: [31:0]; default: 0; + * Stores the 20th 32-bit piece of the message. + */ + +#define SHA_M_20 0xFFFFFFFF +#define SHA_M_20_M (SHA_M_20_V << SHA_M_20_S) +#define SHA_M_20_V 0xFFFFFFFF +#define SHA_M_20_S 0 + +/* SHA_M_21_REG register + * Message + */ + +#define SHA_M_21_REG (DR_REG_SHA_BASE + 0xd4) + +/* SHA_M_21 : R/W; bitpos: [31:0]; default: 0; + * Stores the 21th 32-bit piece of the message. + */ + +#define SHA_M_21 0xFFFFFFFF +#define SHA_M_21_M (SHA_M_21_V << SHA_M_21_S) +#define SHA_M_21_V 0xFFFFFFFF +#define SHA_M_21_S 0 + +/* SHA_M_22_REG register + * Message + */ + +#define SHA_M_22_REG (DR_REG_SHA_BASE + 0xd8) + +/* SHA_M_22 : R/W; bitpos: [31:0]; default: 0; + * Stores the 22th 32-bit piece of the message. + */ + +#define SHA_M_22 0xFFFFFFFF +#define SHA_M_22_M (SHA_M_22_V << SHA_M_22_S) +#define SHA_M_22_V 0xFFFFFFFF +#define SHA_M_22_S 0 + +/* SHA_M_23_REG register + * Message + */ + +#define SHA_M_23_REG (DR_REG_SHA_BASE + 0xdc) + +/* SHA_M_23 : R/W; bitpos: [31:0]; default: 0; + * Stores the 23th 32-bit piece of the message. + */ + +#define SHA_M_23 0xFFFFFFFF +#define SHA_M_23_M (SHA_M_23_V << SHA_M_23_S) +#define SHA_M_23_V 0xFFFFFFFF +#define SHA_M_23_S 0 + +/* SHA_M_24_REG register + * Message + */ + +#define SHA_M_24_REG (DR_REG_SHA_BASE + 0xe0) + +/* SHA_M_24 : R/W; bitpos: [31:0]; default: 0; + * Stores the 24th 32-bit piece of the message. + */ + +#define SHA_M_24 0xFFFFFFFF +#define SHA_M_24_M (SHA_M_24_V << SHA_M_24_S) +#define SHA_M_24_V 0xFFFFFFFF +#define SHA_M_24_S 0 + +/* SHA_M_25_REG register + * Message + */ + +#define SHA_M_25_REG (DR_REG_SHA_BASE + 0xe4) + +/* SHA_M_25 : R/W; bitpos: [31:0]; default: 0; + * Stores the 25th 32-bit piece of the message. + */ + +#define SHA_M_25 0xFFFFFFFF +#define SHA_M_25_M (SHA_M_25_V << SHA_M_25_S) +#define SHA_M_25_V 0xFFFFFFFF +#define SHA_M_25_S 0 + +/* SHA_M_26_REG register + * Message + */ + +#define SHA_M_26_REG (DR_REG_SHA_BASE + 0xe8) + +/* SHA_M_26 : R/W; bitpos: [31:0]; default: 0; + * Stores the 26th 32-bit piece of the message. + */ + +#define SHA_M_26 0xFFFFFFFF +#define SHA_M_26_M (SHA_M_26_V << SHA_M_26_S) +#define SHA_M_26_V 0xFFFFFFFF +#define SHA_M_26_S 0 + +/* SHA_M_27_REG register + * Message + */ + +#define SHA_M_27_REG (DR_REG_SHA_BASE + 0xec) + +/* SHA_M_27 : R/W; bitpos: [31:0]; default: 0; + * Stores the 27th 32-bit piece of the message. + */ + +#define SHA_M_27 0xFFFFFFFF +#define SHA_M_27_M (SHA_M_27_V << SHA_M_27_S) +#define SHA_M_27_V 0xFFFFFFFF +#define SHA_M_27_S 0 + +/* SHA_M_28_REG register + * Message + */ + +#define SHA_M_28_REG (DR_REG_SHA_BASE + 0xf0) + +/* SHA_M_28 : R/W; bitpos: [31:0]; default: 0; + * Stores the 28th 32-bit piece of the message. + */ + +#define SHA_M_28 0xFFFFFFFF +#define SHA_M_28_M (SHA_M_28_V << SHA_M_28_S) +#define SHA_M_28_V 0xFFFFFFFF +#define SHA_M_28_S 0 + +/* SHA_M_29_REG register + * Message + */ + +#define SHA_M_29_REG (DR_REG_SHA_BASE + 0xf4) + +/* SHA_M_29 : R/W; bitpos: [31:0]; default: 0; + * Stores the 29th 32-bit piece of the message. + */ + +#define SHA_M_29 0xFFFFFFFF +#define SHA_M_29_M (SHA_M_29_V << SHA_M_29_S) +#define SHA_M_29_V 0xFFFFFFFF +#define SHA_M_29_S 0 + +/* SHA_M_30_REG register + * Message + */ + +#define SHA_M_30_REG (DR_REG_SHA_BASE + 0xf8) + +/* SHA_M_30 : R/W; bitpos: [31:0]; default: 0; + * Stores the 30th 32-bit piece of the message. + */ + +#define SHA_M_30 0xFFFFFFFF +#define SHA_M_30_M (SHA_M_30_V << SHA_M_30_S) +#define SHA_M_30_V 0xFFFFFFFF +#define SHA_M_30_S 0 + +/* SHA_M_31_REG register + * Message + */ + +#define SHA_M_31_REG (DR_REG_SHA_BASE + 0xfc) + +/* SHA_M_31 : R/W; bitpos: [31:0]; default: 0; + * Stores the 31th 32-bit piece of the message. + */ + +#define SHA_M_31 0xFFFFFFFF +#define SHA_M_31_M (SHA_M_31_V << SHA_M_31_S) +#define SHA_M_31_V 0xFFFFFFFF +#define SHA_M_31_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig new file mode 100644 index 0000000000..66c776dc2f --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_SHA_ACCELERATOR=y +CONFIG_ESP32C3_SHA_ACCELERATOR_TEST=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MAX_TASKS=16 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="esp32c3_sha_main" diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index 5763e8fcfb..550a1339b3 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -59,6 +59,10 @@ # include "esp32c3_efuse.h" #endif +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR +# include "esp32c3_sha.h" +#endif + #ifdef CONFIG_RTC_DRIVER # include "esp32c3_rtc_lowerhalf.h" #endif @@ -137,6 +141,15 @@ int esp32c3_bringup(void) } #endif +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR + ret = esp32c3_sha_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SHA: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */