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Fix the nxlines configuration for the zp214xpa board

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5467 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-12-30 21:12:43 +00:00
parent 5fe6ab5fc3
commit 2df3b8a2d0
6 changed files with 67 additions and 44 deletions
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6
ChangeLog
View File

@ -3843,6 +3843,6 @@
* configs/sim/nxlines: Add an nxlines configuration for the
simulator.
* configs/zp214xpa/nxlines: Add an nxlines configuration for the
ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). As of this
writing (2012-12-30), I see only garbage on the display each time
the display is updated.
ZP213x/4xPA (with the LPC2148 and the UG_2864AMBAG01). Working
as of 2012-12-30.

26
configs/mcu123-lpc214x/src/up_spi1.c
View File

@ -85,20 +85,16 @@
* Definitions
****************************************************************************/
/* Enables debug output from this file (needs CONFIG_DEBUG too) */
/* Enables debug output from this file */
#undef SPI_DEBUG /* Define to enable debug */
#undef SPI_VERBOSE /* Define to enable verbose debug */
#ifdef SPI_DEBUG
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef SPI_VERBOSE
# ifdef CONFIG_DEBUG_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
@ -125,17 +121,17 @@
****************************************************************************/
#ifndef CONFIG_SPI_OWNBUS
static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
#endif
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t ch);
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords);
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords);
/****************************************************************************
* Private Data
@ -224,14 +220,14 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sel
{
/* Enable slave select (low enables) */
spidbg("CD asserted\n");
spidbg("CS asserted\n");
putreg32(bit, CS_CLR_REGISTER);
}
else
{
/* Disable slave select (low enables) */
spidbg("CD de-asserted\n");
spidbg("CS de-asserted\n");
putreg32(bit, CS_SET_REGISTER);
/* Wait for the TX FIFO not full indication */

2
configs/zp214xpa/README.txt
View File

@ -338,3 +338,5 @@ Configurations:
CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too).
CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : Buildroot (arm-nuttx-elf-gcc)
CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary
3. Verified as of this writing (2012-12-30).

44
configs/zp214xpa/src/up_spi1.c
View File

@ -86,20 +86,16 @@
* Definitions
****************************************************************************/
/* Enables debug output from this file (needs CONFIG_DEBUG too) */
/* Enables debug output from this file */
#undef SPI_DEBUG /* Define to enable debug */
#undef SPI_VERBOSE /* Define to enable verbose debug */
#ifdef SPI_DEBUG
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef SPI_VERBOSE
# ifdef CONFIG_DEBUG_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
@ -112,10 +108,12 @@
/* Use either FIO or legacy GPIO */
#ifdef CONFIG_LPC214x_FIO
# define CS_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET)
# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET)
#else
# define CS_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET)
# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET)
@ -130,7 +128,7 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock);
#endif
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency);
static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
#endif
@ -193,7 +191,7 @@ static struct spi_dev_s g_spidev = { &g_spiops };
#ifndef CONFIG_SPI_OWNBUS
static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
{
/* Not implemented */
/* Not implemented -- the UG_2864AMBAG01 is the only device on SPI1 */
return -ENOSYS;
}
@ -219,25 +217,32 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
#ifdef CONFIG_DEBUG_SPI
uint32_t regval;
#endif
uint32_t bit = 1 << 20;
/* We do not bother to check if devid == SPIDEV_DISPLAY because that is the
* only thing on the bus.
*/
#ifdef CONFIG_DEBUG_SPI
regval = getreg32(CS_PIN_REGISTER);
#endif
if (selected)
{
/* Enable slave select (low enables) */
spidbg("CD asserted\n");
putreg32(bit, CS_CLR_REGISTER);
spidbg("CS asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
}
else
{
/* Disable slave select (low enables) */
spidbg("CD de-asserted\n");
putreg32(bit, CS_SET_REGISTER);
spidbg("CS de-asserted: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
/* Wait for the TX FIFO not full indication */
@ -345,6 +350,9 @@ static uint8_t spi_status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
#ifdef CONFIG_DEBUG_SPI
uint32_t regval;
#endif
uint32_t bit = 1 << 23;
/* We do not bother to check if devid == SPIDEV_DISPLAY because that is the
@ -358,19 +366,23 @@ static int spi_cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd
* A0 = L: the inputs at D0 to D7 are transferred to the command registers."
*/
#ifdef CONFIG_DEBUG_SPI
regval = getreg32(CS_PIN_REGISTER);
#endif
if (cmd)
{
/* L: the inputs at D0 to D7 are transferred to the command registers */
spidbg("Command\n");
putreg32(bit, CS_CLR_REGISTER);
spidbg("Command: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
}
else
{
/* H: the inputs at D0 to D7 are treated as display data. */
spidbg("CD de-asserted\n");
putreg32(bit, CS_SET_REGISTER);
spidbg("Data: %08x->%08x\n", regval, getreg32(CS_PIN_REGISTER));
}
return OK;
@ -606,11 +618,15 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
* for commands (also low)
*/
regval32 = (1 << 20) || (1 << 23);
regval32 = (1 << 20) | (1 << 23);
putreg32(regval32, CS_SET_REGISTER);
regval32 |= getreg32(CS_DIR_REGISTER);
putreg32(regval32, CS_DIR_REGISTER);
spidbg("CS Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n",
getreg32(LPC214X_PINSEL1), getreg32(CS_PIN_REGISTER),
getreg32(CS_DIR_REGISTER));
/* Enable peripheral clocking to SPI1 */
regval32 = getreg32(LPC214X_PCON_PCONP);

29
configs/zp214xpa/src/up_ug2864ambag01.c
View File

@ -85,13 +85,15 @@
/* Use either FIO or legacy GPIO */
#ifdef CONFIG_LPC214x_FIO
# define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET)
# define RESET_PIN_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_PIN_OFFSET)
# define RESET_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET)
# define RESET_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET)
# define RESET_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET)
#else
# define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET)
# define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET)
# define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET)
# define RESET_PIN_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_PIN_OFFSET)
# define RESET_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET)
# define RESET_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET)
# define RESET_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET)
#endif
/* Debug ********************************************************************/
@ -136,14 +138,21 @@ FAR struct lcd_dev_s *up_nxdrvinit(unsigned int devno)
/* Set the RESET line low, putting the OLED into the reset state. */
bits32 = (1 << 18);
putreg32(bits32, CS_CLR_REGISTER);
regval32 = getreg32(CS_DIR_REGISTER);
putreg32(regval32 | bits32, CS_DIR_REGISTER);
putreg32(bits32, RESET_CLR_REGISTER);
regval32 = getreg32(RESET_DIR_REGISTER);
putreg32(regval32 | bits32, RESET_DIR_REGISTER);
lcdvdbg("RESET Pin Config: PINSEL1: %08x PIN: %08x DIR: %08x\n",
getreg32(LPC214X_PINSEL1), getreg32(RESET_PIN_REGISTER),
getreg32(RESET_DIR_REGISTER));
/* Wait a bit then release the OLED from the reset state */
up_mdelay(20);
putreg32(bits32, CS_SET_REGISTER);
putreg32(bits32, RESET_SET_REGISTER);
lcdvdbg("RESET release: PIN: %08x DIR: %08x\n",
getreg32(RESET_PIN_REGISTER), getreg32(RESET_DIR_REGISTER));
/* Get the SPI1 port interface */

4
drivers/lcd/ug-2864ambag01.c
View File

@ -1148,8 +1148,8 @@ void ug2864ambag01_fill(FAR struct lcd_dev_s *dev, uint8_t color)
/* Transfer one page of the selected color */
(void)SPI_SNDBLOCK(priv->spi, &priv->fb[page * UG2864AMBAG01_XRES],
UG2864AMBAG01_XRES);
(void)SPI_SNDBLOCK(priv->spi, &priv->fb[page * UG2864AMBAG01_XRES],
UG2864AMBAG01_XRES);
}
/* De-select and unlock the device */