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arch/arm/src/stm32l4: Make STM32L4 CRS synchronization source board configurable.

Browse Source 
configs/nucleo-l432kc:  Add new configuration settings to board.h
configs/nucleo-l452re: ditto
configs/nucleo-l496zg: ditto
configs/stm32l476vg-disco: ditto
This commit is contained in:
Juha Niskanen 2019-05-21 10:21:57 -06:00 committed by Gregory Nutt
parent 9932ddb1f6
commit 2df7235536
12 changed files with 128 additions and 86 deletions
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4
arch/arm/src/stm32f0l0/stm32_hsi48.c
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@ -46,9 +46,9 @@
#include "stm32_hsi48.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_STM32F0)
# define STM32_HSI48_REG STM32_RCC_CR2

2
arch/arm/src/stm32f7/stm32_qspi.h
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_qspi.h
* arch/arm/src/stm32f7/stm32_qspi.h
*
* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
* Author: dev@ziggurat29.com

13
arch/arm/src/stm32l4/stm32l4_hsi48.c
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@ -97,17 +97,16 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
regval |= RCC_CRRCR_HSI48ON;
putreg32(regval, STM32L4_RCC_CRRCR);
if (syncsrc == SYNCSRC_USB)
{
/* Select the HSI48 as the USB clock source */
/* For the STM32L4, this is done in RCC. */
}
/* Wait for the HSI48 clock to stabilize */
while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
/* Return if no synchronization */
if (syncsrc == SYNCSRC_NONE)
{
return;
}
/* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
* register, can be the signal from the external CRS_SYNC pin, the LSE

19
arch/arm/src/stm32l4/stm32l4_hsi48.h
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@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/stm32l4/stm32l4_hsi48.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -32,33 +32,34 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H
#define __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_STM32L4_HAVE_HSI48
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
enum syncsrc_e
{
SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */
SYNCSRC_NONE = 0, /* No SYNC signal */
SYNCSRC_GPIO, /* GPIO selected as SYNC signal source */
SYNCSRC_LSE, /* LSE selected as SYNC signal source */
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
};
/************************************************************************************
/****************************************************************************
* Public Functions
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Name: stm32l4_enable_hsi48

11
arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
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@ -370,9 +370,12 @@ static inline void rcc_enableapb1(void)
#endif
#ifdef STM32L4_USE_HSI48
/* Clock Recovery System clock enable */
if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
{
/* Clock Recovery System clock enable */
regval |= RCC_APB1ENR1_CRSEN;
regval |= RCC_APB1ENR1_CRSEN;
}
#endif
/* Power interface clock enable. The PWR block is always enabled so that
@ -911,7 +914,9 @@ static inline void rcc_enableperipherals(void)
rcc_enableapb2();
#ifdef STM32L4_USE_HSI48
stm32l4_enable_hsi48(SYNCSRC_USB);
/* Enable HSI48 clocking to to support USB transfers or RNG */
stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
#endif
}

11
arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
View File

@ -426,9 +426,12 @@ static inline void rcc_enableapb1(void)
#endif
#ifdef STM32L4_USE_HSI48
/* Clock Recovery System clock enable */
if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
{
/* Clock Recovery System clock enable */
regval |= RCC_APB1ENR1_CRSEN;
regval |= RCC_APB1ENR1_CRSEN;
}
#endif
/* Power interface clock enable. The PWR block is always enabled so that
@ -979,7 +982,9 @@ static inline void rcc_enableperipherals(void)
rcc_enableapb2();
#ifdef STM32L4_USE_HSI48
stm32l4_enable_hsi48(SYNCSRC_USB);
/* Enable HSI48 clocking to to support USB transfers or RNG */
stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
#endif
}

11
arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
View File

@ -413,9 +413,12 @@ static inline void rcc_enableapb1(void)
#endif
#ifdef STM32L4_USE_HSI48
/* Clock Recovery System clock enable */
if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
{
/* Clock Recovery System clock enable */
regval |= RCC_APB1ENR1_CRSEN;
regval |= RCC_APB1ENR1_CRSEN;
}
#endif
/* Power interface clock enable. The PWR block is always enabled so that
@ -972,7 +975,9 @@ static inline void rcc_enableperipherals(void)
rcc_enableapb2();
#ifdef STM32L4_USE_HSI48
stm32l4_enable_hsi48(SYNCSRC_USB);
/* Enable HSI48 clocking to to support USB transfers or RNG */
stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
#endif
}

21
configs/nucleo-l432kc/include/nucleo-l432kc.h
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@ -255,8 +255,11 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
@ -348,8 +351,11 @@
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */
@ -440,8 +446,11 @@
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */

70
configs/nucleo-l452re/include/nucleo-l452re.h
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@ -49,19 +49,8 @@
* Pre-processor Definitions
************************************************************************************/
#if 1
# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
#elif 0
/* Make sure you installed one! */
# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
#else
# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
#endif
/* Clocking *************************************************************************/
#if defined(HSI_CLOCK_CONFIG)
/* The NUCLEOL452RE supports both HSE and LSE crystals (X2 and X3). However, as
* shipped, the X3 crystal is not populated. Therefore the Nucleo-L452RE
* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
@ -97,6 +86,18 @@
#define STM32L4_LSI_FREQUENCY 32000
#define STM32L4_LSE_FREQUENCY 32768
#if 1
# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
#elif 0
/* Make sure you installed one! */
# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
#else
# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
#endif
#if defined(HSI_CLOCK_CONFIG)
#define STM32L4_BOARD_USEHSI 1
/* XXX sysclk mux = pllclk */
@ -223,23 +224,13 @@
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
#define STM32L4_PLLCFG_PLLR_ENABLED
/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
* do that with the main PLL's N value. We set N = 12, and enable
* the Q output (ultimately for CLK48) with /4. So,
* 16 MHz / 1 * 12 / 4 = 48 MHz
*
* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
* menuconfig, or else all this is a moot point, and the various 48 MHz
* peripherals will not work (RNG at present). I would suggest removing
* that option from Kconfig altogether, and simply making it an option
* that is selected via a #define here, like all these other params.
*/
/* 'SAIPLL1' is not used in this application */
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ 0
#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR 0
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
@ -253,10 +244,13 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* CLK48 will come from PLLSAI1 (implicitly Q) */
/* CLK48 will come from HSI48 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
@ -351,8 +345,11 @@
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */
@ -410,13 +407,13 @@
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
#define STM32L4_PLLCFG_PLLR_ENABLED
/* 'SAIPLL1' is used to generate the 48 MHz clock */
/* 'SAIPLL1' is not used in this application */
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ 0
#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR 0
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
@ -430,10 +427,13 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* Enable CLK48; get it from PLLSAI1 */
/* Enable CLK48; get it from HSI48 */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */

21
configs/nucleo-l496zg/include/board.h
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@ -137,8 +137,11 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
@ -241,8 +244,11 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
@ -346,8 +352,11 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */

10
configs/stm32l476vg-disco/scripts/memory.ld
View File

@ -1,5 +1,5 @@
/****************************************************************************
* configs/stm32f4discovery/scripts/memory.ld
* configs/stm32l476vg-disco/scripts/memory.ld
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -47,14 +47,14 @@
* For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
* FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which
* should fit into 64KB and, of course, can be optimized as needed (See
* also configs/stm32f4discovery/scripts/kernel-space.ld). Allowing the
* also configs/stm32l476vg-disco/scripts/kernel-space.ld). Allowing the
* additional does permit addition debug instrumentation to be added to the
* kernel space without overflowing the partition.
*
* Alignment of the user space FLASH partition is also a critical factor:
* The user space FLASH partition will be spanned with a single region of
* size 2**n bytes. The alignment of the user-space region must be the same.
* As a consequence, as the user-space increases in size, the alignmment
* As a consequence, as the user-space increases in size, the alignment
* requirement also increases.
*
* This alignment requirement means that the largest user space FLASH region
@ -95,6 +95,6 @@ MEMORY
/* 96Kb of contiguous SRAM */
ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
usram (rwx) : ORIGIN = 0x20001000, LENGTH = 8K
xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 80K
usram (rwx) : ORIGIN = 0x20002000, LENGTH = 8K
xsram (rwx) : ORIGIN = 0x20004000, LENGTH = 80K
}

21
configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h
View File

@ -145,8 +145,11 @@
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
@ -248,8 +251,11 @@
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */
@ -338,8 +344,11 @@
/* Enable CLK48; get it from PLLSAI1 */
#define STM32L4_USE_CLK48 1
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
# define STM32L4_USE_CLK48 1
# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE
#endif
/* Enable LSE (for the RTC) */