More stm32f3discovery updates
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5624 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
426f8f0214
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2df878981d
@ -120,9 +120,12 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
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/* The following requires exclusive access to the GPIO registers */
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flags = irqsave();
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#if defined(CONFIG_STM32_STM32F10XX)
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_APB2ENR) & RCC_APB2ENR_IOPEN(port)) != 0)
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{
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lldbg(" CR: %08x %08x IDR: %04x ODR: %04x LCKR: %04x\n",
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@ -143,11 +146,38 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
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lldbg(" GPIO%c not enabled: APB2ENR: %08x\n",
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g_portchar[port], getreg32(STM32_RCC_APB2ENR));
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}
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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#elif defined(CONFIG_STM32_STM32F30XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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/* GPIOs are always enabled */
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lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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getreg32(base + STM32_GPIO_MODER_OFFSET),
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getreg32(base + STM32_GPIO_OTYPER_OFFSET),
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getreg32(base + STM32_GPIO_OSPEED_OFFSET),
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getreg32(base + STM32_GPIO_PUPDR_OFFSET));
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lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
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getreg32(base + STM32_GPIO_IDR_OFFSET),
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getreg32(base + STM32_GPIO_ODR_OFFSET),
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getreg32(base + STM32_GPIO_BSRR_OFFSET),
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getreg32(base + STM32_GPIO_LCKR_OFFSET));
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lldbg(" AFRH: %08x AFRL: %08x BRR: %04x\n",
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getreg32(base + STM32_GPIO_ARFH_OFFSET),
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getreg32(base + STM32_GPIO_AFRL_OFFSET),
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getreg32(base + STM32_GPIO_BRR_OFFSET));
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#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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DEBUGASSERT(port < STM32_NGPIO_PORTS);
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lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
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g_portchar[port], pinset, base, msg);
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if ((getreg32(STM32_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
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{
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lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
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@ -14,10 +14,9 @@ Contents
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- NuttX OABI "buildroot" Toolchain
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- NXFLAT Toolchain
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- LEDs
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- PWM
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- UARTs
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- Timer Inputs/Outputs
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- Serial Console
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- FPU
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- Debugging
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- STM32F3Discovery-specific Configuration Options
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- Configurations
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@ -307,101 +306,24 @@ events as follows:
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LED_PANIC The system has crashed LD10 Blinking at 2Hz
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LED_IDLE STM32 is is sleep mode (Optional, not used)
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PWM
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===
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Serial Console
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==============
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The STM32F3Discovery has no real on-board PWM devices, but the board can be
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configured to output a pulse train using TIM4 CH2 on PD3. This pin is
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available next to the audio jack.
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The STM32F3Discovery has no on-board RS-232 driver, however USART2 is
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configuration as the serial console in all configurations that use a serial
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console.
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UARTs
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=====
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There are many options for USART2 RX and TX pins. They configured to use
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PA2 (TX) and PA3 (RX) for connection to an external serial device because of
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the following settings in the include/board.h file:
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UART/USART PINS
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---------------
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#define GPIO_USART2_RX GPIO_USART2_RX_2
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#define GPIO_USART2_TX GPIO_USART2_TX_2
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USART1
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CK PA8
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CTS PA11*
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RTS PA12*
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RX PA10*, PB7
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TX PA9*, PB6*
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USART2
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CK PA4*, PD7
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CTS PA0*, PD3
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RTS PA1, PD4*
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RX PA3, PD6
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TX PA2, PD5*
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USART3
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CK PB12, PC12*, PD10
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CTS PB13, PD11
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RTS PB14, PD12*
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RX PB11, PC11, PD9
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TX PB10*, PC10*, PD8
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UART4
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RX PA1, PC11
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TX PA0*, PC10*
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UART5
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RX PD2
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TX PC12*
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This can be found on the board at:
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* Indicates pins that have other on-board functions and should be used only
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with care (See table 5 in the STM32F3Discovery User Guide). The rest are
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free I/O pins.
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Default USART/UART Configuration
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--------------------------------
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USART2 is enabled in all configurations (see */defconfig). RX and TX are
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configured on pins PA3 and PA2, respectively (see include/board.h).
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Timer Inputs/Outputs
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====================
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TIM1
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CH1 PA8, PE9
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CH2 PA9*, PE11
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CH3 PA10*, PE13
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CH4 PA11*, PE14
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TIM2
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CH1 PA0*, PA15, PA5*
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CH2 PA1, PB3*
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CH3 PA2, PB10*
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CH4 PA3, PB11
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TIM3
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CH1 PA6*, PB4, PC6
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CH2 PA7*, PB5, PC7*
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CH3 PB0, PC8
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CH4 PB1, PC9
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TIM4
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CH1 PB6*, PD12*
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CH2 PB7, PD13*
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CH3 PB8, PD14*
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CH4 PB9*, PD15*
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TIM5
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CH1 PA0*, PH10**
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CH2 PA1, PH11**
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CH3 PA2, PH12**
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CH4 PA3, PI0
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TIM8
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CH1 PC6, PI5
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CH2 PC7*, PI6
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CH3 PC8, PI7
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CH4 PC9, PI2
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* Indicates pins that have other on-board functions and should be used only
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with care (See table 5 in the STM32F3Discovery User Guide). The rest are
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free I/O pins.
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** Port H pins are not supported by the MCU
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Quadrature Encode Timer Inputs
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------------------------------
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If enabled (by setting CONFIG_QENCODER=y), then quadrature encoder will
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use either TIM2 or TIM8 (see nsh/defconfig). If TIM2 is selected, the input
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pins PA15 and PA1 for CH1 and CH2, respectively). If TIM8 is selected, then
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PC6 and PI5 will be used for CH1 and CH2 (see include board.h for pin
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definitions).
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TX, PA2, Connector P1, pin 14
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RX, PA3, Connector P1, pin 9
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FPU
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===
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@ -495,6 +417,36 @@ See the section above on Toolchains, NOTE 2, for explanations for some of
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the configuration settings. Some of the usual settings are just not supported
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by the "Lite" version of the Atollic toolchain.
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Debugging
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=========
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STM32 ST-LINK Utility
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---------------------
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For simply writing to FLASH, I use the STM32 ST-LINK Utility. At least
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version 2.4.0 is required (older versions do not recognize the STM32 F3
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device). This utility is available from free from the STMicro website.
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Debugging
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---------
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If you are going to use a debugger, you should make sure that the following
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settings are selection in your configuration file:
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CONFIG_DEBUG_SYMBOLS=y : Enable debug symbols in the build
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CONFIG_ARMV7M_USEBASEPRI=y : Use the BASEPRI register to disable interrupts
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OpenOCD
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-------
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I am told that OpenOCD will work with the ST-Link, but I have never tried
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it.
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https://github.com/texane/stlink
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--------------------------------
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This is an open source server for the ST-Link that I have never used.
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Atollic GDB Server
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------------------
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You can use the Atollic IDE, but I have never done that either.
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STM32F3Discovery-specific Configuration Options
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===============================================
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@ -746,7 +698,9 @@ Where <subdir> is one of the following:
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2. Default toolchain:
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CONFIG_STM32_CODESOURCERYL=y : CodeSourcery under Linux / Mac OS X
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CONFIG_HOST_WINDOWS=y : Builds under Windows
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CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
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CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
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3. By default, this project assumes that you are *NOT* using the DFU
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bootloader.
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@ -805,35 +759,15 @@ Where <subdir> is one of the following:
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CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
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CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
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3. This example supports the PWM test (apps/examples/pwm) but this must
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be manually enabled by selecting:
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3. This configuration includes USB Support (CDC/ACM device)
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CONFIG_PWM=y : Enable the generic PWM infrastructure
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CONFIG_STM32_TIM4=y : Enable TIM4
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CONFIG_STM32_TIM4_PWM=y : Use TIM4 to generate PWM output
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CONFIG_STM32_USB=y : STM32 USB device support
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CONFIG_USBDEV=y : USB device support must be enabled
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CONFIG_CDCACM=y : The CDC/ACM driver must be built
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CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled
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CONFIG_NSH_ARCHINIT=y : To perform USB initialization
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See also apps/examples/README.txt
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Special PWM-only debug options:
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CONFIG_DEBUG_PWM
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5. This example supports the Quadrature Encode test (apps/examples/qencoder)
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but this must be manually enabled by selecting:
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CONFIG_EXAMPLES_QENCODER=y : Enable the apps/examples/qencoder
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CONFIG_SENSORS=y : Enable support for sensors
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CONFIG_QENCODER=y : Enable the generic Quadrature Encoder infrastructure
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CONFIG_STM32_TIM8=y : Enable TIM8
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CONFIG_STM32_TIM2=n : (Or optionally TIM2)
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CONFIG_STM32_TIM8_QE=y : Use TIM8 as the quadrature encoder
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CONFIG_STM32_TIM2_QE=y : (Or optionally TIM2)
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See also apps/examples/README.tx. Special PWM-only debug options:
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CONFIG_DEBUG_QENCODER
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6. This example supports the watchdog timer test (apps/examples/watchdog)
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4. This example supports the watchdog timer test (apps/examples/watchdog)
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but this must be manually enabled by selecting:
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CONFIG_EXAMPLES_WATCHDOG=y : Enable the apps/examples/watchdog
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@ -850,21 +784,13 @@ Where <subdir> is one of the following:
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The IWDG timer has a range of about 35 seconds and should not be an issue.
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7. USB Support (CDC/ACM device)
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CONFIG_STM32_OTGFS=y : STM32 OTG FS support
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CONFIG_USBDEV=y : USB device support must be enabled
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CONFIG_CDCACM=y : The CDC/ACM driver must be built
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CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled
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CONFIG_NSH_ARCHINIT=y : To perform USB initialization
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8. Using the USB console.
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5. Using the USB console.
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The STM32F3Discovery NSH configuration can be set up to use a USB CDC/ACM
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(or PL2303) USB console. The normal way that you would configure the
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the USB console would be to change the .config file like this:
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CONFIG_STM32_OTGFS=y : STM32 OTG FS support
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CONFIG_STM32_USB=y : STM32 OTG FS support
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CONFIG_USART2_SERIAL_CONSOLE=n : Disable the USART2 console
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CONFIG_DEV_CONSOLE=n : Inhibit use of /dev/console by other logic
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CONFIG_USBDEV=y : USB device support must be enabled
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@ -875,12 +801,12 @@ Where <subdir> is one of the following:
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times before NSH starts. The logic does this to prevent sending USB data
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before there is anything on the host side listening for USB serial input.
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9. Here is an alternative USB console configuration. The following
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6. Here is an alternative USB console configuration. The following
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configuration will also create a NSH USB console but this version
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will use /dev/console. Instead, it will use the normal /dev/ttyACM0
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USB serial device for the console:
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CONFIG_STM32_OTGFS=y : STM32 OTG FS support
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CONFIG_STM32_USB=y : STM32 OTG FS support
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CONFIG_USART2_SERIAL_CONSOLE=y : Keep the USART2 console
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CONFIG_DEV_CONSOLE=y : /dev/console exists (but NSH won't use it)
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CONFIG_USBDEV=y : USB device support must be enabled
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@ -914,65 +840,6 @@ Where <subdir> is one of the following:
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See the usbnsh configuration below for more information on configuring
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USB trace output and the USB monitor.
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10. USB OTG FS Host Support. The following changes will enable support for
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a USB host on the STM32F3Discovery, including support for a mass storage
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class driver:
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CONFIG_USBDEV=n : Make sure tht USB device support is disabled
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CONFIG_USBHOST=y : Enable USB host support
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CONFIG_STM32_OTGFS=y : Enable the STM32 USB OTG FS block
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CONFIG_STM32_SYSCFG=y : Needed for all USB OTF FS support
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CONFIG_SCHED_WORKQUEUE=y : Worker thread support is required for the mass
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storage class driver.
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CONFIG_NSH_ARCHINIT=y : Architecture specific USB initialization
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is needed for NSH
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CONFIG_FS_FAT=y : Needed by the USB host mass storage class.
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With those changes, you can use NSH with a FLASH pen driver as shown
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belong. Here NSH is started with nothing in the USB host slot:
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NuttShell (NSH) NuttX-x.yy
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nsh> ls /dev
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/dev:
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console
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null
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ttyS0
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After inserting the FLASH drive, the /dev/sda appears and can be
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mounted like this:
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nsh> ls /dev
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/dev:
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console
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null
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sda
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ttyS0
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nsh> mount -t vfat /dev/sda /mnt/stuff
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nsh> ls /mnt/stuff
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/mnt/stuff:
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-rw-rw-rw- 16236 filea.c
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And files on the FLASH can be manipulated to standard interfaces:
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nsh> echo "This is a test" >/mnt/stuff/atest.txt
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nsh> ls /mnt/stuff
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/mnt/stuff:
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-rw-rw-rw- 16236 filea.c
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-rw-rw-rw- 16 atest.txt
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nsh> cat /mnt/stuff/atest.txt
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This is a test
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nsh> cp /mnt/stuff/filea.c fileb.c
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nsh> ls /mnt/stuff
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/mnt/stuff:
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-rw-rw-rw- 16236 filea.c
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-rw-rw-rw- 16 atest.txt
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-rw-rw-rw- 16236 fileb.c
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To prevent data loss, don't forget to un-mount the FLASH drive
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before removing it:
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nsh> umount /mnt/stuff
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usbnsh:
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-------
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@ -246,31 +246,15 @@
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* (See the README.txt file for other options)
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_1
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#define GPIO_USART2_TX GPIO_USART2_TX_1
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#define GPIO_USART2_RX GPIO_USART2_RX_2
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#define GPIO_USART2_TX GPIO_USART2_TX_2
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/* PWM
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*
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* The STM32F3Discovery has no real on-board PWM devices, but the board can be
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* configured to output a pulse train using TIM4 CH2 on PD13.
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*/
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#define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2
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/* SPI - There is a MEMS device on SPI1 using these pins: */
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/* SPI - There is a ST MEMS L3GD20 device on SPI1 using these pins: */
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* Timer Inputs/Outputs (see the README.txt file for options) */
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#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_2
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#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_1
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#define GPIO_TIM8_CH1IN GPIO_TIM8_CH1IN_1
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#define GPIO_TIM8_CH2IN GPIO_TIM8_CH2IN_1
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/************************************************************************************
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* Public Data
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************************************************************************************/
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@ -118,68 +118,12 @@
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#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
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/* PWM
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*
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* The STM32F3Discovery has no real on-board PWM devices, but the board can be
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* configured to output a pulse train using TIM4 CH2 on PD13.
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*/
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/* SPI - There is a ST MEMS L3GD20 device on SPI1 using these pins: */
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#define STM32F3DISCOVERY_PWMTIMER 4
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#define STM32F3DISCOVERY_PWMCHANNEL 2
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/* SPI chip selects */
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#define GPIO_CS_MEMS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
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#define GPIO_MEMS_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
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GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
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/* USB OTG FS
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*
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* PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED)
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* PC0 OTG_FS_PowerSwitchOn
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* PD5 OTG_FS_Overcurrent
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*/
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|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0)
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
|
||||
|
||||
#else
|
||||
# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
|
||||
#endif
|
||||
|
||||
/* UG-2864AMBAG01 or UG-2864HSWEG01 OLED Display (SPI 4-wire):
|
||||
*
|
||||
* --------------------------+----------------------------------------------
|
||||
* Connector CON10 J1: | STM32F3Discovery
|
||||
* --------------+-----------+----------------------------------------------
|
||||
* CON10 J1: | CON20 J2: | P1/P2:
|
||||
* --------------+-----------+----------------------------------------------
|
||||
* 1 3v3 | 3,4 3v3 | P2 3V
|
||||
* 3 /RESET | 8 /RESET | P2 PB6 (Arbitrary selection)
|
||||
* 5 /CS | 7 /CS | P2 PB7 (Arbitrary selection)
|
||||
* 7 A0|D/C | 9 A0|D/C | P2 PB8 (Arbitrary selection)
|
||||
* 9 LED+ (N/C) | ----- | -----
|
||||
* 2 5V Vcc | 1,2 Vcc | P2 5V
|
||||
* 4 DI | 18 D1/SI | P1 PA7 (GPIO_SPI1_MOSI == GPIO_SPI1_MOSI_1 (1))
|
||||
* 6 SCLK | 19 D0/SCL | P1 PA5 (GPIO_SPI1_SCK == GPIO_SPI1_SCK_1 (1))
|
||||
* 8 LED- (N/C) | ----- | ------
|
||||
* 10 GND | 20 GND | P2 GND
|
||||
* --------------+-----------+----------------------------------------------
|
||||
* (1) Required because of on-board MEMS
|
||||
* -------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
# define GPIO_OLED_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
|
||||
# define GPIO_OLED_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7)
|
||||
# define GPIO_OLED_A0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
|
||||
# define GPIO_OLED_DC GPIO_OLED_A0
|
||||
#endif
|
||||
#define GPIO_MEMS_INT1 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_MEMS_INT2 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN1)
|
||||
|
||||
/****************************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@ -96,16 +96,9 @@
|
||||
void weak_function stm32_spiinitialize(void)
|
||||
{
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
(void)stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */
|
||||
#endif
|
||||
#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
(void)stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */
|
||||
# if defined(CONFIG_LCD_UG2864AMBAG01)
|
||||
(void)stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */
|
||||
# endif
|
||||
# if defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
(void)stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */
|
||||
# endif
|
||||
(void)stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */
|
||||
(void)stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */
|
||||
(void)stm32_configgpio(GPIO_MEMS_INT2);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -139,16 +132,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool sele
|
||||
{
|
||||
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
|
||||
|
||||
#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
if (devid == SPIDEV_DISPLAY)
|
||||
{
|
||||
stm32_gpiowrite(GPIO_OLED_CS, !selected);
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
stm32_gpiowrite(GPIO_CS_MEMS, !selected);
|
||||
}
|
||||
stm32_gpiowrite(GPIO_MEMS_CS, !selected);
|
||||
}
|
||||
|
||||
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
@ -208,27 +192,6 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
|
||||
{
|
||||
#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
if (devid == SPIDEV_DISPLAY)
|
||||
{
|
||||
/* "This is the Data/Command control pad which determines whether the
|
||||
* data bits are data or a command.
|
||||
*
|
||||
* A0 = "H": the inputs at D0 to D7 are treated as display data.
|
||||
* A0 = "L": the inputs at D0 to D7 are transferred to the command
|
||||
* registers."
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_LCD_UG2864AMBAG01)
|
||||
(void)stm32_gpiowrite(GPIO_OLED_A0, !cmd);
|
||||
# endif
|
||||
# if defined(CONFIG_LCD_UG2864HSWEG01)
|
||||
(void)stm32_gpiowrite(GPIO_OLED_DC, !cmd);
|
||||
# endif
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user