diff --git a/arch/arm/src/kinetis/chip/kinetis_flexcan.h b/arch/arm/src/kinetis/chip/kinetis_flexcan.h index 9d3ec74a38..2463eb6b71 100644 --- a/arch/arm/src/kinetis/chip/kinetis_flexcan.h +++ b/arch/arm/src/kinetis/chip/kinetis_flexcan.h @@ -280,17 +280,17 @@ #define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */ #define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ /* Bit 15: Reserved */ -#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ #define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */ #define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT) /* Bits 23-31: Reserved */ /* CRC Register */ - /* Bits 23-31: Reserved */ -#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */ -#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT) - /* Bit 15: Reserved */ + #define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */ #define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT) + /* Bit 15: Reserved */ +#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */ +#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT) + /* Bits 23-31: Reserved */ /* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */ diff --git a/arch/arm/src/kinetis/chip/kinetis_pit.h b/arch/arm/src/kinetis/chip/kinetis_pit.h index 26cd6caea6..5ccd110a36 100644 --- a/arch/arm/src/kinetis/chip/kinetis_pit.h +++ b/arch/arm/src/kinetis/chip/kinetis_pit.h @@ -48,45 +48,58 @@ * Pre-processor Definitions ************************************************************************************/ +#if defined(KINETIS_K66) +# define KINETIS_PIT_HAS_CHAIN +# define KINETIS_PIT_HAS_LIFETIME +#endif + /* Register Offsets *****************************************************************/ -#define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ -#define KINETIS_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */ -#define KINETIS_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */ -#define KINETIS_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */ -#define KINETIS_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */ -#define KINETIS_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */ -#define KINETIS_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */ -#define KINETIS_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */ -#define KINETIS_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */ -#define KINETIS_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */ -#define KINETIS_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */ -#define KINETIS_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */ -#define KINETIS_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */ -#define KINETIS_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */ -#define KINETIS_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */ -#define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ -#define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ +#define KINETIS_PIT_MCR_OFFSET 0x0000 /* PIT Module Control Register */ +#if defined(KINETIS_PIT_HAS_LIFETIME) +# define KINETIS_PIT_LTMR64H_OFFSET 0x00e0 /* PIT Upper Lifetime Timer Register */ +# define KINETIS_PIT_LTMR64L_OFFSET 0x00e4 /* PIT Lower Lifetime Timer Register */ +#endif +#define KINETIS_PIT_LDVAL0_OFFSET 0x0100 /* Timer Load Value Register */ +#define KINETIS_PIT_CVAL0_OFFSET 0x0104 /* Current Timer Value Register */ +#define KINETIS_PIT_TCTRL0_OFFSET 0x0108 /* Timer Control Register */ +#define KINETIS_PIT_TFLG0_OFFSET 0x010c /* Timer Flag Register */ +#define KINETIS_PIT_LDVAL1_OFFSET 0x0110 /* Timer Load Value Register */ +#define KINETIS_PIT_CVAL1_OFFSET 0x0114 /* Current Timer Value Register */ +#define KINETIS_PIT_TCTRL1_OFFSET 0x0118 /* Timer Control Register */ +#define KINETIS_PIT_TFLG1_OFFSET 0x011c /* Timer Flag Register */ +#define KINETIS_PIT_LDVAL2_OFFSET 0x0120 /* Timer Load Value Register */ +#define KINETIS_PIT_CVAL2_OFFSET 0x0124 /* Current Timer Value Register */ +#define KINETIS_PIT_TCTRL2_OFFSET 0x0128 /* Timer Control Register */ +#define KINETIS_PIT_TFLG2_OFFSET 0x012c /* Timer Flag Register */ +#define KINETIS_PIT_LDVAL3_OFFSET 0x0130 /* Timer Load Value Register */ +#define KINETIS_PIT_CVAL3_OFFSET 0x0134 /* Current Timer Value Register */ +#define KINETIS_PIT_TCTRL3_OFFSET 0x0138 /* Timer Control Register */ +#define KINETIS_PIT_TFLG3_OFFSET 0x013c /* Timer Flag Register */ /* Register Addresses ***************************************************************/ -#define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET) -#define KINETIS_PIT_LDVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL0_OFFSET) -#define KINETIS_PIT_CVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL0_OFFSET) -#define KINETIS_PIT_TCTRL0 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL0_OFFSET) -#define KINETIS_PIT_TFLG0 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG0_OFFSET) -#define KINETIS_PIT_LDVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL1_OFFSET) -#define KINETIS_PIT_CVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL1_OFFSET) -#define KINETIS_PIT_TCTRL1 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL1_OFFSET) -#define KINETIS_PIT_TFLG1 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG1_OFFSET) -#define KINETIS_PIT_LDVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL2_OFFSET) -#define KINETIS_PIT_CVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL2_OFFSET) -#define KINETIS_PIT_TCTRL2 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL2_OFFSET) -#define KINETIS_PIT_TFLG2 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG2_OFFSET) -#define KINETIS_PIT_LDVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL3_OFFSET) -#define KINETIS_PIT_CVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL3_OFFSET) -#define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET) -#define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET) +#define KINETIS_PIT_MCR (KINETIS_PIT_BASE+KINETIS_PIT_MCR_OFFSET) +#if defined(KINETIS_PIT_HAS_LIFETIME) +# define KINETIS_PIT_LTMR64H (KINETIS_PIT_BASE+KINETIS_PIT_LTMR64H_OFFSET) +# define KINETIS_PIT_LTMR64L (KINETIS_PIT_BASE+KINETIS_PIT_LTMR64L_OFFSET) +#endif +#define KINETIS_PIT_LDVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL0_OFFSET) +#define KINETIS_PIT_CVAL0 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL0_OFFSET) +#define KINETIS_PIT_TCTRL0 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL0_OFFSET) +#define KINETIS_PIT_TFLG0 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG0_OFFSET) +#define KINETIS_PIT_LDVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL1_OFFSET) +#define KINETIS_PIT_CVAL1 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL1_OFFSET) +#define KINETIS_PIT_TCTRL1 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL1_OFFSET) +#define KINETIS_PIT_TFLG1 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG1_OFFSET) +#define KINETIS_PIT_LDVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL2_OFFSET) +#define KINETIS_PIT_CVAL2 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL2_OFFSET) +#define KINETIS_PIT_TCTRL2 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL2_OFFSET) +#define KINETIS_PIT_TFLG2 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG2_OFFSET) +#define KINETIS_PIT_LDVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_LDVAL3_OFFSET) +#define KINETIS_PIT_CVAL3 (KINETIS_PIT_BASE+KINETIS_PIT_CVAL3_OFFSET) +#define KINETIS_PIT_TCTRL3 (KINETIS_PIT_BASE+KINETIS_PIT_TCTRL3_OFFSET) +#define KINETIS_PIT_TFLG3 (KINETIS_PIT_BASE+KINETIS_PIT_TFLG3_OFFSET) /* Register Bit Definitions *********************************************************/ @@ -104,6 +117,10 @@ #define PIT_TCTRL_TEN (1 << 0) /* Bit 0: Timer Enable Bit */ #define PIT_TCTRL_TIE (1 << 1) /* Bit 1: Timer Interrupt Enable Bit */ /* Bits 2-31: Reserved */ +#if defined(KINETIS_PIT_HAS_CHAIN) +#define PIT_TCTRL_CHN (1 << 2) /* Bit 2: Chain Mode */ + /* Bits 3-31: Reserved */ +#endif /* Timer Flag Register */ #define PIT_TFLG_TIF (1 << 0) /* Bit 0: Timer Interrupt Flag */ diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index 98c9eb9ef8..a7667f3c9a 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -245,6 +245,8 @@ # if ((CONSOLE_FREQ / (CONSOLE_BAUD * 32)) > (LPUART_BAUD_SBR_MASK >> LPUART_BAUD_SBR_SHIFT)) # error "LPUART Console: Baud rate not obtainable with this input clock!" # endif +#endif +#ifdef HAVE_LPUART_DEVICE # define LPUART_BAUD_INIT (LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS | \ LPUART_BAUD_RXEDGIE | LPUART_BAUD_LBKDIE | \ LPUART_BAUD_RESYNCDIS |LPUART_BAUD_BOTHEDGE | \ @@ -933,7 +935,7 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, /* Check for 9-bit operation */ - if (nbits == 9) + if (nbits == 9 || (nbits == 8 && parity != 0)) { regval |= LPUART_CTRL_M; } diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index 1f61b0b72b..87ec692575 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -570,6 +570,7 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) * Name: kinetis_disableuartint ****************************************************************************/ +#if defined(HAVE_LPUART_PUTC) && defined(HAVE_LPUART_CONSOLE) static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) { irqstate_t flags; @@ -583,6 +584,7 @@ static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) kinetis_restoreuartint(priv, 0); leave_critical_section(flags); } +#endif /**************************************************************************** * Name: kinetis_setup diff --git a/arch/arm/src/kinetis/kinetis_pindma.c b/arch/arm/src/kinetis/kinetis_pindma.c index 411f371bbb..43ae05e877 100644 --- a/arch/arm/src/kinetis/kinetis_pindma.c +++ b/arch/arm/src/kinetis/kinetis_pindma.c @@ -47,14 +47,14 @@ #include #include +#include +#include "up_arch.h" #include "up_internal.h" #include "kinetis_config.h" #include "chip.h" #include "kinetis.h" - - #ifdef CONFIG_KINETIS_DMA /****************************************************************************