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arm64: Updating ARCH_EARLY_PRINT support

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Summary:
  Keeping this option out of depend on any common serial.
Using the option, need to implement xxx_lowputc.S/c.
  You can also logging the booting message through rewriting
fake arm64_lowputc with other debug method (eg semihosting,
ARM debug channel etc).

Signed-off-by: qinwei1 <qinwei1@xiaomi.com>
This commit is contained in:
qinwei1 2023-04-26 09:36:15 +08:00 committed by Xiang Xiao
parent bebddf3981
commit 2eac660ff6
17 changed files with 85 additions and 99 deletions
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11
arch/arm64/Kconfig
View File

@ -119,11 +119,14 @@ config ARCH_EARLY_PRINT
the NuttX should be execute at EL1 in NS(ARmv8-A) or S(ARmv8-R)
state. but booting NuttX have different ELs and state while with
different platform, if NuttX runing at wrong ELs or state it will
be not normal anymore. So we need to print something in arm64_head.S
not normal anymore. So we need to print something in arm64_head.S
to debug this situation.
Enabling this option will need to implement arm64_earlyserialinit and
arm64_lowputc functions just you see in qemu, if you not sure,
keeping the option disable.
Enabling this option will need to implement arm64_earlyprintinit and
arm64_lowputc functions just you see in qemu_lowputc.S.
by default, UART dev will be used. You can also logging the booting
message through rewriting fake arm64_lowputc with other debug
method (eg semihosting , ARM debug channel etc)
if you not sure, keeping the option disable.
config ARCH_CORTEX_A53
bool

2
arch/arm64/src/a64/Make.defs
View File

@ -39,4 +39,6 @@ ifeq ($(CONFIG_A64_TCON0),y)
CHIP_CSRCS += a64_tcon0.c
endif
ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
CHIP_ASRCS = a64_lowputc.S
endif

9
arch/arm64/src/a64/a64_lowputc.S
View File

@ -49,6 +49,15 @@
* Public Functions
****************************************************************************/
/* Initialize A64 UART
* xb: Register that contains the UART Base Address
* c: Scratch register number
*/
GTEXT(arm64_earlyprintinit)
SECTION_FUNC(text, arm64_earlyprintinit)
ret /* Do nothing because U-Boot has already initialized UART */
/* Wait for A64 UART to be ready to transmit
* xb: Register that contains the UART Base Address
* wt: Scratch register number

46
arch/arm64/src/a64/a64_serial.c
View File

@ -634,16 +634,20 @@ void arm64_earlyserialinit(void)
int up_putc(int ch)
{
#ifdef CONSOLE_DEV
struct uart_dev_s *dev = &CONSOLE_DEV;
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
a64_uart_send(dev, '\r');
}
arm64_lowputc((uint8_t)ch);
a64_uart_send(dev, ch);
#endif
return ch;
}
@ -661,6 +665,7 @@ int up_putc(int ch)
void arm64_serialinit(void)
{
#ifdef CONSOLE_DEV
int ret;
ret = uart_register("/dev/console", &CONSOLE_DEV);
@ -675,42 +680,7 @@ void arm64_serialinit(void)
{
sinfo("error at register dev/ttyS0, ret =%d\n", ret);
}
}
#else /* USE_SERIALDRIVER */
/***************************************************************************
* Public Functions
***************************************************************************/
/***************************************************************************
* Name: up_putc
*
* Description:
* Provide priority, low-level access to support OS debug
* writes
*
* Input Parameters:
* ch - Character to be transmitted over UART
*
* Returned Value:
* Character that was transmitted
*
***************************************************************************/
int up_putc(int ch)
{
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
}
arm64_lowputc((uint8_t)ch);
return ch;
#endif
}
#endif /* USE_SERIALDRIVER */

2
arch/arm64/src/common/arm64_head.S
View File

@ -193,7 +193,7 @@ primary_core:
* Should only be called on the boot CPU
*/
bl arm64_earlyserialinit
bl arm64_earlyprintinit
#endif
PRINT(primary_boot, "- Ready to Boot Primary CPU\r\n")

2
arch/arm64/src/common/arm64_internal.h
View File

@ -321,8 +321,6 @@ void arm64_serialinit(void);
void arm64_earlyserialinit(void);
#endif
void arm64_lowputc(char c);
/* DMA */
#ifdef CONFIG_ARCH_DMA

1
arch/arm64/src/fvp-v8r/Kconfig
View File

@ -15,7 +15,6 @@ config ARCH_CHIP_FVP_R82
bool "FVP virtual Processor (Cortex-r82)"
select ARCH_HAVE_MULTICPU
select ARMV8R_HAVE_GICv3
select ARCH_EARLY_PRINT
select ARCH_SET_VMPIDR_EL2
endchoice # FVP Chip Selection

5
arch/arm64/src/fvp-v8r/Make.defs
View File

@ -22,4 +22,7 @@ include common/Make.defs
# fvp-specific C source files
CHIP_CSRCS = fvp_boot.c serial_pl011.c
CHIP_ASRCS = fvp_lowputc.S
ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
CHIP_ASRCS += fvp_lowputc.S
endif

5
arch/arm64/src/fvp-v8r/fvp_boot.c
View File

@ -178,11 +178,6 @@ void arm64_chip_boot(void)
{
/* MAP IO and DRAM, enable MMU. */
uint64_t cpumpid;
cpumpid = read_sysreg(mpidr_el1);
sinfo("Main CPU 0x%-16"PRIx64"", cpumpid);
arm64_mpu_init(true);
#if defined(CONFIG_SMP) && defined(CONFIG_ARCH_HAVE_PCSI)

22
arch/arm64/src/fvp-v8r/fvp_lowputc.S
View File

@ -50,6 +50,28 @@
* Public Functions
****************************************************************************/
/***************************************************************************
* Name: arm64_earlyprintinit
*
* PL011 UART initialization
* xb: register which contains the UART base address
* c: scratch register number
*
***************************************************************************/
GTEXT(arm64_earlyprintinit)
SECTION_FUNC(text, arm64_earlyprintinit)
ldr x15, =CONFIG_UART0_BASE
mov x0, #(7372800 / EARLY_UART_PL011_BAUD_RATE % 16)
strh w0, [x15, #0x28] /* -> UARTFBRD (Baud divisor fraction) */
mov x0, #(7372800 / EARLY_UART_PL011_BAUD_RATE / 16)
strh w0, [x15, #0x24] /* -> UARTIBRD (Baud divisor integer) */
mov x0, #0x60 /* 8n1 */
str w0, [x15, #0x2C] /* -> UARTLCR_H (Line control) */
ldr x0, =0x00000301 /* RXE | TXE | UARTEN */
str w0, [x15, #0x30] /* -> UARTCR (Control Register) */
ret
/* PL011 UART wait UART to be ready to transmit
* xb: register which contains the UART base address
* c: scratch register number

32
arch/arm64/src/fvp-v8r/serial_pl011.c
View File

@ -810,16 +810,21 @@ void arm64_earlyserialinit(void)
int up_putc(int ch)
{
#ifdef CONSOLE_DEV
struct uart_dev_s *dev = &CONSOLE_DEV;
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
pl011_send(dev, '\r');
}
arm64_lowputc((uint8_t)ch);
pl011_send(dev, ch);
#endif
return ch;
}
@ -833,6 +838,7 @@ int up_putc(int ch)
void arm64_serialinit(void)
{
#ifdef CONSOLE_DEV
int ret;
ret = uart_register("/dev/console", &CONSOLE_DEV);
@ -847,27 +853,7 @@ void arm64_serialinit(void)
{
sinfo("error at register dev/ttyS0, ret =%d\n", ret);
}
}
#else /* USE_SERIALDRIVER */
/***************************************************************************
* Public Functions
***************************************************************************/
int up_putc(int ch)
{
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
}
arm64_lowputc((uint8_t)ch);
return ch;
#endif
}
#endif /* USE_SERIALDRIVER */

2
arch/arm64/src/qemu/Make.defs
View File

@ -23,7 +23,9 @@ include common/Make.defs
# qemu-specific C source files
CHIP_CSRCS = qemu_boot.c qemu_serial.c
ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
CHIP_ASRCS = qemu_lowputc.S
endif
ifeq ($(CONFIG_DRIVERS_VIRTIO_NET),y)
CHIP_CSRCS += qemu_virtio.c

10
arch/arm64/src/qemu/qemu_lowputc.S
View File

@ -50,6 +50,16 @@
* Public Functions
****************************************************************************/
/* PL011 UART initialization
*/
GTEXT(arm64_earlyprintinit)
SECTION_FUNC(text, arm64_earlyprintinit)
/* it's seem we can do nothing at the qemu platform
* for qemu pl011, the QEMU has already initialized UART
*/
ret
/* PL011 UART wait UART to be ready to transmit
* xb: register which contains the UART base address
* c: scratch register number

31
arch/arm64/src/qemu/qemu_serial.c
View File

@ -815,16 +815,20 @@ void arm64_earlyserialinit(void)
int up_putc(int ch)
{
#ifdef CONSOLE_DEV
struct uart_dev_s *dev = &CONSOLE_DEV;
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
qemu_pl011_send(dev, '\r');
}
arm64_lowputc((uint8_t)ch);
qemu_pl011_send(dev, ch);
#endif
return ch;
}
@ -838,6 +842,7 @@ int up_putc(int ch)
void arm64_serialinit(void)
{
#ifdef CONSOLE_DEV
int ret;
ret = uart_register("/dev/console", &CONSOLE_DEV);
@ -852,27 +857,7 @@ void arm64_serialinit(void)
{
sinfo("error at register dev/ttyS0, ret =%d\n", ret);
}
}
#else /* USE_SERIALDRIVER */
/***************************************************************************
* Public Functions
***************************************************************************/
int up_putc(int ch)
{
/* Check for LF */
if (ch == '\n')
{
/* Add CR */
arm64_lowputc('\r');
}
arm64_lowputc((uint8_t)ch);
return ch;
#endif
}
#endif /* USE_SERIALDRIVER */

1
boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh/defconfig
View File

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_FVP_ARMV8R=y
CONFIG_ARCH_CHIP="fvp-v8r"
CONFIG_ARCH_CHIP_FVP_ARMV8R=y
CONFIG_ARCH_CHIP_FVP_R82=y
CONFIG_ARCH_EARLY_PRINT=y
CONFIG_ARCH_INTERRUPTSTACK=4096
CONFIG_BUILTIN=y
CONFIG_DEBUG_ASSERTIONS=y

1
boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig
View File

@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_FVP_ARMV8R=y
CONFIG_ARCH_CHIP="fvp-v8r"
CONFIG_ARCH_CHIP_FVP_ARMV8R=y
CONFIG_ARCH_CHIP_FVP_R82=y
CONFIG_ARCH_EARLY_PRINT=y
CONFIG_ARCH_INTERRUPTSTACK=4096
CONFIG_BUILTIN=y
CONFIG_DEBUG_ASSERTIONS=y

2
boards/arm64/fvp-v8r/fvp-armv8r/scripts/fvp_cfg.txt
View File

@ -22,4 +22,4 @@ bp.pl011_uart3.unbuffered_output=1
bp.terminal_3.start_telnet=0
bp.vis.disable_visualisation=1
bp.vis.rate_limit-enable=0
cache_state_modelled=0
cache_state_modelled=1