diff --git a/configs/stm32f103-minimum/rfid-rc522/Make.defs b/configs/stm32f103-minimum/rfid-rc522/Make.defs new file mode 100644 index 0000000000..1daec534a5 --- /dev/null +++ b/configs/stm32f103-minimum/rfid-rc522/Make.defs @@ -0,0 +1,113 @@ +############################################################################ +# configs/stm32f103-minimum/rfid-rc522/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/stm32f103-minimum/rfid-rc522/defconfig b/configs/stm32f103-minimum/rfid-rc522/defconfig new file mode 100644 index 0000000000..788f32fbda --- /dev/null +++ b/configs/stm32f103-minimum/rfid-rc522/defconfig @@ -0,0 +1,1158 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +CONFIG_DEFAULT_SMALL=y +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +# CONFIG_INTELHEX_BINARY is not set +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +CONFIG_ARCH_CORTEXM3=y +# CONFIG_ARCH_CORTEXM4 is not set +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +# CONFIG_ARCH_HAVE_FPU is not set +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +CONFIG_SERIAL_TERMIOS=y + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +CONFIG_ARCH_CHIP_STM32F103C8=y +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +# CONFIG_ARCH_CHIP_STM32F407ZG is not set +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +CONFIG_STM32_STM32F10XX=y +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +CONFIG_STM32_PERFORMANCELINE=y +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +CONFIG_STM32_MEDIUMDENSITY=y +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +# CONFIG_STM32_STM32F40XX is not set +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +# CONFIG_STM32_STM32F407 is not set +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +# CONFIG_STM32_HAVE_CCM is not set +CONFIG_STM32_HAVE_USBDEV=y +# CONFIG_STM32_HAVE_OTGFS is not set +# CONFIG_STM32_HAVE_FSMC is not set +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +# CONFIG_STM32_HAVE_USART6 is not set +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +# CONFIG_STM32_HAVE_TIM2 is not set +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +# CONFIG_STM32_HAVE_TIM9 is not set +# CONFIG_STM32_HAVE_TIM10 is not set +# CONFIG_STM32_HAVE_TIM11 is not set +# CONFIG_STM32_HAVE_TIM12 is not set +# CONFIG_STM32_HAVE_TIM13 is not set +# CONFIG_STM32_HAVE_TIM14 is not set +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +# CONFIG_STM32_HAVE_CAN2 is not set +# CONFIG_STM32_HAVE_DAC1 is not set +# CONFIG_STM32_HAVE_DAC2 is not set +# CONFIG_STM32_HAVE_RNG is not set +# CONFIG_STM32_HAVE_ETHMAC is not set +CONFIG_STM32_HAVE_I2C2=y +# CONFIG_STM32_HAVE_I2C3 is not set +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKP is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_PWR is not set +# CONFIG_STM32_SDIO is not set +CONFIG_STM32_SPI1=y +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +CONFIG_STM32_USART1=y +# CONFIG_STM32_USART2 is not set +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USB is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +CONFIG_STM32_SPI=y +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_SPI1_REMAP is not set +# CONFIG_STM32_USART1_REMAP is not set +# CONFIG_STM32_JTAG_DISABLE is not set +CONFIG_STM32_JTAG_FULL_ENABLE=y +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +# CONFIG_STM32_JTAG_SW_ENABLE is not set +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set + +# +# Timer Configuration +# +# CONFIG_STM32_ONESHOT is not set +# CONFIG_STM32_FREERUN is not set +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART1_SERIALDRIVER=y +# CONFIG_STM32_USART1_1WIREDRIVER is not set +# CONFIG_USART1_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set + +# +# SPI Configuration +# +# CONFIG_STM32_SPI_INTERRUPTS is not set +# CONFIG_STM32_SPI_DMA is not set +CONFIG_STM32_HAVE_RTC_COUNTER=y +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=5483 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=20480 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_STM32_TINY is not set +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="stm32f103-minimum" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +# CONFIG_DISABLE_OS_API is not set + +# +# Clocks and Timers +# +CONFIG_ARCH_HAVE_TICKLESS=y +# CONFIG_SCHED_TICKLESS is not set +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +CONFIG_ARCH_HAVE_TIMEKEEPING=y +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2011 +CONFIG_START_MONTH=7 +CONFIG_START_DAY=5 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set +# CONFIG_SIG_EVTHREAD is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 +CONFIG_SIG_SIGWORK=17 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKPERIOD=50000 +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +# CONFIG_DISABLE_POLL is not set +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_URANDOM is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_SPI_CS_CONTROL is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +CONFIG_USART1_SERIALDRIVER=y +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +CONFIG_SERIAL_NPOLLWAITERS=2 +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +CONFIG_USART1_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# USART1 Configuration +# +CONFIG_USART1_RXBUFSIZE=256 +CONFIG_USART1_TXBUFSIZE=256 +CONFIG_USART1_BAUD=115200 +CONFIG_USART1_BITS=8 +CONFIG_USART1_PARITY=0 +CONFIG_USART1_2STOP=0 +# CONFIG_USART1_IFLOWCONTROL is not set +# CONFIG_USART1_OFLOWCONTROL is not set +# CONFIG_USART1_DMA is not set +# CONFIG_PSEUDOTERM is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +CONFIG_DRIVERS_WIRELESS=y +# CONFIG_WL_CC1101 is not set +# CONFIG_WL_CC3000 is not set +# CONFIG_WL_NRF24L01 is not set +CONFIG_WL_MFRC522=y +CONFIG_MFRC522_SPI_FREQ=1000000 +CONFIG_MFRC522_DEBUG=y +# CONFIG_MFRC522_DEBUG_TX is not set +# CONFIG_MFRC522_DEBUG_RX is not set +# CONFIG_WL_PN532 is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +# CONFIG_SYSLOG_CHARDEV is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +# CONFIG_FS_READABLE is not set +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +CONFIG_SYMTAB_ORDEREDBYNAME=y + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +CONFIG_EXAMPLES_RFID_READUID=y +CONFIG_EXAMPLES_RFID_READUID_PRIORITY=100 +CONFIG_EXAMPLES_RFID_READUID_STACKSIZE=2048 +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CHAT is not set +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=80 +CONFIG_NSH_DISABLE_SEMICOLON=y +# CONFIG_NSH_CMDPARMS is not set +CONFIG_NSH_MAXARGUMENTS=6 +# CONFIG_NSH_ARGCAT is not set +CONFIG_NSH_NESTDEPTH=3 +CONFIG_NSH_DISABLEBG=y +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +CONFIG_NSH_DISABLE_ADDROUTE=y +CONFIG_NSH_DISABLE_BASENAME=y +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DELROUTE=y +CONFIG_NSH_DISABLE_DIRNAME=y +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +CONFIG_NSH_DISABLE_TIME=y +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +CONFIG_NSH_DISABLE_UNAME=y +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CODECS_BUFSIZE=128 +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_FILEIOSIZE=1024 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +CONFIG_NSH_DISABLE_ITEF=y +CONFIG_NSH_DISABLE_LOOPS=y + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/rfid-rc522/setenv.sh b/configs/stm32f103-minimum/rfid-rc522/setenv.sh new file mode 100644 index 0000000000..a6e5649389 --- /dev/null +++ b/configs/stm32f103-minimum/rfid-rc522/setenv.sh @@ -0,0 +1,100 @@ +#!/bin/bash +# configs//stm32f103-minimum/rfid-rc522/setenv.sh +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# This is the path to the location where I installed the devkitARM toolchain +# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/stm32f103-minimum/src/Makefile b/configs/stm32f103-minimum/src/Makefile index b29ce80908..5056bd50c1 100644 --- a/configs/stm32f103-minimum/src/Makefile +++ b/configs/stm32f103-minimum/src/Makefile @@ -43,4 +43,8 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_WL_MFRC522),y) +CSRCS += stm32_mfrc522.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f103-minimum/src/stm32_appinit.c b/configs/stm32f103-minimum/src/stm32_appinit.c index d9291f9a16..78b7ac3ebf 100644 --- a/configs/stm32f103-minimum/src/stm32_appinit.c +++ b/configs/stm32f103-minimum/src/stm32_appinit.c @@ -80,5 +80,11 @@ int board_app_initialize(uintptr_t arg) { - return OK; + int ret = OK; + +#ifdef CONFIG_WL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); +#endif + + return ret; } diff --git a/configs/stm32f103-minimum/src/stm32_mfrc522.c b/configs/stm32f103-minimum/src/stm32_mfrc522.c new file mode 100644 index 0000000000..b3bc776ef7 --- /dev/null +++ b/configs/stm32f103-minimum/src/stm32_mfrc522.c @@ -0,0 +1,101 @@ +/************************************************************************************ + * configs/stm32f4discovery/src/stm32_mfrc522.c + * + * Copyright (C) 2015 Alan Carvalho de Assis. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && defined(CONFIG_WL_MFRC522) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define MFRC522_SPI_PORTNO 1 /* On SPI1 */ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_mfrc522initialize + * + * Description: + * Initialize and register the MFRC522 RFID driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ************************************************************************************/ + +int stm32_mfrc522initialize(FAR const char *devpath) +{ + FAR struct spi_dev_s *spi; + int ret; + + spi = stm32_spibus_initialize(MFRC522_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Then register the MFRC522 */ + + ret = mfrc522_register(devpath, spi); + if (ret < 0) + { + snerr("ERROR: Error registering MFRC522\n"); + } + + return ret; +} + +#endif /* CONFIG_SPI && CONFIG_MFRC522 */ diff --git a/configs/stm32f103-minimum/src/stm32_spi.c b/configs/stm32f103-minimum/src/stm32_spi.c index a1c8dbaadb..4b911f0346 100644 --- a/configs/stm32f103-minimum/src/stm32_spi.c +++ b/configs/stm32f103-minimum/src/stm32_spi.c @@ -73,6 +73,10 @@ void stm32_spidev_initialize(void) * Here, we only initialize chip select pins unique to the board * architecture. */ + +#ifdef CONFIG_WL_MFRC522 + (void)stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif } /**************************************************************************** @@ -103,6 +107,12 @@ void stm32_spidev_initialize(void) #ifdef CONFIG_STM32_SPI1 void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) { +#if defined(CONFIG_WL_MFRC522) + if (devid == SPIDEV_WIRELESS) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h index 47691a195c..873734de89 100644 --- a/configs/stm32f103-minimum/src/stm32f103_minimum.h +++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h @@ -66,6 +66,11 @@ #define GPIO_LED (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13) +/* SPI chip selects */ + +#define GPIO_CS_MFRC522 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) + /* USB Soft Connect Pullup: PC.13 */ #define GPIO_USB_PULLUP (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ @@ -97,6 +102,18 @@ void stm32_spidev_initialize(void); void stm32_usbinitialize(void); +/************************************************************************************ + * Name: stm32_mfrc522initialize + * + * Description: + * Function used to initialize the MFRC522 RFID Transceiver + * + ************************************************************************************/ + +#ifdef CONFIG_WL_MFRC522 +int stm32_mfrc522initialize(FAR const char *devpath); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F103_MINIMUM_SRC_STM32F103_MINIMUM_H */ diff --git a/drivers/pipes/Kconfig b/drivers/pipes/Kconfig index 760f9384dd..ace6ca8458 100644 --- a/drivers/pipes/Kconfig +++ b/drivers/pipes/Kconfig @@ -5,20 +5,23 @@ config DEV_PIPE_MAXSIZE int "Maximum pipe/FIFO size" - default 1024 + default 1024 if !DEFAULT_SMALL + default 256 if DEFAULT_SMALL ---help--- Maximum configurable size of a pipe or FIFO at runtime. config DEV_PIPE_SIZE int "Default pipe size" - default 1024 + default 1024 if !DEFAULT_SMALL + default 256 if DEFAULT_SMALL ---help--- Sets the default size of the pipe ringbuffer in bytes. A value of zero disables pipe support. config DEV_FIFO_SIZE int "Default FIFO size" - default 1024 + default 1024 if !DEFAULT_SMALL + default 256 if DEFAULT_SMALL ---help--- Sets the default size of the FIFO ringbuffer in bytes. A value of zero disables FIFO support. diff --git a/drivers/spi/spi_driver.c b/drivers/spi/spi_driver.c index bbbfb46e68..5f14827c03 100644 --- a/drivers/spi/spi_driver.c +++ b/drivers/spi/spi_driver.c @@ -402,7 +402,7 @@ int spi_register(FAR struct spi_dev_s *spi, int bus) /* Return the result of the registration */ - return OK; + return ret; } return -ENOMEM; diff --git a/drivers/spi/spi_transfer.c b/drivers/spi/spi_transfer.c index 74e312e3fe..5746e4c8aa 100644 --- a/drivers/spi/spi_transfer.c +++ b/drivers/spi/spi_transfer.c @@ -99,7 +99,9 @@ int spi_transfer(FAR struct spi_dev_s *spi, FAR struct spi_sequence_s *seq) SPI_SETMODE(spi, seq->mode); SPI_SETBITS(spi, seq->nbits); - /* Select the SPI device in preparation for the transfer */ + /* Select the SPI device in preparation for the transfer. + * REVISIT: This is redundant. + */ SPI_SELECT(spi, seq->dev, true); diff --git a/drivers/wireless/Kconfig b/drivers/wireless/Kconfig index e978ef6e82..42eda1941c 100644 --- a/drivers/wireless/Kconfig +++ b/drivers/wireless/Kconfig @@ -73,6 +73,37 @@ config WL_NRF24L01_RXFIFO_LEN endif # WL_NRF24L01_RXSUPPORT endif # WL_NRF24L01 +config WL_MFRC522 + bool "NXP MFRC522 ISO14443/Mifare Transceiver" + default n + select SPI + ---help--- + This options adds driver support for the MFRC522 ISO14443/Mifare chip. + +if WL_MFRC522 + +config MFRC522_SPI_FREQ + int "SPI frequency for MFRC522" + default 1000000 + depends on WL_MFRC522 + +config MFRC522_DEBUG + bool "Enable MFRC522 debug" + default n + depends on WL_MFRC522 + +config MFRC522_DEBUG_TX + bool "trace TX frames" + default n + depends on MFRC522_DEBUG + +config MFRC522_DEBUG_RX + bool "trace RX frames" + default n + depends on MFRC522_DEBUG + +endif # WL_MFRC522 + config WL_PN532 bool "pn532 NFC-chip support" default n diff --git a/drivers/wireless/Make.defs b/drivers/wireless/Make.defs index 6322a5c0b0..48b356e7ac 100644 --- a/drivers/wireless/Make.defs +++ b/drivers/wireless/Make.defs @@ -55,6 +55,10 @@ ifeq ($(CONFIG_WL_CC3000),y) include wireless$(DELIM)cc3000$(DELIM)Make.defs endif +ifeq ($(CONFIG_WL_MFRC522),y) +CSRCS += mfrc522.c +endif + ifeq ($(CONFIG_WL_PN532),y) CSRCS += pn532.c endif diff --git a/drivers/wireless/mfrc522.c b/drivers/wireless/mfrc522.c new file mode 100644 index 0000000000..26d02b1286 --- /dev/null +++ b/drivers/wireless/mfrc522.c @@ -0,0 +1,1616 @@ +/**************************************************************************** + * drivers/wireless/mfrc522.c + * + * Copyright(C) 2016 Uniquix Ltda. All rights reserved. + * Author: Alan Carvalho de Assis + * + * This driver is based on Arduino library for MFRC522 from Miguel + * Balboa released into the public domain: + * https://github.com/miguelbalboa/rfid/ + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mfrc522.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_MFRC522_DEBUG +# define mfrc522err _err +# define mfrc522info _info +#else +# ifdef CONFIG_CPP_HAVE_VARARGS +# define mfrc522err(x...) +# define mfrc522info(x...) +# else +# define mfrc522err (void) +# define mfrc522info (void) +# endif +#endif + +#ifdef CONFIG_MFRC522_DEBUG_TX +# define tracetx errdumpbuffer +#else +# define tracetx(x...) +#endif + +#ifdef CONFIG_MFRC522_DEBUG_RX +# define tracerx errdumpbuffer +#else +# define tracerx(x...) +#endif + +#define FRAME_SIZE(f) (sizeof(struct mfrc522_frame) + f->len + 2) +#define FRAME_POSTAMBLE(f) (f->data[f->len + 1]) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline void mfrc522_configspi(FAR struct spi_dev_s *spi); +static void mfrc522_lock(FAR struct spi_dev_s *spi); +static void mfrc522_unlock(FAR struct spi_dev_s *spi); + +/* Character driver methods */ + +static int mfrc522_open(FAR struct file *filep); +static int mfrc522_close(FAR struct file *filep); +static ssize_t mfrc522_read(FAR struct file *, FAR char *, size_t); +static ssize_t mfrc522_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static int mfrc522_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); + +uint8_t mfrc522_readu8(FAR struct mfrc522_dev_s *dev, uint8_t regaddr); +void mfrc522_writeu8(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + FAR uint8_t regval); +void mfrc522_writeblk(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + uint8_t *regval, int length); +void mfrc522_readblk(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + FAR uint8_t *regval, int length, uint8_t rxalign); + +void mfrc522_softreset(FAR struct mfrc522_dev_s *dev); + +int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev, + FAR struct picc_uid_s *uid, uint8_t validbits); + +/* IRQ Handling TODO: +static int mfrc522_irqhandler(FAR int irq, FAR void *context, FAR void* dev); +static inline int mfrc522_attachirq(FAR struct mfrc522_dev_s *dev, xcpt_t isr); +*/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_mfrc522fops = +{ + mfrc522_open, + mfrc522_close, + mfrc522_read, + mfrc522_write, + 0, + mfrc522_ioctl +#ifndef CONFIG_DISABLE_POLL + , 0 +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , 0 +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void mfrc522_lock(FAR struct spi_dev_s *spi) +{ + (void)SPI_LOCK(spi, true); + + SPI_SETMODE(spi, SPIDEV_MODE0); + SPI_SETBITS(spi, 8); + (void)SPI_HWFEATURES(spi, 0); + (void)SPI_SETFREQUENCY(spi, CONFIG_MFRC522_SPI_FREQ); +} + +static void mfrc522_unlock(FAR struct spi_dev_s *spi) +{ + (void)SPI_LOCK(spi, false); +} + +static inline void mfrc522_configspi(FAR struct spi_dev_s *spi) +{ + /* Configure SPI for the MFRC522 module. */ + + SPI_SETMODE(spi, SPIDEV_MODE0); + SPI_SETBITS(spi, 8); + (void)SPI_HWFEATURES(spi, 0); + (void)SPI_SETFREQUENCY(spi, CONFIG_MFRC522_SPI_FREQ); +} + +static inline void mfrc522_select(struct mfrc522_dev_s *dev) +{ + SPI_SELECT(dev->spi, SPIDEV_WIRELESS, true); +} + +static inline void mfrc522_deselect(struct mfrc522_dev_s *dev) +{ + SPI_SELECT(dev->spi, SPIDEV_WIRELESS, false); +} + +/**************************************************************************** + * Name: mfrc522_readu8 + * + * Description: + * Read a byte from a register address. + * + * Input Parameters: + * + * Returned Value: the read byte from the register + * + ****************************************************************************/ + +uint8_t mfrc522_readu8(FAR struct mfrc522_dev_s *dev, uint8_t regaddr) +{ + uint8_t regval; + uint8_t address = (0x80 | (regaddr & 0x7E)); + + mfrc522_lock(dev->spi); + mfrc522_select(dev); + SPI_SEND(dev->spi, address); + regval = SPI_SEND(dev->spi, 0); + mfrc522_deselect(dev); + mfrc522_unlock(dev->spi); + + tracerx("read", regval, 1); + return regval; +} + +/**************************************************************************** + * Name: mfrc522_write8 + * + * Description: + * Write a byte to a register address. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +void mfrc522_writeu8(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + FAR uint8_t regval) +{ + mfrc522_lock(dev->spi); + mfrc522_select(dev); + SPI_SEND(dev->spi, regaddr & 0x7E); + SPI_SEND(dev->spi, regval); + mfrc522_deselect(dev); + mfrc522_unlock(dev->spi); + + tracerx("write", ®val, 1); +} + +/**************************************************************************** + * Name: mfrc522_readblk + * + * Description: + * Read a block of bytes from a register address. Align the bit positions of + * regval[0] from rxalign..7. + * + * Input Parameters: + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_readblk(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + FAR uint8_t *regval, int length, uint8_t rxalign) +{ + uint8_t i = 0; + uint8_t address = (0x80 | (regaddr & 0x7E)); + + mfrc522_lock(dev->spi); + mfrc522_select(dev); + + /* Inform the MFRC522 the address we want to read */ + + SPI_SEND(dev->spi, address); + + while (i < length) + { + if (i == 0 && rxalign) + { + uint8_t mask = 0; + uint8_t value; + uint8_t j; + + for (j = rxalign; j <= 7; j++) + { + mask |= (1 << j); + } + + /* Read the first byte */ + + value = SPI_SEND(dev->spi, address); + + /* Apply mask to current regval[0] with the read value */ + + regval[0] = (regval[0] & ~mask) | (value & mask); + } + else + { + /* Read the remaining bytes */ + + regval[i] = SPI_SEND(dev->spi, address); + } + i++; + } + + /* Read the last byte. Send 0 to stop reading (it maybe wrong, 1 byte out) */ + + regval[i] = SPI_SEND(dev->spi, 0); + + mfrc522_deselect(dev); + mfrc522_unlock(dev->spi); + + tracerx("readblk", regval, size); +} + +/**************************************************************************** + * Name: mfrc522_writeblk + * + * Description: + * Write a block of bytes to a register address. + * + * Input Parameters: + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_writeblk(FAR struct mfrc522_dev_s *dev, uint8_t regaddr, + uint8_t *regval, int length) +{ + uint8_t address = (regaddr & 0x7E); + + mfrc522_lock(dev->spi); + mfrc522_select(dev); + + /* Inform the MFRC522 the address we want write to */ + + SPI_SEND(dev->spi, address); + + /* Send the block of bytes */ + + SPI_SNDBLOCK(dev->spi, regval, length); + + mfrc522_deselect(dev); + mfrc522_unlock(dev->spi); + + tracerx("writeblk", regval, size); +} + +/**************************************************************************** + * Name: mfrc522_calc_crc + * + * Description: + * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A. + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_calc_crc(FAR struct mfrc522_dev_s *dev, uint8_t *buffer, + int length, uint8_t *result) +{ + struct timespec tstart; + struct timespec tend; + + /* Stop any command in execution */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_IDLE_CMD); + + /* Clear the CRCIRq interrupt request bit */ + + mfrc522_writeu8(dev, MFRC522_DIV_IRQ_REG, MFRC522_CRC_IRQ); + + /* Flush all bytes in the FIFO */ + + mfrc522_writeu8(dev, MFRC522_FIFO_LEVEL_REG, MFRC522_FLUSH_BUFFER); + + /* Write data to the FIFO */ + + mfrc522_writeblk(dev, MFRC522_FIFO_DATA_REG, buffer, length); + + /* Start the calculation */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_CALC_CRC_CMD); + + /* Wait for CRC completion or 200ms time-out */ + + clock_gettime(CLOCK_REALTIME, &tstart); + tstart.tv_nsec += 200000; + if (tstart.tv_nsec >= 1000 * 1000 * 1000) + { + tstart.tv_sec++; + tstart.tv_nsec -= 1000 * 1000 * 1000; + } + + while(1) + { + uint8_t irqreg; + + irqreg = mfrc522_readu8(dev, MFRC522_DIV_IRQ_REG); + if ( irqreg & MFRC522_CRC_IRQ) + { + break; + } + + /* Get time now */ + + clock_gettime(CLOCK_REALTIME, &tend); + + if ((tend.tv_sec > tstart.tv_sec) && (tend.tv_nsec > tstart.tv_nsec)) + { + return -ETIMEDOUT; + } + } + + /* Stop calculating CRC for new content of FIFO */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_IDLE_CMD); + + result[0] = mfrc522_readu8(dev, MFRC522_CRC_RESULT_REGL); + result[1] = mfrc522_readu8(dev, MFRC522_CRC_RESULT_REGH); + + return OK; +} + +/**************************************************************************** + * Name: mfrc522_comm_picc + * + * Description: + * Transfers data to the MFRC522 FIFO, executes a command, waits for + * completion and transfers data back from the FIFO. + * CRC validation can only be done if back_data and back_len are specified. + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_comm_picc(FAR struct mfrc522_dev_s *dev, uint8_t command, + uint8_t waitirq, uint8_t *send_data, uint8_t send_len, + uint8_t *back_data, uint8_t *back_len, + uint8_t *validbits, uint8_t rxalign, bool checkcrc) +{ + int ret; + uint8_t errors; + uint8_t vbits; + uint8_t value; + struct timespec tstart; + struct timespec tend; + + /* Prepare values for BitFramingReg */ + + uint8_t txlastbits = validbits ? *validbits : 0; + uint8_t bitframing = (rxalign << 4) + txlastbits; + + /* Stop any active command */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_IDLE_CMD); + + /* Clear all seven interrupt request bits */ + + value = mfrc522_readu8(dev, MFRC522_COM_IRQ_REG); + mfrc522_writeu8(dev, MFRC522_COM_IRQ_REG, value | MFRC522_COM_IRQ_MASK); + + /* Flush all bytes in the FIFO */ + + mfrc522_writeu8(dev, MFRC522_FIFO_LEVEL_REG, MFRC522_FLUSH_BUFFER); + + /* Write data to FIFO */ + + mfrc522_writeblk(dev, MFRC522_FIFO_DATA_REG, send_data, send_len); + + /* Bit adjustments */ + + mfrc522_writeu8(dev, MFRC522_BIT_FRAMING_REG, bitframing); + + /* Execute command */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, command); + + /* We setup the TAuto flag in the mfrc522_init() then we could use the + * internal MFC522 Timer to detect timeout, but because there could be some + * hardware fault, let us to use a NuttX timeout as well. + */ + + clock_gettime(CLOCK_REALTIME, &tstart); + tstart.tv_nsec += 200000; + if (tstart.tv_nsec >= 1000 * 1000 * 1000) + { + tstart.tv_sec++; + tstart.tv_nsec -= 1000 * 1000 * 1000; + } + + /* If it is a Transceive command, then start transmittion */ + + if (command == MFRC522_TRANSCV_CMD) + { + value = mfrc522_readu8(dev, MFRC522_BIT_FRAMING_REG); + mfrc522_writeu8(dev, MFRC522_BIT_FRAMING_REG, value | MFRC522_START_SEND); + } + + /* Wait for the command to complete */ + + while (1) + { + uint8_t irqsreg; + + irqsreg = mfrc522_readu8(dev, MFRC522_COM_IRQ_REG); + + /* If at least an of selected IRQ happened */ + + if (irqsreg & waitirq) + { + break; + } + + /* Timer expired */ + + if (irqsreg & MFRC522_TIMER_IRQ) + { + return -ETIMEDOUT; + } + + /* Get time now */ + + clock_gettime(CLOCK_REALTIME, &tend); + + if ((tend.tv_sec > tstart.tv_sec) && (tend.tv_nsec > tstart.tv_nsec)) + { + return -ETIMEDOUT; + } + } + + /* Read error register to verify if there are any issue */ + + errors = mfrc522_readu8(dev, MFRC522_ERROR_REG); + + /* Check for Protocol error */ + + if (errors & (MFRC522_PROTO_ERR)) + { + return -EPROTO; + } + + /* Check for Parity and Buffer Overflow errors */ + + if (errors & (MFRC522_PARITY_ERR | MFRC522_BUF_OVFL_ERR)) + { + return -EIO; + } + + /* Check collision error */ + + if (errors & MFRC522_COLL_ERR) + { + return -EBUSY; /* should it be EAGAIN ? */ + } + + /* If the caller wants data back, get it from the MFRC522 */ + + if (back_data && back_len) + { + uint8_t nbytes; + + /* Number of bytes in the FIFO */ + + nbytes = mfrc522_readu8(dev, MFRC522_FIFO_LEVEL_REG); + + /* Returned more bytes than the expected */ + + if (nbytes > *back_len) + { + return -ENOMEM; + } + + *back_len = nbytes; + + /* Read the data from FIFO */ + + mfrc522_readblk(dev, MFRC522_FIFO_DATA_REG, back_data, nbytes, rxalign); + + /* RxLastBits[2:0] indicates the number of valid bits received */ + + vbits = mfrc522_readu8(dev, MFRC522_CONTROL_REG) + & MFRC522_RX_LAST_BITS_MASK; + + if (validbits) + { + *validbits = vbits; + } + } + + /* Perform CRC_A validation if requested */ + + if (back_data && back_len && checkcrc) + { + uint8_t ctrlbuf[2]; + + /* In this case a MIFARE Classic NAK is not OK */ + + if (*back_len == 1 && vbits == 4) + { + return -EACCES; + } + + /* We need the CRC_A value or all 8 bits of the last byte */ + + if (*back_len < 2 || vbits != 0) + { + return -EPERM; + } + + /* Verify CRC_A */ + + ret = mfrc522_calc_crc(dev, &back_data[0], *back_len - 2, &ctrlbuf[0]); + if (ret != OK) + { + return ret; + } + + if ((back_data[*back_len - 2] != ctrlbuf[0]) || + (back_data[*back_len - 1] != ctrlbuf[1])) + { + return -EFAULT; + } + } + + return OK; +} + +/**************************************************************************** + * Name: mfrc522_transcv_data + * + * Description: + * Executes the Transceive command + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_transcv_data(FAR struct mfrc522_dev_s *dev, uint8_t *senddata, + uint8_t sendlen, uint8_t *backdata, uint8_t *backlen, + uint8_t *validbits, uint8_t rxalign, bool check_crc) +{ + uint8_t waitirq = MFRC522_RX_IRQ | MFRC522_IDLE_IRQ; + + return mfrc522_comm_picc(dev, MFRC522_TRANSCV_CMD, waitirq, senddata, + sendlen, backdata, backlen, validbits, rxalign, + check_crc); +} + +/**************************************************************************** + * Name: mfrc522_picc_reqa_wupa + * + * Description: + * Transmits REQA or WUPA commands + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_picc_reqa_wupa(FAR struct mfrc522_dev_s *dev, uint8_t command, + uint8_t *buffer, uint8_t length) +{ + uint8_t validbits; + uint8_t value; + int status; + + if (!buffer || length < 2) + { + return -EINVAL; + } + + /* Force clear of received bits if a collision is detected */ + + value = mfrc522_readu8(dev, MFRC522_COLL_REG); + mfrc522_writeu8(dev, MFRC522_COLL_REG, value & MFRC522_VALUES_AFTER_COLL); + + validbits = 7; + status = mfrc522_transcv_data(dev, &command, 1, buffer, &length, &validbits, + 0, false); + + /* For REQA and WUPA we need to transmit only 7 bits */ + + if (status != OK) + { + return status; + } + + /* ATQA must be exactly 16 bits */ + + if (length != 2 || validbits != 0) + { + return -EAGAIN; + } + + mfrc522info("buffer[0]=0x%02X | buffer[1]=0x%02X\n", buffer[0], buffer[1]); + return OK; +} + +/**************************************************************************** + * Name: mfrc522_picc_request_a + * + * Description: + * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to + * READY and prepare for anticollision or selection. + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_picc_request_a(FAR struct mfrc522_dev_s *dev, uint8_t *buffer, + uint8_t length) +{ + return mfrc522_picc_reqa_wupa(dev, PICC_CMD_REQA, buffer, length); +} + +/**************************************************************************** + * Name: mfrc522_picc_detect + * + * Description: + * Detects if a Contactless Card is near + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_picc_detect(FAR struct mfrc522_dev_s *dev) +{ + int ret; + uint8_t buffer_atqa[2]; + uint8_t length = sizeof(buffer_atqa); + + /* Send a REQA command */ + + ret = mfrc522_picc_request_a(dev, buffer_atqa, length); + return (ret == OK || ret == -EBUSY); +} + +/**************************************************************************** + * Name: mfrc522_picc_select + * + * Description: + * Selects a near Card and read its UID. + * + * Input Parameters: + * + * Returned Value: OK or -ETIMEDOUT + * + ****************************************************************************/ + +int mfrc522_picc_select(FAR struct mfrc522_dev_s *dev, + FAR struct picc_uid_s *uid, uint8_t validbits) +{ + bool uid_complete; + bool select_done; + bool use_cascade_tag; + uint8_t cascade_level = 1; + int result; + uint8_t i; + uint8_t value; + uint8_t count; + + /* The first index in uid->data[] that is used in the current Cascade Level */ + + uint8_t uid_index; + + /* The number of known UID bits in the current Cascade Level. */ + + uint8_t curr_level_known_bits; + + /* The SELECT/ANTICOLLISION uses a 7 byte standard frame + 2 bytes CRC_A */ + + uint8_t buffer[9]; + + /* The number of bytes used in the buffer, number bytes on FIFO */ + + uint8_t buffer_used; + + /* Used to defines the bit position for the first bit received */ + + uint8_t rxalign; + + /* The number of valid bits in the last transmitted byte. */ + + uint8_t txlastbits; + + uint8_t *resp_buf; + uint8_t resp_len; + + /* Sanity check */ + + if (validbits > 80) + { + return -EINVAL; + } + + /* Force clear of received bits if a collision is detected */ + + value = mfrc522_readu8(dev, MFRC522_COLL_REG); + mfrc522_writeu8(dev, MFRC522_COLL_REG, value & MFRC522_VALUES_AFTER_COLL); + + /* Repeat cascade level loop until we have a complete UID */ + + uid_complete = false; + while (!uid_complete) + { + uint8_t bytes_to_copy; + + /* Set the Cascade Level in the SEL byte, find out if we need to use the + * Cascade Tag in byte 2. + */ + + switch (cascade_level) + { + case 1: + buffer[0] = PICC_CMD_SEL_CL1; + uid_index = 0; + + /* When we know that the UID has more than 4 bytes */ + + use_cascade_tag = validbits && (uid->size > 4); + break; + + case 2: + buffer[0] = PICC_CMD_SEL_CL2; + uid_index = 3; + + /* When we know that the UID has more than 7 bytes */ + + use_cascade_tag = validbits && (uid->size > 7); + break; + + case 3: + buffer[0] = PICC_CMD_SEL_CL3; + uid_index = 6; + use_cascade_tag = false; + break; + + default: + return -EIO; /* Internal error */ + } + + /* How many UID bits are known in this Cascade Level? */ + + curr_level_known_bits = validbits - (8 * uid_index); + if (curr_level_known_bits < 0) + { + curr_level_known_bits = 0; + } + + /* Copy the known bits from uid->uid_data[] to buffer[] */ + + i = 2; /* destination index in buffer[] */ + if (use_cascade_tag) + { + buffer[i++] = PICC_CMD_CT; + } + + /* Number of bytes needed to represent the known bits for this level */ + + bytes_to_copy = curr_level_known_bits / 8 + + (curr_level_known_bits % 8 ? 1 : 0); + + if (bytes_to_copy) + { + /* Max 4 bytes in each Cascade Level. Only 3 left if we use the + * Cascade Tag. + */ + + uint8_t max_bytes = use_cascade_tag ? 3 : 4; + + if (bytes_to_copy > max_bytes) + { + bytes_to_copy = max_bytes; + } + + for (count = 0; count < bytes_to_copy; count++) + { + buffer[i++] = uid->uid_data[uid_index + count]; + } + } + + /* Now that the data has been copied we need to include the 8 bits in CT + * in curr_level_known_bits. + */ + + if (use_cascade_tag) + { + curr_level_known_bits += 8; + } + + /* Repeat anti collision loop until we can transmit all UID bits + BCC + * and receive a SAK - max 32 iterations. + */ + + select_done = false; + while (!select_done) + { + /* Find out how many bits and bytes to send and receive. */ + + if (curr_level_known_bits >= 32) + { + /* All UID bits in this Cascade Level are known. This is a + * SELECT. + */ + + /* NVB - Number of Valid Bits: Seven whole bytes */ + + buffer[1] = 0x70; + + /* Calculate BCC - Block Check Character */ + + buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5]; + + /* Calculate CRC_A */ + + result = mfrc522_calc_crc(dev, buffer, 7, &buffer[7]); + if (result != OK) + { + return result; + } + + txlastbits = 0; /* 0 => All 8 bits are valid. */ + buffer_used = 9; + + /* Store response in the last 3 bytes of buffer (BCC and CRC_A - + * not needed after tx). + */ + + resp_buf = &buffer[6]; + resp_len = 3; + } + else + { + /* This is an ANTICOLLISION */ + + txlastbits = curr_level_known_bits % 8; + + /* Number of whole bytes in the UID part. */ + + count = curr_level_known_bits / 8; + i = 2 + count; + + /* NVB - Number of Valid Bits */ + + buffer[1] = (i << 4) + txlastbits; + buffer_used = i + (txlastbits ? 1 : 0); + + /* Store response in the unused part of buffer */ + + resp_buf = &buffer[i]; + resp_len = sizeof(buffer) - i; + } + + /* Set bit adjustments */ + + rxalign = txlastbits; + mfrc522_writeu8(dev, MFRC522_BIT_FRAMING_REG, + (rxalign << 4) + txlastbits); + + /* Transmit the buffer and receive the response */ + + result = mfrc522_transcv_data(dev, buffer, buffer_used, resp_buf, + &resp_len, &txlastbits, rxalign, false); + + /* More than one PICC in the field => collision */ + + if (result == -EBUSY) + { + uint8_t coll_pos; + uint8_t coll_reg = mfrc522_readu8(dev, MFRC522_COLL_REG); + + /* CollPosNotValid */ + + if (coll_reg & 0x20) + { + /* Without a valid collision position we cannot continue */ + + return -EBUSY; + } + + coll_pos = coll_reg & 0x1F; /* Values 0-31, 0 means bit 32. */ + if (coll_pos == 0) + { + coll_pos = 32; + } + + if (coll_pos <= curr_level_known_bits) + { + /* No progress - should not happen */ + + return -EIO; + } + + /* Choose the PICC with the bit set. */ + + curr_level_known_bits = coll_pos; + + /* The bit to modify */ + + count = (curr_level_known_bits - 1) % 8; + + /* First byte is index 0. */ + + i = 1 + (curr_level_known_bits / 8) + (count ? 1 : 0); + buffer[i] |= (1 << count); + } + else if (result != OK) + { + return result; + } + else /* OK */ + { + /* This was a SELECT. */ + + if (curr_level_known_bits >= 32) + { + /* No more collision */ + + select_done = true; + } + else + { + /* This was an ANTICOLLISION. */ + /* We have all 32 bits of the UID in this Cascade Level */ + + curr_level_known_bits = 32; + + /* Run loop again to do the SELECT */ + } + } + } + + /* We do not check the CBB - it was constructed by us above. */ + /* Copy the found UID bytes from buffer[] to uid->uid_data[] */ + + i = (buffer[2] == PICC_CMD_CT) ? 3 : 2; /* source index in buffer[] */ + bytes_to_copy = (buffer[2] == PICC_CMD_CT) ? 3 : 4; + + for (count = 0; count < bytes_to_copy; count++) + { + uid->uid_data[uid_index + count] = buffer[i++]; + } + + /* Check response SAK (Select Acknowledge) */ + + if (resp_len != 3 || txlastbits != 0) + { + /* SAK must be exactly 24 bits (1 byte + CRC_A). */ + + return -EIO; + } + + /* Verify CRC_A - do our own calculation and store the control in + * buffer[2..3] - those bytes are not needed anymore. + */ + + result = mfrc522_calc_crc(dev, resp_buf, 1, &buffer[2]); + if (result != OK) + { + return result; + } + + /* Is it correct */ + + if ((buffer[2] != resp_buf[1]) || (buffer[3] != resp_buf[2])) + { + return -EINVAL; + } + + /* Cascade bit set - UID not complete yes */ + + if (resp_buf[0] & 0x04) + { + cascade_level++; + } + else + { + uid_complete = true; + uid->sak = resp_buf[0]; + } + } + + /* Set correct uid->size */ + + uid->size = 3 * cascade_level + 1; + + return OK; +} + +/**************************************************************************** + * Name: mfrc522_softreset + * + * Description: + * Send a software reset command + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_softreset(FAR struct mfrc522_dev_s *dev) +{ + /* Send a software reset command */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_SOFTRST_CMD); + + /* Wait the internal state machine to initialize */ + + usleep(50000); + + /* Wait for the PowerDown bit in COMMAND_REG to be cleared */ + + while (mfrc522_readu8(dev, MFRC522_COMMAND_REG) & MFRC522_POWER_DOWN); +} + +/**************************************************************************** + * Name: mfrc522_enableantenna + * + * Description: + * Turns the antenna on by enabling the pins TX1 and TX2 + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_enableantenna(FAR struct mfrc522_dev_s *dev) +{ + uint8_t value = mfrc522_readu8(dev, MFRC522_TX_CTRL_REG); + + if ((value & (MFRC522_TX1_RF_EN | MFRC522_TX2_RF_EN)) != 0x03) + { + mfrc522_writeu8(dev, MFRC522_TX_CTRL_REG, value | 0x03); + } +} + +/**************************************************************************** + * Name: mfrc522_disableantenna + * + * Description: + * Turns the antenna off cutting the signals on TX1 and TX2 + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_disableantenna(FAR struct mfrc522_dev_s *dev) +{ + uint8_t value = mfrc522_readu8(dev, MFRC522_TX_CTRL_REG); + + value &= ~(MFRC522_TX1_RF_EN | MFRC522_TX2_RF_EN); + mfrc522_writeu8(dev, MFRC522_TX_CTRL_REG, value); +} + +/**************************************************************************** + * Name: mfrc522_getfwversion + * + * Description: + * Read the MFRC522 firmware version. + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: the firmware version byte + * + ****************************************************************************/ + +uint8_t mfrc522_getfwversion(FAR struct mfrc522_dev_s *dev) +{ + return mfrc522_readu8(dev, MFRC522_VERSION_REG); +} + +/**************************************************************************** + * Name: mfrc522_getantennagain + * + * Description: + * Read the MFRC522 receiver gain (RxGain). + * See 9.3.3.6 / table 98 in MFRC522 datasheet. + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +uint8_t mfrc522_getantennagain(FAR struct mfrc522_dev_s *dev) +{ + return mfrc522_readu8(dev, MFRC522_RF_CFG_REG) & MFRC522_RX_GAIN_MASK; +} + +/**************************************************************************** + * Name: mfrc522_setantennagain + * + * Description: + * Set the MFRC522 receiver gain (RxGain) to value value specified in mask. + * See 9.3.3.6 / table 98 in MFRC522 datasheet. + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_setantennagain(FAR struct mfrc522_dev_s *dev, uint8_t mask) +{ + uint8_t value; + + if ((value = mfrc522_getantennagain(dev)) != mask) + { + mfrc522_writeu8(dev, MFRC522_RF_CFG_REG, value & ~MFRC522_RX_GAIN_MASK); + mfrc522_writeu8(dev, MFRC522_RF_CFG_REG, mask & MFRC522_RX_GAIN_MASK); + } +} + +/**************************************************************************** + * Name: mfrc522_init + * + * Description: + * Initializes the MFRC522 chip + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +void mfrc522_init(FAR struct mfrc522_dev_s *dev) +{ + /* Force a reset */ + + mfrc522_softreset(dev); + + /* We need a timeout if something when communicating with a TAG case + * something goes wrong. f_timer = 13.56 MHz / (2*TPreScaler+1) where: + * TPreScaler = [TPrescaler_Hi:Tprescaler_Lo]. Tprescaler_Hi are the four + * low bits in TmodeReg. Tprescaler_Lo is on TPrescalerReg. + * + * TAuto=1; timer starts automatically at the end of the transmission in + * all communication modes at all speeds. + */ + + mfrc522_writeu8(dev, MFRC522_TMODE_REG, MFRC522_TAUTO); + + /* TPreScaler = TModeReg[3..0]:TPrescalerReg, ie: 0x0A9 = 169 => + * f_timer=40kHz, then the timer period will be 25us. + */ + + mfrc522_writeu8(dev, MFRC522_TPRESCALER_REG, 0xA9); + + /* Reload timer with 0x3E8 = 1000, ie 25ms before timeout. */ + + mfrc522_writeu8(dev, MFRC522_TRELOAD_REGH, 0x06); + mfrc522_writeu8(dev, MFRC522_TRELOAD_REGL, 0xE8); + + /* Force 100% ASK modulation independent of the ModGsPReg setting */ + + mfrc522_writeu8(dev, MFRC522_TX_ASK_REG, MFRC522_FORCE_100ASK); + + /* Set the preset value for the CRC to 0x6363 (ISO 14443-3 part 6.2.4) */ + + mfrc522_writeu8(dev, MFRC522_MODE_REG, 0x3D); + + /* Enable the Antenna pins */ + + mfrc522_enableantenna(dev); +} + +/**************************************************************************** + * Name: mfrc522_selftest + * + * Description: + * Executes a self-test of the MFRC522 chip + * + * See 16.1.1 in the MFRC522 datasheet + * + * Input Parameters: a pointer to mfrc522_dev_s structure + * + * Returned Value: none + * + ****************************************************************************/ + +int mfrc522_selftest(FAR struct mfrc522_dev_s *dev) +{ + uint8_t i; + uint8_t result[64]; + uint8_t zeros[25] = {0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0}; + + /* Execute a software reset */ + + mfrc522_softreset(dev); + + /* Flush the FIFO buffer */ + + mfrc522_writeu8(dev, MFRC522_FIFO_LEVEL_REG, MFRC522_FLUSH_BUFFER); + + /* Clear the internal buffer by writing 25 bytes 0x00 */ + + mfrc522_writeblk(dev, MFRC522_FIFO_DATA_REG, zeros, 25); + + /* Transfer to internal buffer */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_MEM_CMD); + + /* Enable self-test */ + + mfrc522_writeu8(dev, MFRC522_AUTOTEST_REG, MFRC522_SELFTEST_EN); + + /* Write 0x00 to FIFO buffer */ + + mfrc522_writeu8(dev, MFRC522_FIFO_DATA_REG, 0x00); + + /* Start self-test by issuing the CalcCRC command */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_CALC_CRC_CMD); + + /* Wait for self-test to complete */ + + for (i = 0; i < 255; i++) + { + uint8_t n; + + n = mfrc522_readu8(dev, MFRC522_DIV_IRQ_REG); + if (n & MFRC522_CRC_IRQ) + { + break; + } + } + + /* Stop calculating CRC for new content in the FIFO */ + + mfrc522_writeu8(dev, MFRC522_COMMAND_REG, MFRC522_IDLE_CMD); + + /* Read out the 64 bytes result from the FIFO buffer */ + + mfrc522_readblk(dev, MFRC522_FIFO_DATA_REG, result, 64, 0); + + /* Self-test done. Reset AutoTestReg register to normal operation */ + + mfrc522_writeu8(dev, MFRC522_AUTOTEST_REG, 0x00); + + mfrc522info("Self Test Result:\n"); + for (i = 1; i <= 64; i++) + { + printf("0x%02X ", result[i - 1]); + + if ((i % 8) == 0) + { + printf("\n"); + } + } + + mfrc522info("Done!\n"); + return OK; +} + +/**************************************************************************** + * Name: mfrc522_open + * + * Description: + * This function is called whenever the MFRC522 device is opened. + * + ****************************************************************************/ + +static int mfrc522_open(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct mfrc522_dev_s *dev; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + dev = inode->i_private; + + mfrc522_configspi(dev->spi); + + usleep(10000); + + mfrc522_getfwversion(dev); + + dev->state = MFRC522_STATE_IDLE; + return OK; +} + +/**************************************************************************** + * Name: mfrc522_close + * + * Description: + * This routine is called when the MFRC522 device is closed. + * + ****************************************************************************/ + +static int mfrc522_close(FAR struct file *filep) +{ + FAR struct inode *inode; + FAR struct mfrc522_dev_s *dev; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + dev = inode->i_private; + + dev->state = MFRC522_STATE_NOT_INIT; + + return OK; +} + +/**************************************************************************** + * Name: mfrc522_read + * + * Description: + * This routine is called when the device is read. + * + * Returns TAG id as string to buffer. + * or -EIO if no TAG found + * + ****************************************************************************/ + +static ssize_t mfrc522_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct inode *inode; + FAR struct mfrc522_dev_s *dev; + FAR struct picc_uid_s uid; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + dev = inode->i_private; + + /* Is a card near? */ + + if (!mfrc522_picc_detect(dev)) + { + mfrc522err("Card is not present!\n"); + return -EAGAIN; + } + + /* Now read the UID */ + + mfrc522_picc_select(dev, &uid, 0); + + if (uid.sak != 0) + { + if (buffer) + { + snprintf(buffer, buflen, "0x%02X%02X%02X%02X", + uid.uid_data[0], uid.uid_data[1], + uid.uid_data[2], uid.uid_data[3]); + return buflen; + } + } + + return OK; +} + +/**************************************************************************** + * Name: mfrc522_write + ****************************************************************************/ + +static ssize_t mfrc522_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen) +{ + FAR struct inode *inode; + FAR struct mfrc522_dev_s *dev; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + dev = inode->i_private; + + (void)dev; + + return -ENOSYS; +} + +/**************************************************************************** + * Name: mfrc522_ioctl + ****************************************************************************/ + +static int mfrc522_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode; + FAR struct mfrc522_dev_s *dev; + int ret = OK; + + DEBUGASSERT(filep); + inode = filep->f_inode; + + DEBUGASSERT(inode && inode->i_private); + dev = inode->i_private; + + switch (cmd) + { + case MFRC522IOC_GET_PICC_UID: + { + struct picc_uid_s *uid = (struct picc_uid_s *)arg; + + /* Is a card near? */ + + if (mfrc522_picc_detect(dev)) + { + ret = mfrc522_picc_select(dev, uid, 0); + } + } + break; + + case MFRC522IOC_GET_STATE: + ret = dev->state; + break; + + default: + mfrc522err("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mfrc522_register + * + * Description: + * Register the MFRC522 character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. + * E.g., "/dev/rfid0" + * spi - An instance of the SPI interface to use to communicate with + * MFRC522. + * config - chip config + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int mfrc522_register(FAR const char *devpath, FAR struct spi_dev_s *spi) +{ + FAR struct mfrc522_dev_s *dev; + uint8_t fwver; + int ret = 0; + + /* Initialize the MFRC522 device structure */ + + dev = (FAR struct mfrc522_dev_s *)kmm_malloc(sizeof(struct mfrc522_dev_s)); + if (!dev) + { + mfrc522err("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + dev->spi = spi; + + /* Device is not initialized yet */ + + dev->state = MFRC522_STATE_NOT_INIT; + +#if defined CONFIG_PM + dev->pm_level = PM_IDLE; +#endif + + /* mfrc522_attachirq(dev, mfrc522_irqhandler); */ + + /* Initialize the MFRC522 */ + + mfrc522_init(dev); + + /* Device initialized and idle */ + + dev->state = MFRC522_STATE_IDLE; + + /* Read the Firmware Version */ + + fwver = mfrc522_getfwversion(dev); + + mfrc522info("MFRC522 Firmware Version: 0x%02X!\n", fwver); + + /* If returned firmware version is unknown don't register the device */ + + if (fwver != 0x90 && fwver != 0x91 && fwver != 0x92 && fwver != 0x88 ) + { + mfrc522err("None supported device detected!\n"); + goto firmware_error; + } + + /* Register the character driver */ + + ret = register_driver(devpath, &g_mfrc522fops, 0666, dev); + if (ret < 0) + { + mfrc522err("ERROR: Failed to register driver: %d\n", ret); + kmm_free(dev); + } + + return ret; + +firmware_error: + free(dev); + return -ENODEV; +} diff --git a/drivers/wireless/mfrc522.h b/drivers/wireless/mfrc522.h new file mode 100644 index 0000000000..821b82c0a4 --- /dev/null +++ b/drivers/wireless/mfrc522.h @@ -0,0 +1,430 @@ +/**************************************************************************** + * drivers/wireless/mfrc522.h + * + * Copyright(C) 2016 Uniquix Ltda. All rights reserved. + * Authors: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __DRIVERS_WIRELESS_MFRC522_H +#define __DRIVERS_WIRELESS_MFRC522_H 1 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/* The commands used by the PCD to manage communication with several PICCs + * (ISO 14443-3, Type A, section 6.4) + */ + +#define PICC_CMD_REQA 0x26 /* REQuest command, Type A */ +#define PICC_CMD_WUPA 0x52 /* Wake-UP command, Type A */ +#define PICC_CMD_CT 0x88 /* Cascade Tag, used during anti collision. */ +#define PICC_CMD_SEL_CL1 0x93 /* Anti collision/Select, Cascade Level 1 */ +#define PICC_CMD_SEL_CL2 0x95 /* Anti collision/Select, Cascade Level 2 */ +#define PICC_CMD_SEL_CL3 0x97 /* Anti collision/Select, Cascade Level 3 */ +#define PICC_CMD_HLTA 0x50 /* HaLT command, Type A */ + +/* The commands used for MIFARE Classic + * (from http://www.mouser.com/ds/2/302/MF1S503x-89574.pdf, Section 9) + * Use PCD_MFAuthent to authenticate access to a sector, then use these + * commands to read/write/modify the blocks on the sector. + * The read/write commands can also be used for MIFARE Ultralight. + */ + +#define PICC_CMD_MF_AUTH_KEY_A 0x60 /* Perform authentication with Key A */ +#define PICC_CMD_MF_AUTH_KEY_B 0x61 /* Perform authentication with Key B */ +#define PICC_CMD_MF_READ 0x30 /* Reads one 16 byte block from auth sector */ +#define PICC_CMD_MF_WRITE 0xA0 /* Writes one 16 byte block to auth senctor */ +#define PICC_CMD_MF_DECREMENT 0xC0 /* Decrements contents of a block */ +#define PICC_CMD_MF_INCREMENT 0xC1 /* Increments contents of a block */ +#define PICC_CMD_MF_RESTORE 0xC2 /* Reads the contents of a block */ +#define PICC_CMD_MF_TRANSFER 0xB0 /* Writes the contents of a block */ + +/* The commands used for MIFARE Ultralight + * (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6) + * The PICC_CMD_MF_READ/_MF_WRITE can also be used for MIFARE Ultralight. + */ + +#define PICC_CMD_UL_WRITE 0xA2 /* Writes one 4 byte page to the PICC. */ + +/* MFRC522 Registers */ + +/* NOTE: All SPI addresses are shifted one bit left in the SPI address byte + * See section 8.1.2.3 from MFRC522 datasheet + */ + +/* Page 0: Commands and status */ + /* 0x00 - reserved for future use */ +#define MFRC522_COMMAND_REG (0x01 << 1) /* starts/stops command execution */ +#define MFRC522_COM_IEN_REG (0x02 << 1) /* dis/enable int. req. ctrl bits */ +#define MFRC522_DIV_IEN_REG (0x03 << 1) /* dis/enable int. req. ctrl bits */ +#define MFRC522_COM_IRQ_REG (0x04 << 1) /* interrupt request bits */ +#define MFRC522_DIV_IRQ_REG (0x05 << 1) /* interrupt request bits */ +#define MFRC522_ERROR_REG (0x06 << 1) /* error bits status of last cmd */ +#define MFRC522_STATUS1_REG (0x07 << 1) /* communication status bits */ +#define MFRC522_STATUS2_REG (0x08 << 1) /* rcvr and transmitter status */ +#define MFRC522_FIFO_DATA_REG (0x09 << 1) /* input/output of FIFO buffer */ +#define MFRC522_FIFO_LEVEL_REG (0x0A << 1) /* number of bytes stored in the FIFO */ +#define MFRC522_WATER_LEVEL_REG (0x0B << 1) /* level for FIFO under/overflow */ +#define MFRC522_CONTROL_REG (0x0C << 1) /* miscellaneos control register */ +#define MFRC522_BIT_FRAMING_REG (0x0D << 1) /* adjustments for bit-oriented frames */ +#define MFRC522_COLL_REG (0x0E << 1) /* bit position of first bit-collision detected */ + /* 0x0F - reserved for future use */ +/* Page 1: Commands */ + /* 0x10 - reserved for future use */ +#define MFRC522_MODE_REG (0x11 << 1) /* defines general modes for transmit/receive */ +#define MFRC522_TX_MODE_REG (0x12 << 1) /* defines transmission data rate and framing */ +#define MFRC522_RX_MODE_REG (0x13 << 1) /* defines reception data rate and framing */ +#define MFRC522_TX_CTRL_REG (0x14 << 1) /* controls antenna driver pins TX1 and TX2 */ +#define MFRC522_TX_ASK_REG (0x15 << 1) /* controls the setting of transmission modulation */ +#define MFRC522_TX_SEL_REG (0x16 << 1) /* selects the internal sources for antenna driver */ +#define MFRC522_RX_SEL_REG (0x17 << 1) /* selects the internal receiver settings */ +#define MFRC522_RX_THLD_REG (0x18 << 1) /* selects the thresholds for bit decoder */ +#define MFRC522_DEMOD_REG (0x19 << 1) /* defines demodulator settings */ + /* 0x1A - reserved for future use */ + /* 0x1B - reserved for future use */ +#define MFRC522_MF_TX_REG (0x1C << 1) /* controls some MIFARE comm tx param */ +#define MFRC522_MF_RX_REG (0x1D << 1) /* controls some MIFARE comm rx param */ + /* 0x1E - reserved for future use */ +#define MFRC522_SERIAL_SPD_REG (0x1F << 1) /* selects the speed of the serial UART */ + +/* Page 2: Configuration */ + /* 0x20 - reserved for future use */ +#define MFRC522_CRC_RESULT_REGH (0x21 << 1) /* shows the MSB values of CRC calc. */ +#define MFRC522_CRC_RESULT_REGL (0x22 << 1) /* shows the LSB values of CRC calc. */ + /* 0x23 - reserved for future use */ +#define MFRC522_MOD_WIDTH_REG (0x24 << 1) /* controls the ModWidth setting */ + /* 0x25 - reserved for future use */ +#define MFRC522_RF_CFG_REG (0x26 << 1) /* configures the receiver gain */ +#define MFRC522_GSN_REG (0x27 << 1) /* selects the conductance of n-driver TX1/2 */ +#define MFRC522_CW_GSP_REG (0x28 << 1) /* defines the conductance of p-driver during no modulation */ +#define MFRC522_MOD_GSP_REG (0x29 << 1) /* defines the conductance of p-driver during modulation */ +#define MFRC522_TMODE_REG (0x2A << 1) /* defines settings for the internal timer */ +#define MFRC522_TPRESCALER_REG (0x2B << 1) /* the lower 8 bits of TPrescaler value */ +#define MFRC522_TRELOAD_REGH (0x2C << 1) /* defines the 16-bit timer reload value */ +#define MFRC522_TRELOAD_REGL (0x2D << 1) /* defines the 16-bit timer reload value */ +#define MFRC522_TCOUNT_VAL_REGH (0x2E << 1) /* shows the 16-bit timer value */ +#define MFRC522_TCOUNT_VAL_REGL (0x2F << 1) /* shows the 16-bit timer value */ + +/* Page 3: Test Registers */ + /* 0x30 - reserved for future use */ +#define MFRC522_TEST_SEL1_REG (0x31 << 1) /* general test signal configuration */ +#define MFRC522_TEST_SEL2_REG (0x32 << 1) /* general test signal configuration */ +#define MFRC522_TEST_PIN_EN_REG (0x33 << 1) /* enables pin output driver on pins D1 to D7 */ +#define MFRC522_TEST_PIN_VAL_REG (0x34 << 1) /* defines the values to D1 to D7 */ +#define MFRC522_TEST_BUS_REG (0x35 << 1) /* shows the status of the internal test bus */ +#define MFRC522_AUTOTEST_REG (0x36 << 1) /* controls the digital self test */ +#define MFRC522_VERSION_REG (0x37 << 1) /* shows the software version */ +#define MFRC522_ANALOG_TEST_REG (0x38 << 1) /* controls the pins AUX1 and AUX2 */ +#define MFRC522_TEST_DAC1_REG (0x39 << 1) /* defines the test value for TestDAC1 */ +#define MFRC522_TEST_DAC2_REG (0x3A << 1) /* defines the test value for TestDAC2 */ +#define MFRC522_TEST_ADC_REG (0x3B << 1) /* show the value of ADC I and Q channels */ + +/* Section 9.3.1.2: MFRC522 Command Register */ + +#define MFRC522_CMD_MASK 0x0F +# define MFRC522_IDLE_CMD 0x00 /* no action, cancels current command execution */ +# define MFRC522_MEM_CMD 0x01 /* stores 25 bytes into the internal buffer */ +# define MFRC522_GEN_RND_ID_CMD 0x02 /* generates a 10-bytes random ID number */ +# define MFRC522_CALC_CRC_CMD 0x03 /* activates the CRC coprocessor or self test */ +# define MFRC522_TRANSMIT_CMD 0x04 /* transmits data from the FIFO buffer */ +# define MFRC522_NO_CHANGE_CMD 0x07 /* no command change, used to modify CommandReg */ +# define MFRC522_RECEIVE_CMD 0x08 /* activates the receiver circuits */ +# define MFRC522_TRANSCV_CMD 0x0C /* transmits data from FIFO and receive automatically */ +# define MFRC522_MF_AUTH_CMD 0x0E /* performs the MIFARE stand authentication as a reader */ +# define MFRC522_SOFTRST_CMD 0x0F /* resets the MFRC522 */ +#define MFRC522_POWER_DOWN (1 << 4) /* soft power-down mode entered */ +#define MFRC522_RCV_OFF (1 << 5) /* turns off analog part of receiver */ + +/* Section 9.3.1.3: ComIEnReg register */ + +#define MFRC522_TIMER_IEN (1 << 0) /* allows the timer interrupt request on pin IRQ */ +#define MFRC522_ERR_IEN (1 << 1) /* allows the error interrupt request on pin IRQ */ +#define MFRC522_LO_ALERT_IEN (1 << 2) /* allows the low alert interrupt request on pin IRQ */ +#define MFRC522_HI_ALERT_IEN (1 << 3) /* allows the high alert interrupt request on pin IRQ */ +#define MFRC522_IDLE_IEN (1 << 4) /* allows the idle interrupt request on pin IRQ */ +#define MFRC522_RX_IEN (1 << 5) /* allows the receiver interrupt request on pin IRQ */ +#define MFRC522_TX_IEN (1 << 6) /* allows the transmitter interrupt request on pin IRQ */ +#define MFRC522_IRQ_INV (1 << 7) /* signal on pin IRQ is inverse of IRq bit from Status1Reg */ + +/* Section 9.3.1.4: DivIEnReg register */ + +#define MFRC522_CRC_IEN (1 << 2) /* allows the CRC interrupt request on pin IRQ */ +#define MFRC522_MFIN_ACT_IEN (1 << 4) /* allows the MFIN active interrupt request on pin IRQ */ +#define MFRC522_IRQ_PUSH_PULL (1 << 7) /* 1 = IRQ pin is a standard CMOS output pin, 0 = open-drain */ + +/* Section 9.3.1.5: ComIrqReg register */ + +#define MFRC522_COM_IRQ_MASK (0x7F) +#define MFRC522_TIMER_IRQ (1 << 0) /* enabled when TCounterValReg reaches value 0 */ +#define MFRC522_ERR_IRQ (1 << 1) /* any error bit in the ErrorReg register is set */ +#define MFRC522_LO_ALERT_IRQ (1 << 2) /* Status1Reg register’s LoAlert bit is set */ +#define MFRC522_HI_ALERT_IRQ (1 << 3) /* Status1Reg register’s HiAlert bit is set */ +#define MFRC522_IDLE_IRQ (1 << 4) /* if a command terminates this bit is set */ +#define MFRC522_RX_IRQ (1 << 5) /* receiver has detected the end of a valid data stream */ +#define MFRC522_TX_IRQ (1 << 6) /* set immediately after the last data bit was transmitted */ +#define MFRC522_SET1 (1 << 7) /* indicate the status of ComIrqReg bits */ + +/* Section 9.3.1.6: DivIrqReg register */ + +#define MFRC522_CRC_IRQ (1 << 2) /* the CalcCRC command is active and all data is processed */ +#define MFRC522_MFIN_ACT_IRQ (1 << 4) /* MFIN is active, int is set on rising/falling signal edge */ +#define MFRC522_SET2 (1 << 7) /* indicates the status of the marked bits in the DivIrqReg */ + +/* Section 9.3.1.7: ErrorReg register */ + +#define MFRC522_PROTO_ERR (1 << 0) /* set if the SOF is incorrect or during MFAuthent if data is incorrect */ +#define MFRC522_PARITY_ERR (1 << 1) /* parity check failed */ +#define MFRC522_CRC_ERR (1 << 2) /* the RxCRCEn bit is set and the CRC calculation fails */ +#define MFRC522_COLL_ERR (1 << 3) /* a bit-collision is detected */ +#define MFRC522_BUF_OVFL_ERR (1 << 4) /* FIFO is full and the host or internal state machine try to write data */ +#define MFRC522_TEMP_ERR (1 << 6) /* internal temperature sensor detects overheating */ +#define MFRC522_WR_ERR (1 << 7) /* data write error in the FIFO, host writing to FIFO at the wrong time */ + +/* Section 9.3.1.8: Status1Reg register */ + +#define MFRC522_LO_ALERT (1 << 0) /* number of bytes on FIFO lower than the water-mark */ +#define MFRC522_HI_ALERT (1 << 1) /* number of bytes on FIFO higher than the water-mark */ +#define MFRC522_TRUNNING (1 << 3) /* timer is running */ +#define MFRC522_IRQ (1 << 4) /* indicates if any interrupt source requests attention */ +#define MFRC522_CRC_READY (1 << 5) /* the CRC calculation has finished */ +#define MFRC522_CRC_OK (1 << 6) /* when the calculation is done correctly this bit change to 1 */ + +/* Section 9.3.1.9: Status2Reg register */ + +#define MFRC522_MODEM_STATE_MASK (7 << 0) /* shows the state of the transmitter and receiver state machine */ +#define MFRC522_MODEM_IDLE (0) /* idle */ +#define MFRC522_MODEM_WAIT_BFR (1) /* wait for the BitFramingReg register’s StartSend bit */ +#define MFRC522_MODEM_TXWAIT (2) /* wait until RF field is present if TxWaitRF bit is set to 1 */ +#define MFRC522_MODEM_TXING (3) /* transmitting */ +#define MFRC522_MODEM_RXWAIT (4) /* wait until RF field is present if TxWaitRF bit is set to 1 */ +#define MFRC522_MODEM_WAIT_DATA (5) /* wait for data */ +#define MFRC522_MODEM_RXING (6) /* receiving */ +#define MFRC522_MF_CRYPTO1_ON (1 << 3) /* MIFARE Crypto1 unit is switched on */ +#define MFRC522_I2C_FORCE_HS (1 << 6) /* set the I2C to high-speed mode (R/W bit) */ +#define MFRC522_TEMP_SENS_CLEAR (1 << 7) /* clears the temperature error if it is below 125C (R/W bit) */ + +/* Section 9.3.1.10: FIFODataReg register */ + +#define MFRC522_FIFO_DATA_MASK (0xFF) /* Input and output of 64 byte FIFO buffer */ + +/* Section 9.3.1.11: FIFOLevelReg register */ + +#define MFRC522_FIFOLEVEL_MASK (0x7F) /* indicates the number of bytes stored in the FIFO buffer */ +#define MFRC522_FLUSH_BUFFER (1 << 7) /* immediately clears the internal FIFO buffer */ + +/* Section 9.3.1.12: WaterLevelReg register */ + +#define MFRC522_WATER_LEVEL_MASK (0x3F) /* level for FIFO under- and overflow warning */ + +/* Section 9.3.1.13: ControlReg register */ + +#define MFRC522_RX_LAST_BITS_MASK (7 << 0) /* indicates the number of valid bits in the last received byte */ +#define MFRC522_TSTART_NOW (1 << 6) /* timer starts immediately */ +#define MFRC522_TSTOP_NOW (1 << 7) /* timer stops immediately */ + +/* Section 9.3.1.14: BitFramingReg register */ + +#define MFRC522_TX_LAST_BITS_MASK (7 << 0) /* defines the number of bits of the last byte that will be transmitted */ +#define MFRC522_RX_ALIGN_MASK (7 << 4) /* used for reception of bit-oriented frames */ +#define MFRC522_START_SEND (1 << 7) /* starts the transmission of data */ + +/* Section 9.3.1.15: CollReg register */ + +#define MFRC522_COLL_POS_MASK (0x1F) /* shows the bit position of the first detected collision */ +#define MFRC522_COLL_POS_NOT_VALID (1 << 5) /* no collision detected or it is out of the range of CollPos[4:0] */ +#define MFRC522_VALUES_AFTER_COLL (1 << 7) /* 0 means: all received bits will be cleared after a collision */ + +/* Section 9.3.2.2: ModeReg register */ + +#define MFRC522_CRC_PRESET_MASK (0x3) /* defines the preset value for the CalcCRC */ +#define MFRC522_CRC_PRESET_0000 (0x0) /* 0000h CRC preset value */ +#define MFRC522_CRC_PRESET_6363 (0x1) /* 6363h CRC preset value */ +#define MFRC522_CRC_PRESET_A671 (0x2) /* A671h CRC preset value */ +#define MFRC522_CRC_PRESET_FFFF (0x3) /* FFFFh CRC preset value */ +#define MFRC522_POL_MFIN (1 << 3) /* defines the polarity of pin MFIN */ +#define MFRC522_TX_WAIT_RF (1 << 5) /* transmitter can only be started if an RF field is generated */ +#define MFRC522_MSB_FIRST (1 << 7) /* CRC coprocessor calculates the CRC with MSB first */ + +/* Section 9.3.2.3: TxModeReg register */ + +#define MFRC522_INV_MOD (1 << 3) /* modulation of transmitted data is inverted */ +#define MFRC522_TX_SPEED_MASK (7 << 4) /* defines the bit rate during data transmission */ +#define MFRC522_TX_106KBD (0 << 4) /* 106 kBd */ +#define MFRC522_TX_212KBD (1 << 4) /* 212 kBd */ +#define MFRC522_TX_424KBD (2 << 4) /* 424 kBd */ +#define MFRC522_TX_848KBD (3 << 4) /* 848 kBd */ + /* 4-7 << 4 - reserved */ +#define MFRC522_TX_CRC_EN (1 << 7) /* enables CRC generation during data transmission */ + +/* Section 9.3.2.4: RxModeReg register */ + +#define MFRC522_RX_MULTIPLE (1 << 2) /* enable to receive more than one data frame, only at 106kBd */ +#define MFRC522_RX_NO_ERR (1 << 3) /* ignore invalid data stream error (less than 4 bits received) */ +#define MFRC522_RX_SPEED_MASK (7 << 4) /* defines the bit rate during data reception */ +#define MFRC522_RX_106KBD (0 << 4) /* 106 kBd */ +#define MFRC522_RX_212KBD (1 << 4) /* 212 kBd */ +#define MFRC522_RX_424KBD (2 << 4) /* 424 kBd */ +#define MFRC522_RX_848KBD (3 << 4) /* 848 kBd */ + /* 4-7 << 4 - reserved */ +#define MFRC522_RX_CRC_EN (1 << 7) /* enables CRC generation during data reception */ + +/* Section 9.3.2.5: TxControlReg register */ + +#define MFRC522_TX1_RF_EN (1 << 0) /* output signal on pin TX1 delivers 13.56MHz */ +#define MFRC522_TX2_RF_EN (1 << 1) /* output signal on pin TX2 delivers 13.56MHz */ + /* bit 2 - reserved */ +#define MFRC522_TX2_CW (1 << 3) /* output signal on pin TX2 delivers (un)modulated 13.56MHz */ +#define MFRC522_INV_TX1_RF_OFF (1 << 4) /* output signal on pin TX1 is inverted when driver TX1 is disabled */ +#define MFRC522_INV_TX2_RF_OFF (1 << 5) /* output signal on pin TX2 is inverted when driver TX2 is disabled */ +#define MFRC522_INV_TX1_RF_ON (1 << 6) /* output signal on pin TX1 is inverted when driver TX1 is enabled */ +#define MFRC522_INV_TX2_RF_ON (1 << 7) /* output signal on pin TX2 is inverted when driver TX2 is enabled */ + +/* Section 9.3.2.6: TxASKReg register */ + +#define MFRC522_FORCE_100ASK (1 << 6) /* forces a 100% ASK modulation independent of the ModGsPReg setting */ + +/* Section 9.3.2.7: TxSelReg register */ + +#define MFRC522_MFOUT_SEL_MASK (0xF) /* selects the input for pin MFOUT */ +#define MFRC522_MFOUT_3STATE (0) /* 3-state */ +#define MFRC522_MFOUT_LOW (1) /* constant Low */ +#define MFRC522_MFOUT_HIGH (2) /* constant High */ +#define MFRC522_MFOUT_TEST_BUS (3) /* test bus signal as defined by the TstBusBitSel[2:0] value */ +#define MFRC522_MFOUT_INT_ENV (4) /* modulation signal (envelope) from the internal encoder */ +#define MFRC522_MFOUT_TX_STREAM (5) /* serial data stream to be transmitted, data stream before Miller encoder */ + /* 6 - reserved */ +#define MFRC522_MFOUT_RX_STREAM (7) /* serial data stream received, data stream after Manchester decoder */ + /* 8-15 - reserved */ +#define MFRC522_DRV_SEL_MASK (3 << 4) /* selects the input of drivers TX1 and TX2 */ +#define MFRC522_DRV_SEL_3STATE (0 << 4) /* 3-state */ +#define MFRC522_DRV_SEL_INT_ENV (1 << 4) /* modulation signal (envelope) from the internal encoder */ +#define MFRC522_DVR_SEL_ENV_MFIN (2 << 4) /* modulation signal (envelope) from pin MFIN */ +#define MFRC522_DVR_SEL_HIGH (3 << 4) /* High: depends on InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff */ + +/* Section 9.3.2.8: RxSelReg register */ + +#define MFRC522_RX_WAIT_MASK (0x3F) /* delay the receiver RxWait bit-clocks after transmission */ +#define MFRC522_UART_SEL_MASK (3 << 6) /* selects the input of the contactless UART */ +#define MFRC522_UART_LOW (0 << 6) /* constant Low */ +#define MFRC522_UART_MANCHESTER (1 << 6) /* Manchester with subcarrier from pin MFIN */ +#define MFRC522_UART_INT_MOD (2 << 6) /* modulated signal from the internal analog module, default */ +#define MFRC522_UART_NRZ_CODE (3 << 6) /* NRZ coding without subcarrier from pin MFIN */ + +/* Section 9.3.2.9: RxThresholdReg register */ + +#define MFRC522_COLL_LEVEL_MASK (7) /* the minimum signal strength to generate a bit-collision */ +#define MFRC522_MIN_LEVEL_MASK (0xF << 4) /* the minimum signal strength that will be accepted */ + +/* Section 9.3.2.10: DemodReg register */ + +#define MFRC522_TAU_SYNC_MASK (3 << 0) /* changes the time-constant of the internal PLL during burst */ +#define MFRC522_TAU_RCV_MASK (3 << 2) /* changes the time-constant of the internal PLL during data reception */ +#define MFRC522_TPRESCAL_EVEN (1 << 4) /* defines the Timer Prescaler formula to use */ +#define MFRC522_FIX_IQ (1 << 5) /* defines if reception will be fixed at channel I or Q based on AddIQ[1:0] */ +#define MFRC522_ADD_IQ_MASK (3 << 6) /* defines the use of I and Q channel during reception */ + +/* Section 9.3.2.13: MfTxReg register */ + +#define MFRC522_MF_TX_WAIT_MASK (3 << 0) /* defines the additional response time */ + +/* Section 9.3.2.14 MfRxReg register */ + +#define MFRC522_MF_RX_PARITY_DIS (1 << 4 ) /* disable parity bit to transmittion and reception */ + +/* Section 9.3.2.16: SerialSpeedReg register */ + +#define MFRC522_BR_T1_MASK (0x1F) /* factor BR_T1 adjusts the transfer speed */ +#define MFRC522_BR_T0_MASK (7 << 5) /* factor BR_T0 adjusts the transfer speed */ + +/* Section 9.3.3.6: RFCfgReg register */ + +#define MFRC522_RX_GAIN_MASK (0x7 << 4) +#define MFRC522_RX_GAIN_18DB (0x0 << 4) +#define MFRC522_RX_GAIN_23DB (0x1 << 4) +#define MFRC522_RX_GAIN_18DB_2 (0x2 << 4) +#define MFRC522_RX_GAIN_23DB_2 (0x3 << 4) +#define MFRC522_RX_GAIN_33DB (0x4 << 4) +#define MFRC522_RX_GAIN_38DB (0x5 << 4) +#define MFRC522_RX_GAIN_43DB (0x6 << 4) +#define MFRC522_RX_GAIN_48DB (0x7 << 4) + +/* MFRC522 TModeReg and TPrescalerReg registers */ + +#define MFRC522_TPRESCALER_HI_MASK (0xF) +#define MFRC522_TAUTO_RESTART (1 << 4) +#define MFRC522_TGATED_MASK (3 << 5) +#define MFRC522_TGATED_NONGATED (0 << 5) /* non-gated mode */ +#define MFRC522_TGATED_MFIN (1 << 5) /* gated by pin MFIN */ +#define MFRC522_TGATED_AUX1 (2 << 5) /* gated by pin AUX1 */ +#define MFRC522_TAUTO (1 << 7) /* timer starts automatically at the end of the transmission */ + +/* MFRC522 AutoTestReg register */ + +#define MFRC522_SELFTEST_MASK (0xF) /* for default operation the self test must be disabled by value 0000b */ +#define MFRC522_RFT_MASK (3 << 4) /* reserved for production tests */ +#define MFRC522_AMP_RCV (1 << 6) /* non-linear signal processing mode, increase range distance at 106kBd */ + +#define MFRC522_SELFTEST_EN 9 /* the self test is enabled by value 1001b */ + +#ifndef CONFIG_MFRC522_SPI_FREQ +# define CONFIG_MFRC522_SPI_FREQ (5000000) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct mfrc522_dev_s +{ + uint8_t state; + FAR struct spi_dev_s *spi; /* SPI interface */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +bool mfrc522_set_config(struct mfrc522_dev_s *dev, uint8_t flags); + +#endif /* __DRIVERS_WIRELESS_MFRC522_H */ diff --git a/include/nuttx/wireless/mfrc522.h b/include/nuttx/wireless/mfrc522.h new file mode 100644 index 0000000000..cdb55134c1 --- /dev/null +++ b/include/nuttx/wireless/mfrc522.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * include/wireless/mfrc522.h + * + * Copyright(C) 2016 Uniquix Ltda. All rights reserved. + * Author: Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __NUTTX_WIRELESS_MFRC522_H +#define __NUTTX_WIRELESS_MFRC522_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +#define MFRC522_MIFARE_ISO14443A (0x00) + +/* IOCTL Commands ***********************************************************/ + +#define MFRC522IOC_GET_PICC_UID _WLIOC_USER(0x0001) +#define MFRC522IOC_GET_STATE _WLIOC_USER(0x0002) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum mfrc522_state_E +{ + MFRC522_STATE_NOT_INIT, + MFRC522_STATE_IDLE, + MFRC522_STATE_CMD_SENT, + MFRC522_STATE_DATA_READY, +}; + +struct mfrc522_dev_s; + +struct picc_uid_s +{ + uint8_t size; /* Number of bytes in the UID. 4, 7 or 10 */ + uint8_t uid_data[10]; + uint8_t sak; /* The SAK (Select Acknowledge) return by the PICC */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: mfrc522_register + * + * Description: + * Register the MFRC522 character device as 'devpath' + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * spi - An instance of the SPI interface to use to communicate with MFRC522 + * config - Device persistent board data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int mfrc522_register(FAR const char *devpath, FAR struct spi_dev_s *spi); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __NUTTX_WIRELESS_MFRC522_H */