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arm64: s/ARCH_BOOT_EL3/ARCH_ARM64_EXCEPTION_LEVEL/g

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Search and replace ARCH_BOOT_EL3 with more generic
ARCH_ARM64_EXCEPTION_LEVEL that holds the EL level
in an integer variable.

Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>
This commit is contained in:
Eero Nurkkala 2024-05-17 10:45:30 +03:00 committed by Xiang Xiao
parent 1d3ce6b527
commit 2f753a48c7
12 changed files with 25 additions and 25 deletions
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14
arch/arm64/Kconfig
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@ -146,14 +146,14 @@ config ARCH_HAVE_EL3
runing at EL3 is not necessary and system register for EL3
is not accessible
config ARCH_BOOT_EL3
bool "Boot in EL3"
default n
depends on ARCH_HAVE_EL3
config ARCH_ARM64_EXCEPTION_LEVEL
int "Exception level to operate"
default 1
range 1 3
---help---
If NuttX works as the primary bootloader, give option to
stay in EL3. This will prevent it to switching into EL2/EL1
levels.
Default exception level is EL1 for the NuttX OS. However,
if NuttX works as the primary bootloader, this may be set
to EL3. Other levels are not supported at the moment.
config ARCH_SET_VMPIDR_EL2
bool "Set VMPIDR_EL2 at EL2 stage"

4
arch/arm64/src/common/arm64_boot.c
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@ -78,11 +78,11 @@ void arm64_boot_el3_init(void)
reg = 0U; /* Reset */
reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */
reg |= (SCR_RES1 | /* RES1 */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
SCR_IRQ_BIT | /* Route IRQs to EL3 */
SCR_FIQ_BIT | /* Route FIQs to EL3 */
SCR_EA_BIT | /* Route EAs to EL3 */
#endif
#endif
SCR_RW_BIT | /* EL2 execution state is AArch64 */
SCR_ST_BIT | /* Do not trap EL1 accesses to timer */
SCR_HCE_BIT | /* Do not trap HVC */

2
arch/arm64/src/common/arm64_fork.c
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@ -225,7 +225,7 @@ pid_t arm64_fork(const struct fork_s *context)
pforkctx->regs[REG_X28] = context->regs[FORK_REG_X28];
pforkctx->regs[REG_X29] = newfp;
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
pforkctx->spsr = SPSR_MODE_EL3H;
#else
pforkctx->spsr = SPSR_MODE_EL1H;

2
arch/arm64/src/common/arm64_gicv3.c
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@ -792,7 +792,7 @@ uint64_t * arm64_decodefiq(uint64_t * regs)
irq = arm64_gic_get_active_fiq();
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
/* FIQ is group0 interrupt */
if (irq == PENDING_GRP1NS_INTID)

2
arch/arm64/src/common/arm64_head.S
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@ -235,7 +235,7 @@ switch_el:
bl arm64_boot_el3_init
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
msr SPSel, #1
/* Set SP_EL3 (with SPSel = 1) */

2
arch/arm64/src/common/arm64_initialstate.c
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@ -76,7 +76,7 @@ void arm64_new_task(struct tcb_s * tcb)
/* Keep using SP_EL1 or SP_EL3 */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
pinitctx->spsr = SPSR_MODE_EL3H;
#else
pinitctx->spsr = SPSR_MODE_EL1H;

10
arch/arm64/src/common/arm64_mmu.c
View File

@ -523,7 +523,7 @@ static void setup_page_tables(void)
}
}
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
static void enable_mmu_el3(unsigned int flags)
{
uint64_t value;
@ -533,7 +533,7 @@ static void enable_mmu_el3(unsigned int flags)
write_sysreg(MEMORY_ATTRIBUTES, mair_el3);
write_sysreg(get_tcr(3), tcr_el3);
write_sysreg(((uint64_t)base_xlat_table), ttbr0_el3);
write_sysreg((uint64_t)base_xlat_table, ttbr0_el3);
/* Ensure these changes are seen before MMU is enabled */
@ -566,7 +566,7 @@ static void enable_mmu_el1(unsigned int flags)
write_sysreg(MEMORY_ATTRIBUTES, mair_el1);
write_sysreg(get_tcr(1), tcr_el1);
write_sysreg(((uint64_t)base_xlat_table), ttbr0_el1);
write_sysreg((uint64_t)base_xlat_table, ttbr0_el1);
/* Ensure these changes are seen before MMU is enabled */
@ -630,7 +630,7 @@ int arm64_mmu_init(bool is_primary_core)
__asm__ volatile ("mrs %0, CurrentEL" : "=r" (el));
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
__MMU_ASSERT(GET_EL(el) == MODE_EL3,
"Exception level not EL3, MMU not enabled!\n");
@ -665,7 +665,7 @@ int arm64_mmu_init(bool is_primary_core)
/* Currently EL1 and EL3 are supported */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
enable_mmu_el3(flags);
#else
enable_mmu_el1(flags);

2
arch/arm64/src/common/arm64_schedulesigaction.c
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@ -74,7 +74,7 @@ void arm64_init_signal_process(struct tcb_s *tcb, struct regs_context *regs)
/* Keep using SP_EL1 */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
psigctx->spsr = SPSR_MODE_EL3H | DAIF_FIQ_BIT | DAIF_IRQ_BIT;
#else
psigctx->spsr = SPSR_MODE_EL1H | DAIF_FIQ_BIT | DAIF_IRQ_BIT;

4
arch/arm64/src/common/arm64_vector_table.S
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@ -69,7 +69,7 @@
stp x30, \xreg0, [sp, #8 * REG_X30]
/* ELR and SPSR */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
mrs \xreg0, elr_el3
mrs \xreg1, spsr_el3
#else
@ -251,7 +251,7 @@ arm64_exit_exc_fpu_done:
/* restore spsr and elr at el1*/
ldp x0, x1, [sp, #8 * REG_ELR]
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
msr elr_el3, x0
msr spsr_el3, x1
#else

4
arch/arm64/src/common/arm64_vectors.S
View File

@ -92,7 +92,7 @@ SECTION_FUNC(text, up_saveusercontext)
stp x30, x4, [x0, #8 * REG_X30]
/* ELR and SPSR */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
mrs x4, elr_el3
mrs x5, spsr_el3
#else
@ -186,7 +186,7 @@ GTEXT(arm64_sync_exc)
SECTION_FUNC(text, arm64_sync_exc)
/* checking the EC value to see which exception need to be handle */
#ifdef CONFIG_ARCH_BOOT_EL3
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
mrs x0, esr_el3
#else
mrs x0, esr_el1

2
arch/arm64/src/imx9/Kconfig
View File

@ -16,7 +16,7 @@ config ARCH_CHIP_IMX93
select ARCH_HAVE_MULTICPU
select ARMV8A_HAVE_GICv3
select ARCH_CORTEX_A55
select ARCH_HAVE_PSCI if !ARCH_BOOT_EL3
select ARCH_HAVE_PSCI if !IMX9_BOOTLOADER
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_RESET

2
boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig
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@ -8,9 +8,9 @@
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ARCH="arm64"
CONFIG_ARCH_ARM64=y
CONFIG_ARCH_ARM64_EXCEPTION_LEVEL=3
CONFIG_ARCH_BOARD="imx93-evk"
CONFIG_ARCH_BOARD_IMX93_EVK=y
CONFIG_ARCH_BOOT_EL3=y
CONFIG_ARCH_CHIP="imx9"
CONFIG_ARCH_CHIP_IMX93=y
CONFIG_ARCH_CHIP_IMX9=y