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rename up_led*() functions to board_led_*()

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This commit is contained in:
Gregory Nutt 2014-01-24 14:28:49 -06:00
parent 1d5b2d3d3e
commit 2f837ccd2a
256 changed files with 1969 additions and 1966 deletions
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3
ChangeLog
View File

@ -6515,4 +6515,7 @@
* Rename up_buttons() to board_buttons() for the same reason (2014-
1-14).
* Rename up_irqbutton() to board_button_irq() (2014-1-24).
* Rename up_ledinit() to board_led_intialize() (2014-1-24).
* Rename up_ledon() to board_led_on() and up_ledoff() to board_led_off()
(2014-1-24).

18
Documentation/NuttxPortingGuide.html
View File

@ -2679,13 +2679,13 @@ else
/* Defined in board/up_leds.c */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(int led);
extern void up_ledoff(int led);
extern void board_led_initialize(void);
extern void board_led_on(int led);
extern void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
</pre></ul>
<p>
@ -2693,14 +2693,14 @@ extern void up_ledoff(int led);
<p>
<ul>
<li>
<code>void up_ledinit(void)</code> is called early in power-up initialization to initialize the LED hardware.
<code>void board_led_initialize(void)</code> is called early in power-up initialization to initialize the LED hardware.
</li>
<li>
<code>up_ledon(int led)</code> is called to instantiate the LED presentation of the event.
<code>board_led_on(int led)</code> is called to instantiate the LED presentation of the event.
The <code>led</code> argument is one of the definitions provided in <code><i>&lt;board-name&gt;</i>/include/board.h</code>.
</li>
<li>
<code>up_ledoff(int led</code>is called to terminate the LED presentation of the event.
<code>board_led_off(int led</code>is called to terminate the LED presentation of the event.
The <code>led</code> argument is one of the definitions provided in <code><i>&lt;board-name&gt;</i>/include/board.h</code>.
Note that only <code>LED_INIRQ</code>, <code>LED_SIGNAL</code>, <code>LED_ASSERTION</code>, and <code>LED_PANIC</code>
indications are terminated.

2
arch/8051/src/up_allocateheap.c
View File

@ -79,7 +79,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
*heap_start = (FAR void*)UP_HEAP1_BASE;
*heap_size = UP_HEAP1_END - UP_HEAP1_BASE;
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
}
#if CONFIG_MM_REGIONS > 1

6
arch/8051/src/up_assert.c
View File

@ -76,9 +76,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_delay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_delay(250);
#endif
}
@ -103,7 +103,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed at file:%s line: %d task: %s\n",

6
arch/8051/src/up_head.S
View File

@ -137,7 +137,7 @@ start:
mov sp, #(STACK_BASE-1)
#ifdef CONFIG_ARCH_LEDS
lcall _up_ledinit
lcall _board_led_initialize
#endif
ljmp _os_start
@ -251,7 +251,7 @@ _up_timer0join:
#ifdef CONFIG_ARCH_LEDS
mov dpl, #LED_INIRQ
lcall _up_ledon
lcall _board_led_on
#endif
/* Save the IRQ number in r2 */
@ -443,7 +443,7 @@ _up_timer0join:
push dpl
push dph
mov dpl, #LED_INIRQ
lcall _up_ledoff
lcall _board_led_off
pop dph
pop dpl
#endif

4
arch/8051/src/up_idle.c
View File

@ -85,11 +85,11 @@ void up_idle(void)
g_ledtoggle++;
if (g_ledtoggle == 0x80)
{
up_ledon(LED_IDLE);
board_led_on(LED_IDLE);
}
else if (g_ledtoggle == 0x00)
{
up_ledoff(LED_IDLE);
board_led_off(LED_IDLE);
}
#endif
}

2
arch/8051/src/up_initialize.c
View File

@ -139,6 +139,6 @@ void up_initialize(void)
up_timerinit();
#endif
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

12
arch/8051/src/up_internal.h
View File

@ -139,13 +139,13 @@ extern void up_dumpframe(FAR struct xcptcontext *context);
/* Defined in board/up_leds.c */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(uint8_t led);
extern void up_ledoff(uint8_t led);
extern void board_led_initialize(void);
extern void board_led_on(uint8_t led);
extern void board_led_off(uint8_t led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
#endif /* __ASSEMBLY */

8
arch/8051/src/up_irqtest.c
View File

@ -251,23 +251,23 @@ void up_dumpframe(FAR struct xcptcontext *context)
}
/************************************************************************
* Name: up_ledinit, up_ledon, up_ledoff
* Name: board_led_initialize, board_led_on, board_led_off
*
* Description:
* "Fake" LED routines if needed
*
************************************************************************/
void up_ledinit(void)
void board_led_initialize(void)
{
}
void up_ledon(uint8_t led)
void board_led_on(uint8_t led)
{
led;
}
void up_ledoff(uint8_t led)
void board_led_off(uint8_t led)
{
led;
}

6
arch/arm/src/arm/up_assert.c
View File

@ -263,9 +263,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -290,7 +290,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/arm/up_doirq.c
View File

@ -72,7 +72,7 @@
void up_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -112,5 +112,5 @@ void up_doirq(int irq, uint32_t *regs)
up_enable_irq(irq);
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
}

2
arch/arm/src/arm/up_nommuhead.S
View File

@ -125,7 +125,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl up_ledinit
bl board_led_initialize
#endif
#ifdef CONFIG_DEBUG_STACK

4
arch/arm/src/arm/up_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -131,7 +131,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv6-m/up_assert.c
View File

@ -279,9 +279,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -306,7 +306,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv6-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv6-m/up_sigdeliver.c
View File

@ -97,7 +97,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -139,7 +139,7 @@ void up_sigdeliver(void)
* execution.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv7-a/arm_assert.c
View File

@ -273,9 +273,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -299,7 +299,7 @@ void up_assert(const uint8_t *filename, int lineno)
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-a/arm_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -121,6 +121,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
up_enable_irq(irq);
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv7-a/arm_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -131,7 +131,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv7-m/up_assert.c
View File

@ -290,9 +290,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -317,7 +317,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv7-m/up_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -142,7 +142,7 @@ void up_sigdeliver(void)
* execution.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

4
arch/arm/src/common/up_allocateheap.c
View File

@ -118,14 +118,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

2
arch/arm/src/common/up_createstack.c
View File

@ -226,7 +226,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
#endif
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

2
arch/arm/src/common/up_initialize.c
View File

@ -207,5 +207,5 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

12
arch/arm/src/common/up_internal.h
View File

@ -456,13 +456,13 @@ void up_wdtinit(void);
/* LED interfaces provided by board-level logic *****************************/
#ifdef CONFIG_ARCH_LEDS
void up_ledinit(void);
void up_ledon(int led);
void up_ledoff(int led);
void board_led_initialize(void);
void board_led_on(int led);
void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
/* Networking ***************************************************************/

2
arch/arm/src/dm320/dm320_allocateheap.c
View File

@ -84,7 +84,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack;
}

2
arch/arm/src/dm320/dm320_boot.c
View File

@ -227,7 +227,7 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
up_ledinit();
board_led_initialize();
#endif
/* Perform early serial initialization */

4
arch/arm/src/efm32/efm32_idle.c
View File

@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

2
arch/arm/src/imx/imx_allocateheap.c
View File

@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack;
}

2
arch/arm/src/imx/imx_boot.c
View File

@ -215,7 +215,7 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
up_ledinit();
board_led_initialize();
#endif
/* Perform early serial initialization */

4
arch/arm/src/kinetis/kinetis_allocateheap.c
View File

@ -130,7 +130,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
@ -141,7 +141,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/kinetis/kinetis_idle.c
View File

@ -52,8 +52,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/kl/kl_idle.c
View File

@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/lm/lm_allocateheap.c
View File

@ -130,7 +130,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
@ -141,7 +141,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/lpc17xx/lpc17_allocateheap.c
View File

@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
@ -251,7 +251,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/lpc17xx/lpc17_idle.c
View File

@ -54,8 +54,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

2
arch/arm/src/lpc214x/lpc214x_head.S
View File

@ -592,7 +592,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl up_ledinit
bl board_led_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc2378/lpc23xx_head.S
View File

@ -192,7 +192,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl up_ledinit
bl board_led_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc31xx/lpc31_allocateheap.c
View File

@ -179,7 +179,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = LPC31_HEAP_VEND - g_idle_topstack;
}

2
arch/arm/src/lpc43xx/lpc43_allocateheap.c
View File

@ -247,7 +247,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* Start with the first SRAM region */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

4
arch/arm/src/lpc43xx/lpc43_idle.c
View File

@ -56,8 +56,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/nuc1xx/nuc_idle.c
View File

@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/sam34/sam_allocateheap.c
View File

@ -229,7 +229,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/sama5/sam_allocateheap.c
View File

@ -213,14 +213,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_VEND - g_idle_topstack;
#endif

4
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -474,7 +474,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_size = usize;
@ -489,7 +489,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;

4
arch/arm/src/stm32/stm32_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() up_ledon(LED_IDLE)
# define END_IDLE() up_ledoff(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

6
arch/arm/src/str71x/str71x_decodeirq.c
View File

@ -90,7 +90,7 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
lowsyslog("Unexpected IRQ\n");
current_regs = regs;
PANIC();
@ -101,7 +101,7 @@ void up_decodeirq(uint32_t *regs)
* info from CIC register without the setup).
*/
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
irq = getreg32(STR71X_EIC_IVR);
/* Verify that the resulting IRQ number is valid */
@ -142,6 +142,6 @@ void up_decodeirq(uint32_t *regs)
PANIC(); /* Normally never happens */
}
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
#endif
}

4
arch/arm/src/str71x/str71x_head.S
View File

@ -65,7 +65,7 @@
.globl up_earlyserialinit /* Early initialization of serial driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl up_ledinit /* Boot LED setup */
.globl board_led_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG
.globl up_lowputc /* Low-level debug output */
@ -570,7 +570,7 @@ ctor_end:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl up_ledinit
bl board_led_initialize
#endif
/* Then jump to OS entry */

2
arch/avr/src/avr/up_createstack.c
View File

@ -186,7 +186,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR void *)top_of_stack;
tcb->adj_stack_size = stack_size;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/avr/src/avr/up_doirq.c
View File

@ -72,7 +72,7 @@
uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -112,7 +112,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
current_regs = savestate;
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/avr/src/avr/up_sigdeliver.c
View File

@ -91,7 +91,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -146,7 +146,7 @@ void up_sigdeliver(void)
* to the size of register save structure size will protect its contents.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

2
arch/avr/src/avr32/up_createstack.c
View File

@ -193,7 +193,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR void *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/avr/src/avr32/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -112,7 +112,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/avr/src/avr32/up_sigdeliver.c
View File

@ -95,7 +95,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -149,7 +149,7 @@ void up_sigdeliver(void)
* to the size of register save structure size will protect its contents.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

2
arch/avr/src/common/up_allocateheap.c
View File

@ -81,7 +81,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/avr/src/common/up_assert.c
View File

@ -101,9 +101,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -128,7 +128,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/avr/src/common/up_initialize.c
View File

@ -237,6 +237,6 @@ void up_initialize(void)
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

8
arch/avr/src/common/up_internal.h
View File

@ -179,11 +179,11 @@ extern void up_timerinit(void);
/* Defined in configs/<board-name>/src/up_leds.c */
#ifdef CONFIG_ARCH_LEDS
void up_ledon(int led);
void up_ledoff(int led);
void board_led_on(int led);
void board_led_off(int led);
#else
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_on(led)
# define board_led_off(led)
#endif
/* Defined in chip/xxx_ethernet.c */

2
arch/hc/src/common/up_allocateheap.c
View File

@ -80,7 +80,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

2
arch/hc/src/common/up_createstack.c
View File

@ -192,7 +192,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/hc/src/common/up_doirq.c
View File

@ -72,7 +72,7 @@
uint8_t *up_doirq(int irq, uint8_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -112,6 +112,6 @@ uint8_t *up_doirq(int irq, uint8_t *regs)
current_regs = savestate;
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

2
arch/hc/src/common/up_initialize.c
View File

@ -190,5 +190,5 @@ void up_initialize(void)
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

12
arch/hc/src/common/up_internal.h
View File

@ -237,13 +237,13 @@ extern void up_usbuninitialize(void);
/* Board-specific functions */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(int led);
extern void up_ledoff(int led);
extern void board_led_initialize(void);
extern void board_led_on(int led);
extern void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
#endif /* __ASSEMBLY__ */

6
arch/hc/src/m9s12/m9s12_assert.c
View File

@ -258,9 +258,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -285,7 +285,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

792
arch/mips/include/pic32mx/cp0.h
View File

@ -1,396 +1,396 @@
/****************************************************************************
* arch/mips/include/pic32mx/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/mips32/cp0.h>
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
# define PIC32MX_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */
# define PIC32MX_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define PIC32MX_CP0_COUNT $9,0 /* Processor cycle count */
# define PIC32MX_CP0_COMPARE $11,0 /* Timer interrupt control */
# define PIC32MX_CP0_STATUS $12,0 /* Processor status and control */
# define PIC32MX_CP0_INTCTL $12,1 /* Interrupt system status and control */
# define PIC32MX_CP0_SRSCTL $12,2 /* Shadow register set status and control */
# define PIC32MX_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */
# define PIC32MX_CP0_CAUSE $13,0 /* Cause of last general exception */
# define PIC32MX_CP0_EPC $14,0 /* Program counter at last exception */
# define PIC32MX_CP0_PRID $15,0 /* Processor identification and revision */
# define PIC32MX_CP0_EBASE $15,1 /* Exception vector base register */
# define PIC32MX_CP0_CONFIG $16,0 /* Configuration register */
# define PIC32MX_CP0_CONFIG1 $16,1 /* Configuration register 1 */
# define PIC32MX_CP0_CONFIG2 $16,2 /* Configuration register 3 */
# define PIC32MX_CP0_CONFIG3 $16,3 /* Configuration register 3 */
# define PIC32MX_CP0_DEBUG $23,3 /* Debug control and exception status */
# define PIC32MX_CP0_DEPC $24,3 /* Program counter at last debug exception */
# define PIC32MX_CP0_ERREPC $30,3 /* Program counter at last error */
# define PIC32MX_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ************************************************************/
/* Register Number: 0-6: Reserved
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*/
/* Register Number: 7 Sel: 0 Name: HWREna
* Function: Enables access via the RDHWR instruction to selected hardware
* registers in non-privileged mode.
* Compliance Level: (Reserved for future extensions)
*/
#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */
#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT)
/* Register Number: 8 Sel: 0 Name: BadVAddr
* Function: Reports the address for the most recent address-related
* exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 9 Sel: 0 Name: Count
* Function: Processor cycle count
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 10 Reserved.
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*
* Register Number: 11 Sel: 0 Name: Compare
* Function: Timer interrupt control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 12 Sel: 0 Name: Status
* Function: Processor status and control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES:
* 1. The following are reserved bits in the PIC32:
* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
*/
#undef CP0_STATUS_UX
#undef CP0_STATUS_SX
#undef CP0_STATUS_KX
#undef CP0_STATUS_IMPL
#undef CP0_STATUS_IMPL_SHIFT
#undef CP0_STATUS_IMPL_MASK
#undef CP0_STATUS_TS
#undef CP0_STATUS_PX
#undef CP0_STATUS_MX
/* 2. The following field is of a different width. Apparently, it
* excludes the software interrupt bits.
*
* CP0_STATUS_IM Bits 8-15: Interrupt Mask
* Vs.
* CP0_STATUS_IPL Bits 10-15: Interrupt priority level
* Bitss 8-9 reserved
*/
#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */
#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT)
/* 3. Supervisor mode not supported
* CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode)
*/
#undef CP0_STATUS_KSU_SHIFT
#undef CP0_STATUS_KSU_MASK
#undef CP0_STATUS_KSU_KERNEL
#undef CP0_STATUS_KSU_SUPER
#undef CP0_STATUS_KSU_USER
/* Register Number: 12 Sel: 1 Name: IntCtl */
#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
/* Register Number: 12 Sel: 2 Name: SRSCtl */
#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */
#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT)
#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */
#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT)
#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */
#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT)
#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */
#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT)
#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */
#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT)
# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */
# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */
# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */
/* Register Number: 12 Sel: 3 Name: SRSMap */
#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */
#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT)
#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */
#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT)
#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */
#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT)
#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */
#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT)
#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */
#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT)
#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */
#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT)
#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */
#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT)
#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */
#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT)
/* Register Number: 13 Sel: 0 Name: Cause
* Function: Cause of last general exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES: The following bits are added in the PIC32:
*/
#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
/* Register Number: 14 Sel: 0 Name: EPC
* Function: Program counter at last exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 15 Sel: 0 Name: PRId
* Function: Processor identification and revision
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTE: Slightly different bit interpretations of some fields:
*/
#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */
#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT)
#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */
#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT)
#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */
#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT)
#undef CP0_PRID_OPTIONS_SHIFT
#undef CP0_PRID_OPTIONS_MASK
/* Register Number: 15 Sel: 1 Name: EBASE */
#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */
#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT)
#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */
#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT)
/* Register Number: 16 Sel: 0 Name: Config
* Function: Configuration register
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* 1. PIC32MX is always little-endian.
* 2. Implementation specific bits defined.
*/
#undef CP0_CONFIG_IMPL_SHIFT
#undef CP0_CONFIG_IMPL_MASK
#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */
#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT)
#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */
#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT)
#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */
#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */
/* Register Number: 16 Sel: 1 Name: Config1
* Function: Configuration register 1
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 16 Sel: 2 Name: Config2
* Function: Configuration register 2
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#undef CP0_CONFIG2_TBS_SHIFT
#undef CP0_CONFIG2_TBS_MASK
/* Register Number: 16 Sel: 3 Name: Config3
* Function: Configuration register 3
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
/* Register Number: 17-22 Reserved
* Compliance Level: Optional.
*/
/* Register Number: 23 Sel: 0 Name: Debug
* Function: EJTAG Debug register
* Compliance Level: Optional.
*/
#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */
#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */
#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */
#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */
#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */
#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */
#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */
#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */
#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */
#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT)
#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */
#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT)
#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */
#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */
#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */
#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */
#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */
#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */
#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */
#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */
#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */
#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */
#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */
#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */
#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */
#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */
/* Register Number: 23 Sel: ? Name: Debug2
* Is this documented anywhere?
*/
/* Register Number: 24 Sel: 0 Name: DEPC
* Function: Program counter at last EJTAG debug exception
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 25-29 Reserved
* Compliance Level: Recommended/Optional.
*
* Register Number: 30 Sel: 0 Name: ErrorEPC
* Function: Program counter at last error
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 31 Sel: 0 Name: DeSAVE
* Function: EJTAG debug exception save register
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */
/****************************************************************************
* arch/mips/include/pic32mx/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/mips32/cp0.h>
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* CP0 Register Addresses ***************************************************/
#ifdef __ASSEMBLY__
# define PIC32MX_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */
# define PIC32MX_CP0_BADVADDR $8,0 /* Address of most recent exception */
# define PIC32MX_CP0_COUNT $9,0 /* Processor cycle count */
# define PIC32MX_CP0_COMPARE $11,0 /* Timer interrupt control */
# define PIC32MX_CP0_STATUS $12,0 /* Processor status and control */
# define PIC32MX_CP0_INTCTL $12,1 /* Interrupt system status and control */
# define PIC32MX_CP0_SRSCTL $12,2 /* Shadow register set status and control */
# define PIC32MX_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */
# define PIC32MX_CP0_CAUSE $13,0 /* Cause of last general exception */
# define PIC32MX_CP0_EPC $14,0 /* Program counter at last exception */
# define PIC32MX_CP0_PRID $15,0 /* Processor identification and revision */
# define PIC32MX_CP0_EBASE $15,1 /* Exception vector base register */
# define PIC32MX_CP0_CONFIG $16,0 /* Configuration register */
# define PIC32MX_CP0_CONFIG1 $16,1 /* Configuration register 1 */
# define PIC32MX_CP0_CONFIG2 $16,2 /* Configuration register 3 */
# define PIC32MX_CP0_CONFIG3 $16,3 /* Configuration register 3 */
# define PIC32MX_CP0_DEBUG $23,3 /* Debug control and exception status */
# define PIC32MX_CP0_DEPC $24,3 /* Program counter at last debug exception */
# define PIC32MX_CP0_ERREPC $30,3 /* Program counter at last error */
# define PIC32MX_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ************************************************************/
/* Register Number: 0-6: Reserved
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*/
/* Register Number: 7 Sel: 0 Name: HWREna
* Function: Enables access via the RDHWR instruction to selected hardware
* registers in non-privileged mode.
* Compliance Level: (Reserved for future extensions)
*/
#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */
#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT)
# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT)
/* Register Number: 8 Sel: 0 Name: BadVAddr
* Function: Reports the address for the most recent address-related
* exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 9 Sel: 0 Name: Count
* Function: Processor cycle count
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 10 Reserved.
* Compliance Level: Required for TLB-based MMU; Optional otherwise.
*
* Register Number: 11 Sel: 0 Name: Compare
* Function: Timer interrupt control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 12 Sel: 0 Name: Status
* Function: Processor status and control
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES:
* 1. The following are reserved bits in the PIC32:
* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
*/
#undef CP0_STATUS_UX
#undef CP0_STATUS_SX
#undef CP0_STATUS_KX
#undef CP0_STATUS_IMPL
#undef CP0_STATUS_IMPL_SHIFT
#undef CP0_STATUS_IMPL_MASK
#undef CP0_STATUS_TS
#undef CP0_STATUS_PX
#undef CP0_STATUS_MX
/* 2. The following field is of a different width. Apparently, it
* excludes the software interrupt bits.
*
* CP0_STATUS_IM Bits 8-15: Interrupt Mask
* Vs.
* CP0_STATUS_IPL Bits 10-15: Interrupt priority level
* Bitss 8-9 reserved
*/
#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */
#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT)
/* 3. Supervisor mode not supported
* CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode)
*/
#undef CP0_STATUS_KSU_SHIFT
#undef CP0_STATUS_KSU_MASK
#undef CP0_STATUS_KSU_KERNEL
#undef CP0_STATUS_KSU_SUPER
#undef CP0_STATUS_KSU_USER
/* Register Number: 12 Sel: 1 Name: IntCtl */
#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
/* Register Number: 12 Sel: 2 Name: SRSCtl */
#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */
#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT)
#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */
#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT)
#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */
#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT)
#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */
#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT)
#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */
#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT)
# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */
# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */
# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */
/* Register Number: 12 Sel: 3 Name: SRSMap */
#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */
#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT)
#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */
#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT)
#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */
#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT)
#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */
#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT)
#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */
#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT)
#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */
#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT)
#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */
#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT)
#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */
#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT)
/* Register Number: 13 Sel: 0 Name: Cause
* Function: Cause of last general exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTES: The following bits are added in the PIC32:
*/
#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
/* Register Number: 14 Sel: 0 Name: EPC
* Function: Program counter at last exception
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*/
/* Register Number: 15 Sel: 0 Name: PRId
* Function: Processor identification and revision
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* NOTE: Slightly different bit interpretations of some fields:
*/
#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */
#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT)
#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */
#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT)
#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */
#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT)
#undef CP0_PRID_OPTIONS_SHIFT
#undef CP0_PRID_OPTIONS_MASK
/* Register Number: 15 Sel: 1 Name: EBASE */
#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */
#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT)
#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */
#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT)
/* Register Number: 16 Sel: 0 Name: Config
* Function: Configuration register
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
* 1. PIC32MX is always little-endian.
* 2. Implementation specific bits defined.
*/
#undef CP0_CONFIG_IMPL_SHIFT
#undef CP0_CONFIG_IMPL_MASK
#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */
#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT)
# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT)
#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */
#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT)
# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT)
#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */
#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */
/* Register Number: 16 Sel: 1 Name: Config1
* Function: Configuration register 1
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 16 Sel: 2 Name: Config2
* Function: Configuration register 2
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#undef CP0_CONFIG2_TBS_SHIFT
#undef CP0_CONFIG2_TBS_MASK
/* Register Number: 16 Sel: 3 Name: Config3
* Function: Configuration register 3
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
/* Register Number: 17-22 Reserved
* Compliance Level: Optional.
*/
/* Register Number: 23 Sel: 0 Name: Debug
* Function: EJTAG Debug register
* Compliance Level: Optional.
*/
#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */
#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */
#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */
#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */
#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */
#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */
#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */
#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */
#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */
#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT)
#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */
#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT)
#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */
#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */
#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */
#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */
#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */
#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */
#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */
#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */
#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */
#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */
#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */
#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */
#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */
#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */
/* Register Number: 23 Sel: ? Name: Debug2
* Is this documented anywhere?
*/
/* Register Number: 24 Sel: 0 Name: DEPC
* Function: Program counter at last EJTAG debug exception
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 25-29 Reserved
* Compliance Level: Recommended/Optional.
*
* Register Number: 30 Sel: 0 Name: ErrorEPC
* Function: Program counter at last error
* Compliance Level: Required.
*
* See arch/mips/include/mips32/cp0.h
*
* Register Number: 31 Sel: 0 Name: DeSAVE
* Function: EJTAG debug exception save register
* Compliance Level: Optional.
*
* See arch/mips/include/mips32/cp0.h
*/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */

2
arch/mips/src/common/up_allocateheap.c
View File

@ -81,7 +81,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

2
arch/mips/src/common/up_createstack.c
View File

@ -213,7 +213,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

2
arch/mips/src/common/up_initialize.c
View File

@ -191,5 +191,5 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

10
arch/mips/src/common/up_internal.h
View File

@ -290,12 +290,12 @@ extern void up_usbuninitialize(void);
/* LEDs */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledon(int led);
extern void up_ledoff(int led);
extern void board_led_on(int led);
extern void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
#endif /* __ASSEMBLY__ */

6
arch/mips/src/mips32/up_assert.c
View File

@ -101,9 +101,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -128,7 +128,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/mips/src/mips32/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -122,6 +122,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
up_enable_irq(irq);
#endif
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return regs;
}

4
arch/mips/src/mips32/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -135,7 +135,7 @@ void up_sigdeliver(void)
* execution.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
/* up_fullcontextrestore() should not return but could if the software

226
arch/mips/src/pic32mx/pic32mx-cvr.h
View File

@ -1,113 +1,113 @@
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-cvr.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_CVR_CON_OFFSET 0x0000 /* Comparator voltage reference control register */
#define PIC32MX_CVR_CONCLR_OFFSET 0x0004 /* Comparator voltage reference control clear register */
#define PIC32MX_CVR_CONSET_OFFSET 0x0008 /* Comparator voltage reference control set register */
#define PIC32MX_CVR_CONINV_OFFSET 0x000c /* Comparator voltage reference control invert register */
/* Register Addresses ***************************************************************/
#define PIC32MX_CVR_CON (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CON_OFFSET)
#define PIC32MX_CVR_CONCLR (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONCLR_OFFSET)
#define PIC32MX_CVR_CONSET (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONSET_OFFSET)
#define PIC32MX_CVR_CONINV (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Comparator voltage reference control register */
#define CVR_CON_CVR_SHIFT (0) /* Bits 0-3: CVREF value selection */
#define CVR_CON_CVR_MASK (15 << CVR_CON_CVR_SHIFT)
# define CVR_CON_CVR(n) ((n) << CVR_CON_CVR_SHIFT)
#define CVR_CON_CVRSS (1 << 4) /* Bit 4: CVREF source selection */
#define CVR_CON_CVRR (1 << 5) /* Bit 5: CVREF range selection */
#define CVR_CON_CVROE (1 << 6) /* Bit 6: CVREFOUT enable */
#ifdef CHIP_VRFSEL
# define CVR_CON_BGSEL_SHIFT (8) /* Bits 8-9: Band gap reference source */
# define CVR_CON_BGSEL_MASK (3 << CVR_CON_CVR_SHIFT)
# define CVR_CON_BGSEL_1p2V (0 << CVR_CON_CVR_SHIFT) /* IVREF = 1.2V (nominal) */
# define CVR_CON_BGSEL_0p6V (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
# define CVR_CON_BGSEL_0p2V (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
# define CVR_CON_BGSEL_VREF (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
# define CVR_CON_VREFSEL (1 << 10) /* Bit 10: Voltage reference select */
#endif
#define CVR_CON_ON (1 << 15) /* Bit 15: Comparator voltage reference on */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H */
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-cvr.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_CVR_CON_OFFSET 0x0000 /* Comparator voltage reference control register */
#define PIC32MX_CVR_CONCLR_OFFSET 0x0004 /* Comparator voltage reference control clear register */
#define PIC32MX_CVR_CONSET_OFFSET 0x0008 /* Comparator voltage reference control set register */
#define PIC32MX_CVR_CONINV_OFFSET 0x000c /* Comparator voltage reference control invert register */
/* Register Addresses ***************************************************************/
#define PIC32MX_CVR_CON (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CON_OFFSET)
#define PIC32MX_CVR_CONCLR (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONCLR_OFFSET)
#define PIC32MX_CVR_CONSET (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONSET_OFFSET)
#define PIC32MX_CVR_CONINV (PIC32MX_CVR_K1BASE+PIC32MX_CVR_CONINV_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Comparator voltage reference control register */
#define CVR_CON_CVR_SHIFT (0) /* Bits 0-3: CVREF value selection */
#define CVR_CON_CVR_MASK (15 << CVR_CON_CVR_SHIFT)
# define CVR_CON_CVR(n) ((n) << CVR_CON_CVR_SHIFT)
#define CVR_CON_CVRSS (1 << 4) /* Bit 4: CVREF source selection */
#define CVR_CON_CVRR (1 << 5) /* Bit 5: CVREF range selection */
#define CVR_CON_CVROE (1 << 6) /* Bit 6: CVREFOUT enable */
#ifdef CHIP_VRFSEL
# define CVR_CON_BGSEL_SHIFT (8) /* Bits 8-9: Band gap reference source */
# define CVR_CON_BGSEL_MASK (3 << CVR_CON_CVR_SHIFT)
# define CVR_CON_BGSEL_1p2V (0 << CVR_CON_CVR_SHIFT) /* IVREF = 1.2V (nominal) */
# define CVR_CON_BGSEL_0p6V (1 << CVR_CON_CVR_SHIFT) /* IVREF = 0.6V (nominal) */
# define CVR_CON_BGSEL_0p2V (2 << CVR_CON_CVR_SHIFT) /* IVREF = 0.2V (nominal) */
# define CVR_CON_BGSEL_VREF (3 << CVR_CON_CVR_SHIFT) /* VREF = VREF+ */
# define CVR_CON_VREFSEL (1 << 10) /* Bit 10: Voltage reference select */
#endif
#define CVR_CON_ON (1 << 15) /* Bit 15: Comparator voltage reference on */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CVR_H */

6
arch/mips/src/pic32mx/pic32mx-decodeirq.c
View File

@ -95,7 +95,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
* processing an interrupt.
*/
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
/* Save the current value of current_regs (to support nested interrupt
* handling). Then set current_regs to regs, indicating that this is
@ -161,11 +161,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
current_regs = savestate;
if (current_regs == NULL)
{
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
}
#else
current_regs = NULL;
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
#endif
return regs;

2
arch/mips/src/pic32mx/pic32mx-exception.c
View File

@ -94,7 +94,7 @@ uint32_t *pic32mx_exception(uint32_t *regs)
* processing an interrupt.
*/
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_DEBUG
/* Get the cause of the exception from the CAUSE register */

332
arch/mips/src/pic32mx/pic32mx-ic.h
View File

@ -1,166 +1,166 @@
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-ic.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NIC > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
#define PIC32MX_IC_CONSET_OFFSET 0x0008 /* Input Capture X Control Clear Register */
#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
/* Register Addresses ***************************************************************/
#define PIC32MX_IC_CON(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CON_OFFSET)
#define PIC32MX_IC_CONCLR(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONCLR_OFFSET)
#define PIC32MX_IC_CONSET(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONSET_OFFSET)
#define PIC32MX_IC_CONINV(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONINV_OFFSET)
#define PIC32MX_IC_BUF(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_BUF_OFFSET)
#define PIC32MX_IC1_CON (PIC32MX_IC1_K1BASE+PIC32MX_IC_CON_OFFSET)
#define PIC32MX_IC1_CONCLR (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
#define PIC32MX_IC1_CONSET (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONSET_OFFSET)
#define PIC32MX_IC1_CONINV (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONINV_OFFSET)
#define PIC32MX_IC1_BUF (PIC32MX_IC1_K1BASE+PIC32MX_IC_BUF_OFFSET)
#if CHIP_NIC > 1
# define PIC32MX_IC2_CON (PIC32MX_IC2_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC2_CONCLR (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC2_CONSET (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC2_CONINV (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC2_BUF (PIC32MX_IC2_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 2
# define PIC32MX_IC3_CON (PIC32MX_IC3_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC3_CONCLR (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC3_CONSET (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC3_CONINV (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC3_BUF (PIC32MX_IC3_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 3
# define PIC32MX_IC4_CON (PIC32MX_IC4_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC4_CONCLR (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC4_CONSET (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC4_CONINV (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC4_BUF (PIC32MX_IC4_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 4
# define PIC32MX_IC5_CON (PIC32MX_IC5_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC5_CONCLR (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC5_CONSET (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC5_CONINV (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC5_BUF (PIC32MX_IC5_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Input Capture X Control Register */
#define IC_CON_ICM_SHIFT (0) /* Bits 0-2: Input Capture Mode Select */
#define IC_CON_ICM_MASK (7 << IC_CON_ICM_SHIFT)
# define IC_CON_ICM_DISABLE (0 << IC_CON_ICM_SHIFT) /* Capture disable mode */
# define IC_CON_ICM_EDGE (1 << IC_CON_ICM_SHIFT) /* Edge detect mode */
# define IC_CON_ICM_FALLING (2 << IC_CON_ICM_SHIFT) /* Every falling edge */
# define IC_CON_ICM_RISING (3 << IC_CON_ICM_SHIFT) /* Every rising edge */
# define IC_CON_ICM_4th (4 << IC_CON_ICM_SHIFT) /* Every fourth rising edge */
# define IC_CON_ICM_16th (5 << IC_CON_ICM_SHIFT) /* Every sixteenth rising edge */
# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICM_SHIFT) /* Specified edge first and every edge thereafter */
# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICM_SHIFT) /* Interrupt-only mode */
#define IC_CON_ICBNE (1 << 3) /* Bit 3: Input Capture Buffer Not Empty Status */
#define IC_CON_ICOV (1 << 4) /* Bit 4: Input Capture */
#define IC_CON_ICI_SHIFT (5) /* Bits 5-6: Interrupt Control */
#define IC_CON_ICI_MASK (3 << IC_CON_ICI_SHIFT)
# define IC_CON_ICI_EVERY (0 << IC_CON_ICI_SHIFT) /* Interrupt every capture event */
# define IC_CON_ICI_2ND (1 << IC_CON_ICI_SHIFT) /* Interrupt every 2nd capture event */
# define IC_CON_ICI_3RD (2 << IC_CON_ICI_SHIFT) /* Interrupt every 3rd capture event */
# define IC_CON_ICI_4TH (3 << IC_CON_ICI_SHIFT) /* Interrupt every 4th capture event */
#define IC_CON_ICTMR (1 << 7) /* Bit 7: Timer Select */
#define IC_CON_C32 (1 << 8) /* Bit 8: 32-bit Capture Select */
#define IC_CON_FEDGE (1 << 9) /* Bit 9: First Capture Edge Select */
#define IC_CON_SIDL (1 << 13) /* Bit 13: Stop in Idle Control */
#define IC_CON_FRZ (1 << 14) /* Bit 14: Freeze in Debug Mode Control */
#define IC_CON_ON (1 << 15) /* Bit 15: Input Capture Module Enable */
/* Input Capture X Buffer Register -- 32-bit capture value */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NIC > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H */
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-ic.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NIC > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
#define PIC32MX_IC_CONSET_OFFSET 0x0008 /* Input Capture X Control Clear Register */
#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
/* Register Addresses ***************************************************************/
#define PIC32MX_IC_CON(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CON_OFFSET)
#define PIC32MX_IC_CONCLR(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONCLR_OFFSET)
#define PIC32MX_IC_CONSET(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONSET_OFFSET)
#define PIC32MX_IC_CONINV(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_CONINV_OFFSET)
#define PIC32MX_IC_BUF(n) (PIC32MX_IC_K1BASE(n)+PIC32MX_IC_BUF_OFFSET)
#define PIC32MX_IC1_CON (PIC32MX_IC1_K1BASE+PIC32MX_IC_CON_OFFSET)
#define PIC32MX_IC1_CONCLR (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
#define PIC32MX_IC1_CONSET (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONSET_OFFSET)
#define PIC32MX_IC1_CONINV (PIC32MX_IC1_K1BASE+PIC32MX_IC_CONINV_OFFSET)
#define PIC32MX_IC1_BUF (PIC32MX_IC1_K1BASE+PIC32MX_IC_BUF_OFFSET)
#if CHIP_NIC > 1
# define PIC32MX_IC2_CON (PIC32MX_IC2_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC2_CONCLR (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC2_CONSET (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC2_CONINV (PIC32MX_IC2_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC2_BUF (PIC32MX_IC2_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 2
# define PIC32MX_IC3_CON (PIC32MX_IC3_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC3_CONCLR (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC3_CONSET (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC3_CONINV (PIC32MX_IC3_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC3_BUF (PIC32MX_IC3_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 3
# define PIC32MX_IC4_CON (PIC32MX_IC4_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC4_CONCLR (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC4_CONSET (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC4_CONINV (PIC32MX_IC4_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC4_BUF (PIC32MX_IC4_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
#if CHIP_NIC > 4
# define PIC32MX_IC5_CON (PIC32MX_IC5_K1BASE+PIC32MX_IC_CON_OFFSET)
# define PIC32MX_IC5_CONCLR (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONCLR_OFFSET)
# define PIC32MX_IC5_CONSET (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONSET_OFFSET)
# define PIC32MX_IC5_CONINV (PIC32MX_IC5_K1BASE+PIC32MX_IC_CONINV_OFFSET)
# define PIC32MX_IC5_BUF (PIC32MX_IC5_K1BASE+PIC32MX_IC_BUF_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Input Capture X Control Register */
#define IC_CON_ICM_SHIFT (0) /* Bits 0-2: Input Capture Mode Select */
#define IC_CON_ICM_MASK (7 << IC_CON_ICM_SHIFT)
# define IC_CON_ICM_DISABLE (0 << IC_CON_ICM_SHIFT) /* Capture disable mode */
# define IC_CON_ICM_EDGE (1 << IC_CON_ICM_SHIFT) /* Edge detect mode */
# define IC_CON_ICM_FALLING (2 << IC_CON_ICM_SHIFT) /* Every falling edge */
# define IC_CON_ICM_RISING (3 << IC_CON_ICM_SHIFT) /* Every rising edge */
# define IC_CON_ICM_4th (4 << IC_CON_ICM_SHIFT) /* Every fourth rising edge */
# define IC_CON_ICM_16th (5 << IC_CON_ICM_SHIFT) /* Every sixteenth rising edge */
# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICM_SHIFT) /* Specified edge first and every edge thereafter */
# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICM_SHIFT) /* Interrupt-only mode */
#define IC_CON_ICBNE (1 << 3) /* Bit 3: Input Capture Buffer Not Empty Status */
#define IC_CON_ICOV (1 << 4) /* Bit 4: Input Capture */
#define IC_CON_ICI_SHIFT (5) /* Bits 5-6: Interrupt Control */
#define IC_CON_ICI_MASK (3 << IC_CON_ICI_SHIFT)
# define IC_CON_ICI_EVERY (0 << IC_CON_ICI_SHIFT) /* Interrupt every capture event */
# define IC_CON_ICI_2ND (1 << IC_CON_ICI_SHIFT) /* Interrupt every 2nd capture event */
# define IC_CON_ICI_3RD (2 << IC_CON_ICI_SHIFT) /* Interrupt every 3rd capture event */
# define IC_CON_ICI_4TH (3 << IC_CON_ICI_SHIFT) /* Interrupt every 4th capture event */
#define IC_CON_ICTMR (1 << 7) /* Bit 7: Timer Select */
#define IC_CON_C32 (1 << 8) /* Bit 8: 32-bit Capture Select */
#define IC_CON_FEDGE (1 << 9) /* Bit 9: First Capture Edge Select */
#define IC_CON_SIDL (1 << 13) /* Bit 13: Stop in Idle Control */
#define IC_CON_FRZ (1 << 14) /* Bit 14: Freeze in Debug Mode Control */
#define IC_CON_ON (1 << 15) /* Bit 15: Input Capture Module Enable */
/* Input Capture X Buffer Register -- 32-bit capture value */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NIC > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IC_H */

422
arch/mips/src/pic32mx/pic32mx-oc.h
View File

@ -1,211 +1,211 @@
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-oc.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NOC > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_OC_CON_OFFSET 0x0000 /* Output compare control register */
#define PIC32MX_OC_CONCLR_OFFSET 0x0004 /* Output compare control clear register */
#define PIC32MX_OC_CONSET_OFFSET 0x0008 /* Output compare control set register */
#define PIC32MX_OC_CONINV_OFFSET 0x000c /* Output compare control invert register */
#define PIC32MX_OC_R_OFFSET 0x0010 /* Output compare data register */
#define PIC32MX_OC_RCLR_OFFSET 0x0014 /* Output compare data clear register */
#define PIC32MX_OC_RSET_OFFSET 0x0018 /* Output compare data set register */
#define PIC32MX_OC_RINV_OFFSET 0x001c /* Output compare data invert register */
#define PIC32MX_OC_RS_OFFSET 0x0020 /* Output compare secondary data register */
#define PIC32MX_OC_RSCLR_OFFSET 0x0024 /* Output compare secondary data clear register */
#define PIC32MX_OC_RSSET_OFFSET 0x0028 /* Output compare secondary data set register */
#define PIC32MX_OC_RSINV_OFFSET 0x002c /* Output compare secondary data invert register */
/* See also TIMER2 and TIMER3 registers */
/* Register Addresses ***************************************************************/
#define PIC32MX_OC_CON(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CON_OFFSET)
#define PIC32MX_OC_CONCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONCLR_OFFSET)
#define PIC32MX_OC_CONSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONSET_OFFSET)
#define PIC32MX_OC_CONINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONINV_OFFSET)
#define PIC32MX_OC_R(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_R_OFFSET)
#define PIC32MX_OC_RCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RCLR_OFFSET)
#define PIC32MX_OC_RSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSET_OFFSET)
#define PIC32MX_OC_RINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RINV_OFFSET)
#define PIC32MX_OC_RS(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RS_OFFSET)
#define PIC32MX_OC_RSCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSCLR_OFFSET)
#define PIC32MX_OC_RSSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSSET_OFFSET)
#define PIC32MX_OC_RSINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSINV_OFFSET)
#define PIC32MX_OC1_CON (PIC32MX_OC1_K1BASE+PIC32MX_OC_CON_OFFSET)
#define PIC32MX_OC1_CONCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
#define PIC32MX_OC1_CONSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONSET_OFFSET)
#define PIC32MX_OC1_CONINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONINV_OFFSET)
#define PIC32MX_OC1_R (PIC32MX_OC1_K1BASE+PIC32MX_OC_R_OFFSET)
#define PIC32MX_OC1_RCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RCLR_OFFSET)
#define PIC32MX_OC1_RSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSET_OFFSET)
#define PIC32MX_OC1_RINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RINV_OFFSET)
#define PIC32MX_OC1_RS (PIC32MX_OC1_K1BASE+PIC32MX_OC_RS_OFFSET)
#define PIC32MX_OC1_RSCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
#define PIC32MX_OC1_RSSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSSET_OFFSET)
#define PIC32MX_OC1_RSINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#if CHIP_NOC > 1
# define PIC32MX_OC2_CON (PIC32MX_OC2_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC2_CONCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC2_CONSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC2_CONINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC2_R (PIC32MX_OC2_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC2_RCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC2_RSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC2_RINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC2_RS (PIC32MX_OC2_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC2_RSCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC2_RSSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC2_RSINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 2
# define PIC32MX_OC3_CON (PIC32MX_OC3_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC3_CONCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC3_CONSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC3_CONINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC3_R (PIC32MX_OC3_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC3_RCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC3_RSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC3_RINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC3_RS (PIC32MX_OC3_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC3_RSCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC3_RSSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC3_RSINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 3
# define PIC32MX_OC4_CON (PIC32MX_OC4_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC4_CONCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC4_CONSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC4_CONINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC4_R (PIC32MX_OC4_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC4_RCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC4_RSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC4_RINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC4_RS (PIC32MX_OC4_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC4_RSCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC4_RSSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC4_RSINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 4
# define PIC32MX_OC5_CON (PIC32MX_OC5_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC5_CONCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC5_CONSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC5_CONINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC5_R (PIC32MX_OC5_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC5_RCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC5_RSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC5_RINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC5_RS (PIC32MX_OC5_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC5_RSCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC5_RSSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC5_RSINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Output compare control register */
#define OC_CON_OCM_SHIFT (0) /* Bits 0-2: Output compare mode select */
#define OC_CON_OCM_MASK (7 << OC_CON_OCM_SHIFT)
# define OC_CON_OCM_DISABLE (0 << OC_CON_OCM_SHIFT) /* Output compare peripheral disabled */
# define OC_CON_OCM_LOW2HI (1 << OC_CON_OCM_SHIFT) /* OCx low; compare forces high */
# define OC_CON_OCM_HITOLOW (2 << OC_CON_OCM_SHIFT) /* OCx high; compare forces low */
# define OC_CON_OCM_TOGGLE (3 << OC_CON_OCM_SHIFT) /* Compare event toggles OCx */
# define OC_CON_OCM_LOWPULSE (4 << OC_CON_OCM_SHIFT) /* OCx low; output pulse on OCx*/
# define OC_CON_OCM_HIPULSE (5 << OC_CON_OCM_SHIFT) /* OCx high; output pulse on OCx */
# define OC_CON_OCM_PWM (6 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault disabled */
# define OC_CON_OCM_PWMFAULT (7 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault enabled */
#define OC_CON_OCTSEL (1 << 3) /* Bit 3: Output compare timer select */
#define OC_CON_OCFLT (1 << 4) /* Bit 4: PWM fault condition status */
#define OC_CON_OC32 (1 << 5) /* Bit 5: 32-bit compare more */
#define OC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define OC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define OC_CON_ON (1 << 15) /* Bit 15: Output compare periperal on */
/* Output compare data register -- 32-bit data register */
/* Output compare secondary data register -- 32-bit data register */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NOC > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H */
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-oc.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NOC > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_OC_CON_OFFSET 0x0000 /* Output compare control register */
#define PIC32MX_OC_CONCLR_OFFSET 0x0004 /* Output compare control clear register */
#define PIC32MX_OC_CONSET_OFFSET 0x0008 /* Output compare control set register */
#define PIC32MX_OC_CONINV_OFFSET 0x000c /* Output compare control invert register */
#define PIC32MX_OC_R_OFFSET 0x0010 /* Output compare data register */
#define PIC32MX_OC_RCLR_OFFSET 0x0014 /* Output compare data clear register */
#define PIC32MX_OC_RSET_OFFSET 0x0018 /* Output compare data set register */
#define PIC32MX_OC_RINV_OFFSET 0x001c /* Output compare data invert register */
#define PIC32MX_OC_RS_OFFSET 0x0020 /* Output compare secondary data register */
#define PIC32MX_OC_RSCLR_OFFSET 0x0024 /* Output compare secondary data clear register */
#define PIC32MX_OC_RSSET_OFFSET 0x0028 /* Output compare secondary data set register */
#define PIC32MX_OC_RSINV_OFFSET 0x002c /* Output compare secondary data invert register */
/* See also TIMER2 and TIMER3 registers */
/* Register Addresses ***************************************************************/
#define PIC32MX_OC_CON(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CON_OFFSET)
#define PIC32MX_OC_CONCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONCLR_OFFSET)
#define PIC32MX_OC_CONSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONSET_OFFSET)
#define PIC32MX_OC_CONINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_CONINV_OFFSET)
#define PIC32MX_OC_R(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_R_OFFSET)
#define PIC32MX_OC_RCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RCLR_OFFSET)
#define PIC32MX_OC_RSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSET_OFFSET)
#define PIC32MX_OC_RINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RINV_OFFSET)
#define PIC32MX_OC_RS(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RS_OFFSET)
#define PIC32MX_OC_RSCLR(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSCLR_OFFSET)
#define PIC32MX_OC_RSSET(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSSET_OFFSET)
#define PIC32MX_OC_RSINV(n) (PIC32MX_OC_K1BASE(n)+PIC32MX_OC_RSINV_OFFSET)
#define PIC32MX_OC1_CON (PIC32MX_OC1_K1BASE+PIC32MX_OC_CON_OFFSET)
#define PIC32MX_OC1_CONCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
#define PIC32MX_OC1_CONSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONSET_OFFSET)
#define PIC32MX_OC1_CONINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_CONINV_OFFSET)
#define PIC32MX_OC1_R (PIC32MX_OC1_K1BASE+PIC32MX_OC_R_OFFSET)
#define PIC32MX_OC1_RCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RCLR_OFFSET)
#define PIC32MX_OC1_RSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSET_OFFSET)
#define PIC32MX_OC1_RINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RINV_OFFSET)
#define PIC32MX_OC1_RS (PIC32MX_OC1_K1BASE+PIC32MX_OC_RS_OFFSET)
#define PIC32MX_OC1_RSCLR (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
#define PIC32MX_OC1_RSSET (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSSET_OFFSET)
#define PIC32MX_OC1_RSINV (PIC32MX_OC1_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#if CHIP_NOC > 1
# define PIC32MX_OC2_CON (PIC32MX_OC2_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC2_CONCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC2_CONSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC2_CONINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC2_R (PIC32MX_OC2_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC2_RCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC2_RSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC2_RINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC2_RS (PIC32MX_OC2_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC2_RSCLR (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC2_RSSET (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC2_RSINV (PIC32MX_OC2_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 2
# define PIC32MX_OC3_CON (PIC32MX_OC3_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC3_CONCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC3_CONSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC3_CONINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC3_R (PIC32MX_OC3_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC3_RCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC3_RSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC3_RINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC3_RS (PIC32MX_OC3_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC3_RSCLR (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC3_RSSET (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC3_RSINV (PIC32MX_OC3_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 3
# define PIC32MX_OC4_CON (PIC32MX_OC4_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC4_CONCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC4_CONSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC4_CONINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC4_R (PIC32MX_OC4_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC4_RCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC4_RSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC4_RINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC4_RS (PIC32MX_OC4_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC4_RSCLR (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC4_RSSET (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC4_RSINV (PIC32MX_OC4_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
#if CHIP_NOC > 4
# define PIC32MX_OC5_CON (PIC32MX_OC5_K1BASE+PIC32MX_OC_CON_OFFSET)
# define PIC32MX_OC5_CONCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONCLR_OFFSET)
# define PIC32MX_OC5_CONSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONSET_OFFSET)
# define PIC32MX_OC5_CONINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_CONINV_OFFSET)
# define PIC32MX_OC5_R (PIC32MX_OC5_K1BASE+PIC32MX_OC_R_OFFSET)
# define PIC32MX_OC5_RCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RCLR_OFFSET)
# define PIC32MX_OC5_RSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSET_OFFSET)
# define PIC32MX_OC5_RINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RINV_OFFSET)
# define PIC32MX_OC5_RS (PIC32MX_OC5_K1BASE+PIC32MX_OC_RS_OFFSET)
# define PIC32MX_OC5_RSCLR (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSCLR_OFFSET)
# define PIC32MX_OC5_RSSET (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSSET_OFFSET)
# define PIC32MX_OC5_RSINV (PIC32MX_OC5_K1BASE+PIC32MX_OC_RSINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Output compare control register */
#define OC_CON_OCM_SHIFT (0) /* Bits 0-2: Output compare mode select */
#define OC_CON_OCM_MASK (7 << OC_CON_OCM_SHIFT)
# define OC_CON_OCM_DISABLE (0 << OC_CON_OCM_SHIFT) /* Output compare peripheral disabled */
# define OC_CON_OCM_LOW2HI (1 << OC_CON_OCM_SHIFT) /* OCx low; compare forces high */
# define OC_CON_OCM_HITOLOW (2 << OC_CON_OCM_SHIFT) /* OCx high; compare forces low */
# define OC_CON_OCM_TOGGLE (3 << OC_CON_OCM_SHIFT) /* Compare event toggles OCx */
# define OC_CON_OCM_LOWPULSE (4 << OC_CON_OCM_SHIFT) /* OCx low; output pulse on OCx*/
# define OC_CON_OCM_HIPULSE (5 << OC_CON_OCM_SHIFT) /* OCx high; output pulse on OCx */
# define OC_CON_OCM_PWM (6 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault disabled */
# define OC_CON_OCM_PWMFAULT (7 << OC_CON_OCM_SHIFT) /* PWM mode on OCx; fault enabled */
#define OC_CON_OCTSEL (1 << 3) /* Bit 3: Output compare timer select */
#define OC_CON_OCFLT (1 << 4) /* Bit 4: PWM fault condition status */
#define OC_CON_OC32 (1 << 5) /* Bit 5: 32-bit compare more */
#define OC_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */
#define OC_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */
#define OC_CON_ON (1 << 15) /* Bit 15: Output compare periperal on */
/* Output compare data register -- 32-bit data register */
/* Output compare secondary data register -- 32-bit data register */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NOC > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OC_H */

444
arch/mips/src/pic32mx/pic32mx-timer.h
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@ -1,222 +1,222 @@
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-timer.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NTIMERS > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_TIMER_CON_OFFSET 0x0000 /* Timer control register */
#define PIC32MX_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
#define PIC32MX_TIMER_CONSET_OFFSET 0x0008 /* Timer control set register */
#define PIC32MX_TIMER_CONINV_OFFSET 0x000c /* Timer control invert register */
#define PIC32MX_TIMER_CNT_OFFSET 0x0010 /* Timer count register */
#define PIC32MX_TIMER_CNTCLR_OFFSET 0x0014 /* Timer count clear register */
#define PIC32MX_TIMER_CNTSET_OFFSET 0x0018 /* Timer count set register */
#define PIC32MX_TIMER_CNTINV_OFFSET 0x001c /* Timer count invert register */
#define PIC32MX_TIMER_PR_OFFSET 0x0020 /* Timer period register */
#define PIC32MX_TIMER_PRCLR_OFFSET 0x0024 /* Timer period clear register */
#define PIC32MX_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
#define PIC32MX_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
/* Register Addresses ***************************************************************/
#define PIC32MX_TIMER_CON(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CON_OFFSET)
#define PIC32MX_TIMER_CONCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONCLR_OFFSET)
#define PIC32MX_TIMER_CONSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONSET_OFFSET)
#define PIC32MX_TIMER_CONINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONINV_OFFSET)
#define PIC32MX_TIMER_CNT(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNT_OFFSET)
#define PIC32MX_TIMER_CNTCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTCLR_OFFSET)
#define PIC32MX_TIMER_CNTSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTSET_OFFSET)
#define PIC32MX_TIMER_CNTINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTINV_OFFSET)
#define PIC32MX_TIMER_PR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PR_OFFSET)
#define PIC32MX_TIMER_PRCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRCLR_OFFSET)
#define PIC32MX_TIMER_PRSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRSET_OFFSET)
#define PIC32MX_TIMER_PRINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRINV_OFFSET)
#define PIC32MX_TIMER1_CON (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CON_OFFSET)
#define PIC32MX_TIMER1_CONCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
#define PIC32MX_TIMER1_CONSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
#define PIC32MX_TIMER1_CONINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
#define PIC32MX_TIMER1_CNT (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
#define PIC32MX_TIMER1_CNTCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
#define PIC32MX_TIMER1_CNTSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
#define PIC32MX_TIMER1_CNTINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
#define PIC32MX_TIMER1_PR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PR_OFFSET)
#define PIC32MX_TIMER1_PRCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
#define PIC32MX_TIMER1_PRSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
#define PIC32MX_TIMER1_PRINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#if CHIP_NTIMERS > 1
# define PIC32MX_TIMER2_CON (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER2_CONCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER2_CONSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER2_CONINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER2_CNT (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER2_CNTCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER2_CNTSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER2_CNTINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER2_PR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER2_PRCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER2_PRSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER2_PRINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 2
# define PIC32MX_TIMER3_CON (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER3_CONCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER3_CONSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER3_CONINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER3_CNT (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER3_CNTCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER3_CNTSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER3_CNTINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER3_PR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER3_PRCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER3_PRSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER3_PRINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 3
# define PIC32MX_TIMER4_CON (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER4_CONCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER4_CONSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER4_CONINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER4_CNT (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER4_CNTCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER4_CNTSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER4_CNTINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER4_PR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER4_PRCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER4_PRSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER4_PRINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 4
# define PIC32MX_TIMER5_CON (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER5_CONCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER5_CONSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER5_CONINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER5_CNT (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER5_CNTCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER5_CNTSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER5_CNTINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER5_PR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER5_PRCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER5_PRSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER5_PRINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Timer control register */
#define TIMER_CON_TCS (1 << 1) /* Bit 1: Timer clock source select (all) */
#define TIMER1_CON_TSYNC (1 << 2) /* Bit 2: Timer external clock input synchronization selection (timer 1 only) */
#define TIMER_CON_T32 (1 << 3) /* Bit 2: 32-bit timer mode select (even timers only) */
#define TIMER_CON_TCKPS_SHIFT (4) /* Bits 4-6: Timer input clock prescale select (all except timer 1) */
#define TIMER_CON_TCKPS_MASK (7 << TIMER_CON_TCKPS_SHIFT)
# define TIMER_CON_TCKPS_1 (0 << TIMER_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER_CON_TCKPS_2 (1 << TIMER_CON_TCKPS_SHIFT) /* 1:2 prescale value */
# define TIMER_CON_TCKPS_4 (2 << TIMER_CON_TCKPS_SHIFT) /* 1:4 prescale value */
# define TIMER_CON_TCKPS_8 (3 << TIMER_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER_CON_TCKPS_16 (4 << TIMER_CON_TCKPS_SHIFT) /* 1:16 prescale value */
# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
#define TIMER_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode (all) */
#define TIMER_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode (all) */
#define TIMER_CON_ON (1 << 15) /* Bit 15: Timer on (all) */
/* Timer count register */
#define TIMER_CNT_MASK 0xffff /* 16-bit timer counter value */
/* Timer period register */
#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NTIMERS > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H */
/************************************************************************************
* arch/mips/src/pic32mx/pic32mx-timer.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
#if CHIP_NTIMERS > 0
/************************************************************************************
* Pre-Processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_TIMER_CON_OFFSET 0x0000 /* Timer control register */
#define PIC32MX_TIMER_CONCLR_OFFSET 0x0004 /* Timer control clear register */
#define PIC32MX_TIMER_CONSET_OFFSET 0x0008 /* Timer control set register */
#define PIC32MX_TIMER_CONINV_OFFSET 0x000c /* Timer control invert register */
#define PIC32MX_TIMER_CNT_OFFSET 0x0010 /* Timer count register */
#define PIC32MX_TIMER_CNTCLR_OFFSET 0x0014 /* Timer count clear register */
#define PIC32MX_TIMER_CNTSET_OFFSET 0x0018 /* Timer count set register */
#define PIC32MX_TIMER_CNTINV_OFFSET 0x001c /* Timer count invert register */
#define PIC32MX_TIMER_PR_OFFSET 0x0020 /* Timer period register */
#define PIC32MX_TIMER_PRCLR_OFFSET 0x0024 /* Timer period clear register */
#define PIC32MX_TIMER_PRSET_OFFSET 0x0028 /* Timer period set register */
#define PIC32MX_TIMER_PRINV_OFFSET 0x002c /* Timer period invert register */
/* Register Addresses ***************************************************************/
#define PIC32MX_TIMER_CON(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CON_OFFSET)
#define PIC32MX_TIMER_CONCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONCLR_OFFSET)
#define PIC32MX_TIMER_CONSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONSET_OFFSET)
#define PIC32MX_TIMER_CONINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CONINV_OFFSET)
#define PIC32MX_TIMER_CNT(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNT_OFFSET)
#define PIC32MX_TIMER_CNTCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTCLR_OFFSET)
#define PIC32MX_TIMER_CNTSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTSET_OFFSET)
#define PIC32MX_TIMER_CNTINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_CNTINV_OFFSET)
#define PIC32MX_TIMER_PR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PR_OFFSET)
#define PIC32MX_TIMER_PRCLR(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRCLR_OFFSET)
#define PIC32MX_TIMER_PRSET(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRSET_OFFSET)
#define PIC32MX_TIMER_PRINV(n) (PIC32MX_TIMER_K1BASE(n)+PIC32MX_TIMER_PRINV_OFFSET)
#define PIC32MX_TIMER1_CON (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CON_OFFSET)
#define PIC32MX_TIMER1_CONCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
#define PIC32MX_TIMER1_CONSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
#define PIC32MX_TIMER1_CONINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
#define PIC32MX_TIMER1_CNT (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
#define PIC32MX_TIMER1_CNTCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
#define PIC32MX_TIMER1_CNTSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
#define PIC32MX_TIMER1_CNTINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
#define PIC32MX_TIMER1_PR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PR_OFFSET)
#define PIC32MX_TIMER1_PRCLR (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
#define PIC32MX_TIMER1_PRSET (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
#define PIC32MX_TIMER1_PRINV (PIC32MX_TIMER1_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#if CHIP_NTIMERS > 1
# define PIC32MX_TIMER2_CON (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER2_CONCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER2_CONSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER2_CONINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER2_CNT (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER2_CNTCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER2_CNTSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER2_CNTINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER2_PR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER2_PRCLR (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER2_PRSET (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER2_PRINV (PIC32MX_TIMER2_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 2
# define PIC32MX_TIMER3_CON (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER3_CONCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER3_CONSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER3_CONINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER3_CNT (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER3_CNTCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER3_CNTSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER3_CNTINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER3_PR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER3_PRCLR (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER3_PRSET (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER3_PRINV (PIC32MX_TIMER3_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 3
# define PIC32MX_TIMER4_CON (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER4_CONCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER4_CONSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER4_CONINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER4_CNT (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER4_CNTCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER4_CNTSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER4_CNTINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER4_PR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER4_PRCLR (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER4_PRSET (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER4_PRINV (PIC32MX_TIMER4_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
#if CHIP_NTIMERS > 4
# define PIC32MX_TIMER5_CON (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CON_OFFSET)
# define PIC32MX_TIMER5_CONCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONCLR_OFFSET)
# define PIC32MX_TIMER5_CONSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONSET_OFFSET)
# define PIC32MX_TIMER5_CONINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CONINV_OFFSET)
# define PIC32MX_TIMER5_CNT (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNT_OFFSET)
# define PIC32MX_TIMER5_CNTCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTCLR_OFFSET)
# define PIC32MX_TIMER5_CNTSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTSET_OFFSET)
# define PIC32MX_TIMER5_CNTINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_CNTINV_OFFSET)
# define PIC32MX_TIMER5_PR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PR_OFFSET)
# define PIC32MX_TIMER5_PRCLR (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRCLR_OFFSET)
# define PIC32MX_TIMER5_PRSET (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRSET_OFFSET)
# define PIC32MX_TIMER5_PRINV (PIC32MX_TIMER5_K1BASE+PIC32MX_TIMER_PRINV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/
/* Timer control register */
#define TIMER_CON_TCS (1 << 1) /* Bit 1: Timer clock source select (all) */
#define TIMER1_CON_TSYNC (1 << 2) /* Bit 2: Timer external clock input synchronization selection (timer 1 only) */
#define TIMER_CON_T32 (1 << 3) /* Bit 2: 32-bit timer mode select (even timers only) */
#define TIMER_CON_TCKPS_SHIFT (4) /* Bits 4-6: Timer input clock prescale select (all except timer 1) */
#define TIMER_CON_TCKPS_MASK (7 << TIMER_CON_TCKPS_SHIFT)
# define TIMER_CON_TCKPS_1 (0 << TIMER_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER_CON_TCKPS_2 (1 << TIMER_CON_TCKPS_SHIFT) /* 1:2 prescale value */
# define TIMER_CON_TCKPS_4 (2 << TIMER_CON_TCKPS_SHIFT) /* 1:4 prescale value */
# define TIMER_CON_TCKPS_8 (3 << TIMER_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER_CON_TCKPS_16 (4 << TIMER_CON_TCKPS_SHIFT) /* 1:16 prescale value */
# define TIMER_CON_TCKPS_32 (5 << TIMER_CON_TCKPS_SHIFT) /* 1:32 prescale value */
# define TIMER_CON_TCKPS_64 (6 << TIMER_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER_CON_TCKPS_256 (7 << TIMER_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER1_CON_TCKPS_SHIFT (4) /* Bits 4-5: Timer input clock prescale select (timer 1 only) */
#define TIMER1_CON_TCKPS_MASK (3 << TIMER1_CON_TCKPS_SHIFT)
# define TIMER1_CON_TCKPS_1 (0 << TIMER1_CON_TCKPS_SHIFT) /* 1:1 prescale value */
# define TIMER1_CON_TCKPS_8 (1 << TIMER1_CON_TCKPS_SHIFT) /* 1:8 prescale value */
# define TIMER1_CON_TCKPS_64 (2 << TIMER1_CON_TCKPS_SHIFT) /* 1:64 prescale value */
# define TIMER1_CON_TCKPS_256 (3 << TIMER1_CON_TCKPS_SHIFT) /* 1:256 prescale value */
#define TIMER_CON_TGATE (1 << 7) /* Bit 7: Timer gated time accumulation enable (all) */
#define TIMER1_CON_TWIP (1 << 11) /* Bit 11: Asynchronous timer write in progress (timer 1 only) */
#define TIMER1_CON_TWDIS (1 << 12) /* Bit 12: Asynchronous timer write disable (timer 1 only) */
#define TIMER_CON_SIDL (1 << 13) /* Bit 13: Stop in idle mode (all) */
#define TIMER_CON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode (all) */
#define TIMER_CON_ON (1 << 15) /* Bit 15: Timer on (all) */
/* Timer count register */
#define TIMER_CNT_MASK 0xffff /* 16-bit timer counter value */
/* Timer period register */
#define TIMER_PR_MASK 0xffff /* 16-bit timer period value */
/************************************************************************************
* Public Types
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Inline Functions
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CHIP_NTIMERS > 0 */
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_TIMER_H */

2
arch/sh/src/common/up_allocateheap.c
View File

@ -80,7 +80,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/sh/src/common/up_assert.c
View File

@ -87,9 +87,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -114,7 +114,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/sh/src/common/up_createstack.c
View File

@ -192,7 +192,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/sh/src/common/up_doirq.c
View File

@ -71,7 +71,7 @@
uint32_t *up_doirq(int irq, uint32_t* regs)
{
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -127,7 +127,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs)
up_enable_irq(irq);
#endif
}
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
#endif
return regs;
}

2
arch/sh/src/common/up_initialize.c
View File

@ -180,5 +180,5 @@ void up_initialize(void)
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

12
arch/sh/src/common/up_internal.h
View File

@ -219,13 +219,13 @@ extern void up_maskack_irq(int irq);
/* Defined in board/up_leds.c */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(int led);
extern void up_ledoff(int led);
extern void board_led_initialize(void);
extern void board_led_on(int led);
extern void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
/* Defined in board/up_lcd.c */

4
arch/sh/src/m16c/m16c_head.S
View File

@ -260,8 +260,8 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
.globl _up_ledinit /* Boot LED setup */
jsr.a _up_ledinit /* Call it */
.globl _board_led_initialize /* Boot LED setup */
jsr.a _board_led_initialize /* Call it */
#endif
showprogress '\n'

4
arch/sh/src/m16c/m16c_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -135,7 +135,7 @@ void up_sigdeliver(void)
* execution.
*/
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
#endif
}

6
arch/sh/src/sh1/sh1_head.S
View File

@ -65,7 +65,7 @@
.globl _up_earlyconsoleinit /* Early initialization of console driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl _up_ledinit /* Boot LED setup */
.globl _board_led_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG
.globl _up_lowputc /* Low-level debug output */
@ -445,7 +445,7 @@ __start0:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
mov.l .Lledinit, r0 /* Address of up_ledinit */
mov.l .Lledinit, r0 /* Address of board_led_initialize */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
#endif
@ -492,7 +492,7 @@ __start0:
.long _up_lowputc
#endif
.Lledinit:
.long _up_ledinit
.long _board_led_initialize
.Losstart:
.long _os_start
.Lsvect:

4
arch/sh/src/sh1/sh1_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
#endif
}

2
arch/x86/src/common/up_allocateheap.c
View File

@ -81,7 +81,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/x86/src/common/up_assert.c
View File

@ -220,9 +220,9 @@ static void _up_assert(int errorcode)
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -247,7 +247,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/x86/src/common/up_initialize.c
View File

@ -191,5 +191,5 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
up_ledon(LED_IRQSENABLED);
board_led_on(LED_IRQSENABLED);
}

12
arch/x86/src/common/up_internal.h
View File

@ -241,13 +241,13 @@ extern void up_maskack_irq(int irq);
/* Defined in board/up_leds.c */
#ifdef CONFIG_ARCH_LEDS
extern void up_ledinit(void);
extern void up_ledon(int led);
extern void up_ledoff(int led);
extern void board_led_initialize(void);
extern void board_led_on(int led);
extern void board_led_off(int led);
#else
# define up_ledinit()
# define up_ledon(led)
# define up_ledoff(led)
# define board_led_initialize()
# define board_led_on(led)
# define board_led_off(led)
#endif
/* Defined in board/up_network.c */

2
arch/x86/src/i486/up_createstack.c
View File

@ -192,7 +192,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/x86/src/i486/up_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
up_ledon(LED_SIGNAL);
board_led_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -131,7 +131,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
up_ledoff(LED_SIGNAL);
board_led_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

14
arch/x86/src/qemu/qemu_handlers.c
View File

@ -89,7 +89,7 @@ static uint32_t *common_handler(int irq, uint32_t *regs)
{
uint32_t *savestate;
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
/* Nested interrupts are not supported in this implementation. If you want
* implemented nested interrupts, you would have to (1) change the way that
@ -141,7 +141,7 @@ static uint32_t *common_handler(int irq, uint32_t *regs)
uint32_t *isr_handler(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
PANIC(); /* Doesn't return */
return regs; /* To keep the compiler happy */
#else
@ -149,9 +149,9 @@ uint32_t *isr_handler(uint32_t *regs)
/* Dispatch the interrupt */
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
ret = common_handler((int)regs[REG_IRQNO], regs);
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return ret;
#endif
}
@ -167,14 +167,14 @@ uint32_t *isr_handler(uint32_t *regs)
uint32_t *irq_handler(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
PANIC(); /* Doesn't return */
return regs; /* To keep the compiler happy */
#else
uint32_t *ret;
int irq;
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
/* Get the IRQ number */
@ -198,7 +198,7 @@ uint32_t *irq_handler(uint32_t *regs)
/* Dispatch the interrupt */
ret = common_handler(irq, regs);
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
return ret;
#endif
}

2
arch/z16/src/common/up_allocateheap.c
View File

@ -98,7 +98,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
*heap_start = (FAR void*)CONFIG_HEAP1_BASE;
*heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE;
up_ledon(LED_HEAPALLOCATE);
board_led_on(LED_HEAPALLOCATE);
}
/****************************************************************************

6
arch/z16/src/common/up_assert.c
View File

@ -87,9 +87,9 @@ static void _up_assert(int errorcode) /* noreturn_function */
for(;;)
{
#ifdef CONFIG_ARCH_LEDS
up_ledon(LED_PANIC);
board_led_on(LED_PANIC);
up_mdelay(250);
up_ledoff(LED_PANIC);
board_led_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -118,7 +118,7 @@ void up_assert(void)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
up_ledon(LED_ASSERTION);
board_led_on(LED_ASSERTION);
#ifdef CONFIG_HAVE_FILENAME
#if CONFIG_TASK_NAME_SIZE > 0

2
arch/z16/src/common/up_createstack.c
View File

@ -191,7 +191,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
up_ledon(LED_STACKCREATED);
board_led_on(LED_STACKCREATED);
return OK;
}

4
arch/z16/src/common/up_doirq.c
View File

@ -82,7 +82,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs)
{
FAR chipreg_t *ret = regs;
up_ledon(LED_INIRQ);
board_led_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -130,7 +130,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs)
up_enable_irq(irq);
}
up_ledoff(LED_INIRQ);
board_led_off(LED_INIRQ);
#endif
return ret;

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