Revert THRNE-patch. The problem was in u16550_putc
Regarding to: https://github.com/tanzilli/ariag25-linux-2.6.39/blob/ariag25/drivers/tty/serial/8250.c#L1584 https://github.com/tanzilli/ariag25-linux-2.6.39/blob/ariag25/drivers/tty/serial/8250.c#L1913 When UART_LSR_THRE bit is set, then we ready to transmit more. Current u16550_putc loops while UART_LSR_THRE bit is set. This logic have to be inverted. Signed-off-by: Anton D. Kachalov <mouse@yandex-team.ru>
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@ -337,18 +337,7 @@ config 16550_ADDRWIDTH
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---help---
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---help---
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The bit width of registers. Options are 8, 16, or 32. Default: 8
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The bit width of registers. Options are 8, 16, or 32. Default: 8
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config 16550_THRNE
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endif
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bool "Use THRNE"
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default n if !ARCH_CHIP_MOXART
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default y if ARCH_CHIP_MOXART
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---help---
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The 16550 UART has a bit in the line status register, THRE, that
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indicates that the Transmit Holding Register (THR) is Empty (N).
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This bit is inverted in at least one variant (the moxART SoC).
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In that case, this setting must be included to use this bit as
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THR *Not* Empty (THRNE).
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endif # 16550_UART
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#
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#
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# MCU serial peripheral driver?
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# MCU serial peripheral driver?
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@ -1065,11 +1065,7 @@ static bool u16550_txempty(struct uart_dev_s *dev)
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static void u16550_putc(struct u16550_s *priv, int ch)
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static void u16550_putc(struct u16550_s *priv, int ch)
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{
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{
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#ifdef CONFIG_16550_THRNE
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while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
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while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRNE) == 0);
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#else
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while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
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#endif
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u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
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u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
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}
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}
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@ -299,11 +299,7 @@
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#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
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#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
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#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
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#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
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#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
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#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
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#ifdef CONFIG_16550_THRNE
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#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
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# define UART_LSR_THRNE (1 << 5) /* Bit 5: Transmitter Holding Register Not Empty */
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#else
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# define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
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#endif
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#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
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#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
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#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
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#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
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