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Revert THRNE-patch. The problem was in u16550_putc

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Regarding to:
https://github.com/tanzilli/ariag25-linux-2.6.39/blob/ariag25/drivers/tty/serial/8250.c#L1584
https://github.com/tanzilli/ariag25-linux-2.6.39/blob/ariag25/drivers/tty/serial/8250.c#L1913

When UART_LSR_THRE bit is set, then we ready to transmit more.

Current u16550_putc loops while UART_LSR_THRE bit is set. This logic have to be inverted.

Signed-off-by: Anton D. Kachalov <mouse@yandex-team.ru>
This commit is contained in:
Anton D. Kachalov 2015-08-03 12:42:39 +03:00
parent 2ca1dd6efe
commit 2fa6237b49
3 changed files with 3 additions and 22 deletions
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13
drivers/serial/Kconfig
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@ -337,18 +337,7 @@ config 16550_ADDRWIDTH
---help---
The bit width of registers. Options are 8, 16, or 32. Default: 8
config 16550_THRNE
bool "Use THRNE"
default n if !ARCH_CHIP_MOXART
default y if ARCH_CHIP_MOXART
---help---
The 16550 UART has a bit in the line status register, THRE, that
indicates that the Transmit Holding Register (THR) is Empty (N).
This bit is inverted in at least one variant (the moxART SoC).
In that case, this setting must be included to use this bit as
THR *Not* Empty (THRNE).
endif # 16550_UART
endif
#
# MCU serial peripheral driver?

6
drivers/serial/uart_16550.c
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@ -1065,11 +1065,7 @@ static bool u16550_txempty(struct uart_dev_s *dev)
static void u16550_putc(struct u16550_s *priv, int ch)
{
#ifdef CONFIG_16550_THRNE
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRNE) == 0);
#else
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
#endif
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
}

6
include/nuttx/serial/uart_16550.h
View File

@ -299,11 +299,7 @@
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
#ifdef CONFIG_16550_THRNE
# define UART_LSR_THRNE (1 << 5) /* Bit 5: Transmitter Holding Register Not Empty */
#else
# define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
#endif
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */