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stm32h7: Adds tickless support.

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This commit is contained in:
Anthony Merlino 2021-04-06 13:41:26 -04:00 committed by Xiang Xiao
parent c61710c7b8
commit 2fad06008a
7 changed files with 1190 additions and 20 deletions
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2
arch/arm/Kconfig
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@ -377,6 +377,8 @@ config ARCH_CHIP_STM32H7
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TIMEKEEPING
---help---
STMicro STM32H7 architectures (ARM Cortex-M7).

21
arch/arm/src/stm32h7/Kconfig
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@ -1838,6 +1838,27 @@ config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED
menu "Timer Configuration"
if SCHED_TICKLESS
config STM32H7_TICKLESS_TIMER
int "Tickless hardware timer"
default 2
range 1 17
---help---
If the Tickless OS feature is enabled, then one clock must be
assigned to provided the timer needed by the OS.
config STM32H7_TICKLESS_CHANNEL
int "Tickless timer channel"
default 1
range 1 4
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the free-running timer needed by the OS
and one channel on that clock is needed to handle intervals.
endif # SCHED_TICKLESS
config STM32H7_ONESHOT
bool "TIM one-shot wrapper"
default n

6
arch/arm/src/stm32h7/Make.defs
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@ -36,6 +36,10 @@ CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_udelay.c arm_unblocktask.c
CMN_CSRCS += arm_usestack.c arm_vfork.c arm_switchcontext.c arm_puts.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
@ -88,6 +92,8 @@ CHIP_CSRCS += stm32_uid.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
else
CHIP_CSRCS += stm32_tickless.c
endif
ifeq ($(CONFIG_STM32H7_ONESHOT),y)

1
arch/arm/src/stm32h7/hardware/stm32h7xxx_dbgmcu.h
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@ -105,7 +105,6 @@
#define DBGMCU_APB2Z1_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when halted */
#define DBGMCU_APB2Z1_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when halted */
#define DBGMCU_APB2Z1_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when halted */
#define DBGMCU_APB2Z1_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when halted */
#define DBGMCU_APB2Z1_HRTIMSTOP (1 << 29) /* Bit 29: HRTIM stopped when halted */
/* Debug MCU APB4 freeze register */

1059
arch/arm/src/stm32h7/stm32_tickless.c Normal file
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File diff suppressed because it is too large Load Diff

113
arch/arm/src/stm32h7/stm32_tim.c
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@ -251,24 +251,31 @@ struct stm32_tim_priv_s
/* Timer methods */
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev,
stm32_tim_mode_t mode);
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev,
uint32_t freq);
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
uint32_t period);
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
uint8_t channel, stm32_tim_channel_t mode);
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev,
uint8_t channel, uint32_t compare);
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev,
uint8_t channel);
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
void *arg, int source);
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source);
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev,
int source);
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source);
static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev,
stm32_tim_mode_t mode);
static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev,
uint32_t freq);
static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
uint32_t period);
static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev);
static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev,
uint32_t count);
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev);
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
uint8_t channel,
stm32_tim_channel_t mode);
static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev,
uint8_t channel, uint32_t compare);
static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev,
uint8_t channel);
static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
xcpt_t handler, void *arg, int source);
static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev,
int source);
static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev,
int source);
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source);
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source);
/****************************************************************************
* Private Data
@ -279,13 +286,17 @@ static const struct stm32_tim_ops_s stm32_tim_ops =
.setmode = &stm32_tim_setmode,
.setclock = &stm32_tim_setclock,
.setperiod = &stm32_tim_setperiod,
.getcounter = &stm32_tim_getcounter,
.setcounter = &stm32_tim_setcounter,
.getwidth = &stm32_tim_getwidth,
.setchannel = &stm32_tim_setchannel,
.setcompare = &stm32_tim_setcompare,
.getcapture = &stm32_tim_getcapture,
.setisr = &stm32_tim_setisr,
.enableint = &stm32_tim_enableint,
.disableint = &stm32_tim_disableint,
.ackint = &stm32_tim_ackint
.ackint = &stm32_tim_ackint,
.checkint = &stm32_tim_checkint,
};
#ifdef CONFIG_STM32H7_TIM1
@ -485,6 +496,64 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val);
}
/*****************************************************************************
* Name: stm32_tim_getwidth
*****************************************************************************/
static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev)
{
/* Only TIM2 and TIM5 timers may be 32-bits in width */
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if defined(CONFIG_STM32H7_TIM2)
case STM32_TIM2_BASE:
return 32;
#endif
#if defined(CONFIG_STM32H7_TIM5)
case STM32_TIM5_BASE:
return 32;
#endif
/* All others are 16-bit times */
default:
return 16;
}
}
/*****************************************************************************
* Name: stm32_tim_getcounter
*****************************************************************************/
static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev)
{
DEBUGASSERT(dev != NULL);
return stm32_tim_getwidth(dev) > 16 ?
stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) :
(uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET);
}
/*****************************************************************************
* Name: stm32_tim_setcounter
*****************************************************************************/
static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev,
uint32_t count)
{
DEBUGASSERT(dev != NULL);
if (stm32_tim_getwidth(dev) > 16)
{
stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count);
}
else
{
stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count);
}
}
/* Reset timer into system default state, but do not affect output/input
* pins
*/
@ -773,6 +842,12 @@ static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0);
}
static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source)
{
uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET);
return (regval & source) ? 1 : 0;
}
static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
{
stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source);

8
arch/arm/src/stm32h7/stm32_tim.h
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@ -39,6 +39,9 @@
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c))
#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
@ -46,6 +49,7 @@
#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
/****************************************************************************
* Public Types
@ -143,9 +147,12 @@ struct stm32_tim_ops_s
int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
uint32_t (*getcounter)(FAR struct stm32_tim_dev_s *dev);
void (*setcounter)(FAR struct stm32_tim_dev_s *dev, uint32_t count);
/* General and Advanced Timers Adds */
int (*getwidth)(FAR struct stm32_tim_dev_s *dev);
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
stm32_tim_channel_t mode);
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
@ -159,6 +166,7 @@ struct stm32_tim_ops_s
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
int (*checkint)(FAR struct stm32_tim_dev_s *dev, int source);
};
/****************************************************************************