From 2fca67c421d96026aedecb89cfae8c527ab6b8eb Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Feb 2020 15:46:52 -0600 Subject: [PATCH] arch/z80/src/ez80 and include/ez80: Add ez80f92 support The ez80f92 is similar to the currently supported ez80f91 except that is: 1. Has no PLL and has a maximum CPU frequency of only 20MHz 2. Has no Ethernet controller 3. Timers are different 4. Has no GPIO Port A 5. Timers are different 6. It comes in a smaller package and other small differences. This provided the architecture (only) support for the forthcoming z20x port. --- arch/z80/Kconfig | 5 + arch/z80/include/ez80/irq.h | 155 +++++++---- arch/z80/src/ez80/Make.defs | 6 +- arch/z80/src/ez80/ez80_spi.c | 9 +- arch/z80/src/ez80/ez80_vectors.asm | 93 +------ arch/z80/src/ez80/ez80f91_handlers.asm | 147 +++++++++++ arch/z80/src/ez80/ez80f91_spi.h | 7 +- arch/z80/src/ez80/ez80f92.h | 341 +++++++++++++++++++++++++ arch/z80/src/ez80/ez80f92_handlers.asm | 147 +++++++++++ arch/z80/src/ez80/ez80f92_init.asm | 170 ++++++++++++ 10 files changed, 929 insertions(+), 151 deletions(-) create mode 100644 arch/z80/src/ez80/ez80f91_handlers.asm create mode 100644 arch/z80/src/ez80/ez80f92.h create mode 100644 arch/z80/src/ez80/ez80f92_handlers.asm create mode 100644 arch/z80/src/ez80/ez80f92_init.asm diff --git a/arch/z80/Kconfig b/arch/z80/Kconfig index a41ba393f6..c922f28f7b 100644 --- a/arch/z80/Kconfig +++ b/arch/z80/Kconfig @@ -352,6 +352,7 @@ config ARCH_CHIP_Z8F6423 config ARCH_CHIP_EZ80F91 bool "EZ80F91" select ARCH_CHIP_EZ80 + select ARCH_CHIP_EZ80_HAVE_PLL ---help--- ZiLOG EZ80F91 (ez80 Acclaim) @@ -412,6 +413,10 @@ config ARCH_CHIP_EZ80 select MM_SMALL if EZ80_Z80MODE select ARCH_HAVE_PHY +config ARCH_CHIP_EZ80_HAVE_PLL + bool + default n + config ARCH_CHIP string default "z80" if ARCH_CHIP_Z80 diff --git a/arch/z80/include/ez80/irq.h b/arch/z80/include/ez80/irq.h index 08d8bfac55..80553a0e2b 100644 --- a/arch/z80/include/ez80/irq.h +++ b/arch/z80/include/ez80/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/z80/include/ez80/irq.h * - * Copyright (C) 2008-2009, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2008-2009, 2015, 2020 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,17 +33,13 @@ * ****************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h (via arch/irq.h) +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h (via arch/irq.h) */ #ifndef __ARCH_Z80_INCLUDE_EZ80_IRQ_H #define __ARCH_Z80_INCLUDE_EZ80_IRQ_H -#ifndef _EZ80F91 -# error "Only the EZ80F91 is currently supported" -#endif - /**************************************************************************** * Included Files ****************************************************************************/ @@ -58,61 +54,112 @@ /* ez80 Interrupt Numbers ***************************************************/ -#define EZ80_EMACRX_IRQ (0) /* Vector 0x40 */ -#define EZ80_EMACTX_IRQ (1) /* Vector 0x44 */ -#define EZ80_EMACSYS_IRQ (2) /* Vector 0x48 */ -#define EZ80_PLL_IRQ (3) /* Vector 0x4c */ -#define EZ80_FLASH_IRQ (4) /* Vector 0x50 */ +#if defined(CONFIG_ARCH_CHIP_EZ80F91) +# define EZ80_EMACRX_IRQ (0) /* Vector 0x40 */ +# define EZ80_EMACTX_IRQ (1) /* Vector 0x44 */ +# define EZ80_EMACSYS_IRQ (2) /* Vector 0x48 */ +# define EZ80_PLL_IRQ (3) /* Vector 0x4c */ +# define EZ80_FLASH_IRQ (4) /* Vector 0x50 */ -#define EZ80_TIMER0_IRQ (5) /* Vector 0x54 */ -#define EZ80_TIMER1_IRQ (6) /* Vector 0x58 */ -#define EZ80_TIMER2_IRQ (7) /* Vector 0x5c */ -#define EZ80_TIMER3_IRQ (8) /* Vector 0x60 */ +# define EZ80_TIMER0_IRQ (5) /* Vector 0x54 */ +# define EZ80_TIMER1_IRQ (6) /* Vector 0x58 */ +# define EZ80_TIMER2_IRQ (7) /* Vector 0x5c */ +# define EZ80_TIMER3_IRQ (8) /* Vector 0x60 */ -#define EZ80_RTC_IRQ (9) /* Vector 0x6C */ -#define EZ80_UART0_IRQ (10) /* Vector 0x70 */ -#define EZ80_UART1_IRQ (11) /* Vector 0x74 */ +# define EZ80_RTC_IRQ (9) /* Vector 0x6C */ +# define EZ80_UART0_IRQ (10) /* Vector 0x70 */ +# define EZ80_UART1_IRQ (11) /* Vector 0x74 */ -#define EZ80_I2C_IRQ (12) /* Vector 0x78 */ -#define EZ80_SPI_IRQ (13) /* Vector 0x7c */ +# define EZ80_I2C_IRQ (12) /* Vector 0x78 */ +# define EZ80_SPI_IRQ (13) /* Vector 0x7c */ -#define EZ80_PORTA0_IRQ (14) /* Vector 0x80 */ -#define EZ80_PORTA1_IRQ (15) /* Vector 0x84 */ -#define EZ80_PORTA2_IRQ (16) /* Vector 0x88 */ -#define EZ80_PORTA3_IRQ (17) /* Vector 0x8c */ -#define EZ80_PORTA4_IRQ (18) /* Vector 0x90 */ -#define EZ80_PORTA5_IRQ (19) /* Vector 0x94 */ -#define EZ80_PORTA6_IRQ (20) /* Vector 0x98 */ -#define EZ80_PORTA7_IRQ (21) /* Vector 0x9c */ +# define EZ80_PORTA0_IRQ (14) /* Vector 0x80 */ +# define EZ80_PORTA1_IRQ (15) /* Vector 0x84 */ +# define EZ80_PORTA2_IRQ (16) /* Vector 0x88 */ +# define EZ80_PORTA3_IRQ (17) /* Vector 0x8c */ +# define EZ80_PORTA4_IRQ (18) /* Vector 0x90 */ +# define EZ80_PORTA5_IRQ (19) /* Vector 0x94 */ +# define EZ80_PORTA6_IRQ (20) /* Vector 0x98 */ +# define EZ80_PORTA7_IRQ (21) /* Vector 0x9c */ -#define EZ80_PORTB0_IRQ (22) /* Vector 0xa0 */ -#define EZ80_PORTB1_IRQ (23) /* Vector 0xa4 */ -#define EZ80_PORTB2_IRQ (24) /* Vector 0xa8 */ -#define EZ80_PORTB3_IRQ (25) /* Vector 0xac */ -#define EZ80_PORTB4_IRQ (26) /* Vector 0xb0 */ -#define EZ80_PORTB5_IRQ (27) /* Vector 0xb4 */ -#define EZ80_PORTB6_IRQ (28) /* Vector 0xb8 */ -#define EZ80_PORTB7_IRQ (29) /* Vector 0xbc */ +# define EZ80_PORTB0_IRQ (22) /* Vector 0xa0 */ +# define EZ80_PORTB1_IRQ (23) /* Vector 0xa4 */ +# define EZ80_PORTB2_IRQ (24) /* Vector 0xa8 */ +# define EZ80_PORTB3_IRQ (25) /* Vector 0xac */ +# define EZ80_PORTB4_IRQ (26) /* Vector 0xb0 */ +# define EZ80_PORTB5_IRQ (27) /* Vector 0xb4 */ +# define EZ80_PORTB6_IRQ (28) /* Vector 0xb8 */ +# define EZ80_PORTB7_IRQ (29) /* Vector 0xbc */ -#define EZ80_PORTC0_IRQ (30) /* Vector 0xc0 */ -#define EZ80_PORTC1_IRQ (31) /* Vector 0xc4 */ -#define EZ80_PORTC2_IRQ (32) /* Vector 0xc8 */ -#define EZ80_PORTC3_IRQ (33) /* Vector 0xcc */ -#define EZ80_PORTC4_IRQ (34) /* Vector 0xd0 */ -#define EZ80_PORTC5_IRQ (35) /* Vector 0xd4 */ -#define EZ80_PORTC6_IRQ (36) /* Vector 0xd8 */ -#define EZ80_PORTC7_IRQ (37) /* Vector 0xdc */ +# define EZ80_PORTC0_IRQ (30) /* Vector 0xc0 */ +# define EZ80_PORTC1_IRQ (31) /* Vector 0xc4 */ +# define EZ80_PORTC2_IRQ (32) /* Vector 0xc8 */ +# define EZ80_PORTC3_IRQ (33) /* Vector 0xcc */ +# define EZ80_PORTC4_IRQ (34) /* Vector 0xd0 */ +# define EZ80_PORTC5_IRQ (35) /* Vector 0xd4 */ +# define EZ80_PORTC6_IRQ (36) /* Vector 0xd8 */ +# define EZ80_PORTC7_IRQ (37) /* Vector 0xdc */ -#define EZ80_PORTD0_IRQ (38) /* Vector 0xe0 */ -#define EZ80_PORTD1_IRQ (39) /* Vector 0xe4 */ -#define EZ80_PORTD2_IRQ (40) /* Vector 0xe8 */ -#define EZ80_PORTD3_IRQ (41) /* Vector 0xec */ -#define EZ80_PORTD4_IRQ (42) /* Vector 0xf0 */ -#define EZ80_PORTD5_IRQ (43) /* Vector 0xf4 */ -#define EZ80_PORTD6_IRQ (44) /* Vector 0xf8 */ -#define EZ80_PORTD7_IRQ (45) /* Vector 0xfc */ +# define EZ80_PORTD0_IRQ (38) /* Vector 0xe0 */ +# define EZ80_PORTD1_IRQ (39) /* Vector 0xe4 */ +# define EZ80_PORTD2_IRQ (40) /* Vector 0xe8 */ +# define EZ80_PORTD3_IRQ (41) /* Vector 0xec */ +# define EZ80_PORTD4_IRQ (42) /* Vector 0xf0 */ +# define EZ80_PORTD5_IRQ (43) /* Vector 0xf4 */ +# define EZ80_PORTD6_IRQ (44) /* Vector 0xf8 */ +# define EZ80_PORTD7_IRQ (45) /* Vector 0xfc */ + +# define NR_IRQS (46) +#elif defined(CONFIG_ARCH_CHIP_EZ80F92) || defined(CONFIG_ARCH_CHIP_EZ80F93) + +# /* Vectors 0x40-0x4c unused */ +# define EZ80_FLASH_IRQ (0) /* Vector 0x50 */ + +# define EZ80_TIMER0_IRQ (1) /* Vector 0x54 */ +# define EZ80_TIMER1_IRQ (2) /* Vector 0x58 */ +# define EZ80_TIMER2_IRQ (3) /* Vector 0x5c */ +# define EZ80_TIMER3_IRQ (4) /* Vector 0x60 */ +# define EZ80_TIMER4_IRQ (5) /* Vector 0x64 */ +# define EZ80_TIMER5_IRQ (6) /* Vector 0x68 */ + +# define EZ80_RTC_IRQ (7) /* Vector 0x6C */ +# define EZ80_UART0_IRQ (8) /* Vector 0x70 */ +# define EZ80_UART1_IRQ (9) /* Vector 0x74 */ + +# define EZ80_I2C_IRQ (10) /* Vector 0x78 */ +# define EZ80_SPI_IRQ (11) /* Vector 0x7c */ +# /* Vectors 0x80-0x9c unused */ + +# define EZ80_PORTB0_IRQ (12) /* Vector 0xa0 */ +# define EZ80_PORTB1_IRQ (13) /* Vector 0xa4 */ +# define EZ80_PORTB2_IRQ (14) /* Vector 0xa8 */ +# define EZ80_PORTB3_IRQ (15) /* Vector 0xac */ +# define EZ80_PORTB4_IRQ (16) /* Vector 0xb0 */ +# define EZ80_PORTB5_IRQ (17) /* Vector 0xb4 */ +# define EZ80_PORTB6_IRQ (18) /* Vector 0xb8 */ +# define EZ80_PORTB7_IRQ (19) /* Vector 0xbc */ + +# define EZ80_PORTC0_IRQ (20) /* Vector 0xc0 */ +# define EZ80_PORTC1_IRQ (21) /* Vector 0xc4 */ +# define EZ80_PORTC2_IRQ (22) /* Vector 0xc8 */ +# define EZ80_PORTC3_IRQ (23) /* Vector 0xcc */ +# define EZ80_PORTC4_IRQ (24) /* Vector 0xd0 */ +# define EZ80_PORTC5_IRQ (25) /* Vector 0xd4 */ +# define EZ80_PORTC6_IRQ (26) /* Vector 0xd8 */ +# define EZ80_PORTC7_IRQ (27) /* Vector 0xdc */ + +# define EZ80_PORTD0_IRQ (28) /* Vector 0xe0 */ +# define EZ80_PORTD1_IRQ (29) /* Vector 0xe4 */ +# define EZ80_PORTD2_IRQ (30) /* Vector 0xe8 */ +# define EZ80_PORTD3_IRQ (31) /* Vector 0xec */ +# define EZ80_PORTD4_IRQ (32) /* Vector 0xf0 */ +# define EZ80_PORTD5_IRQ (33) /* Vector 0xf4 */ +# define EZ80_PORTD6_IRQ (34) /* Vector 0xf8 */ +# define EZ80_PORTD7_IRQ (35) /* Vector 0xfc */ + +# define NR_IRQS (36) +#endif -#define NR_IRQS (46) #define EZ80_IRQ_SYSTIMER EZ80_TIMER0_IRQ /* IRQ Management Macros ****************************************************/ diff --git a/arch/z80/src/ez80/Make.defs b/arch/z80/src/ez80/Make.defs index c369fd57fe..8c6fe0d893 100644 --- a/arch/z80/src/ez80/Make.defs +++ b/arch/z80/src/ez80/Make.defs @@ -52,7 +52,11 @@ CHIP_ASRCS = ez80_startup.asm ez80_io.asm ez80_irqsave.asm CHIP_ASRCS += ez80_saveusercontext.asm ez80_restorecontext.asm ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y) -CHIP_ASRCS += ez80f91_init.asm +CHIP_ASRCS += ez80f91_init.asm ez80f91_handlers.asm +endif + +ifeq ($(CONFIG_ARCH_CHIP_EZ80F92),y) +CHIP_ASRCS += ez80f92_init.asm ez80f92_handlers.asm endif ifeq ($(CONFIG_ARCH_STACKDUMP),y) diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c index 27af964ae0..603bcf4ae8 100644 --- a/arch/z80/src/ez80/ez80_spi.c +++ b/arch/z80/src/ez80/ez80_spi.c @@ -56,13 +56,16 @@ #include "up_arch.h" #include "chip.h" -#include "ez80f91_spi.h" + +#if defined(CONFIG_ARCH_CHIP_EZ80F91) || defined(CONFIG_ARCH_CHIP_EZ80F92) +# include "ez80f91_spi.h" +#endif /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_EZ80F91 +#if defined(CONFIG_ARCH_CHIP_EZ80F91) || defined(CONFIG_ARCH_CHIP_EZ80F92) # define GPIOB_SPI_SS (1 << 2) /* Pin 2: /SS (not used by driver) */ # define GPIOB_SPI_SCK (1 << 3) /* Pin 3: SCK */ # define GPIOB_SPI_MISO (1 << 6) /* Pin 6: MISO */ @@ -614,7 +617,7 @@ FAR struct spi_dev_s *ez80_spibus_initialize(int port) * Select the alternate function for PB2-3,6-7: */ -#ifdef CONFIG_ARCH_CHIP_EZ80F91 +#if defined(CONFIG_ARCH_CHIP_EZ80F91) || defined(CONFIG_ARCH_CHIP_EZ80F92) regval = inp(EZ80_PB_DDR); regval |= GPIOB_SPI_PINSET; outp(EZ80_PB_DDR, regval); diff --git a/arch/z80/src/ez80/ez80_vectors.asm b/arch/z80/src/ez80/ez80_vectors.asm index ddcea31e0c..6476c6f3c2 100644 --- a/arch/z80/src/ez80/ez80_vectors.asm +++ b/arch/z80/src/ez80/ez80_vectors.asm @@ -1,7 +1,7 @@ ;************************************************************************** ; arch/z80/src/ez80/ez80_vectors.asm ; -; Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. +; Copyright (C) 2008-2009, 2020 Gregory Nutt. All rights reserved. ; Author: Gregory Nutt ; ; Redistribution and use in source and binary forms, with or without @@ -48,14 +48,11 @@ EZ80_H_FLAG EQU 10h ; Bit 4: Half carry flag EZ80_Z_FLAG EQU 40h ; Bit 5: Zero flag EZ80_S_FLAG EQU 80h ; Bit 7: Sign flag -;* The IRQ number to use for unused vectors - -EZ80_UNUSED EQU 40h - ;************************************************************************** ; Global Symbols Imported ;************************************************************************** + xref _ez80_handlers xref _ez80_startup xref _z80_doirq @@ -65,7 +62,6 @@ EZ80_UNUSED EQU 40h xdef _ez80_reset xdef _ez80_initvectors - xdef _ez80_handlers xdef _ez80_rstcommon xdef _ez80_initvectors xdef _ez80_vectable @@ -85,17 +81,6 @@ rstvector: macro jp.lil _ez80_startup endmac rstvector -; Define one interrupt handler - -irqhandler: macro vectno - ; Save AF on the stack, set the interrupt number and jump to the - ; common reset handling logic. - ; Offset 8: Return PC is already on the stack - push af ; Offset 7: AF (retaining flags) - ld a, #vectno ; A = vector number - jp _ez80_rstcommon ; Remaining RST handling is common - endmac irqhandler - ;************************************************************************** ; Reset entry points ;************************************************************************** @@ -132,79 +117,6 @@ _nmi: segment .STARTUP .assume ADL=1 -;************************************************************************** -; Interrupt Vector Handling -;************************************************************************** - - ; Symbol Val VecNo Addr - ;----------------- --- ----- ----- -_ez80_handlers: - irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 - handlersize equ $-_ez80_handlers - irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 - irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 - irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c - irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 - irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 - irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 - irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c - irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 - irqhandler EZ80_UNUSED ; 9 0x064 - irqhandler EZ80_UNUSED+1 ; 10 0x068 - irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C - irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 - irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 - irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 - irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c - irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 - irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 - irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 - irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c - irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 - irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 - irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 - irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c - irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 - irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 - irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 - irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac - irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 - irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 - irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 - irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc - irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 - irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 - irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 - irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc - irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 - irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 - irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 - irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc - irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 - irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 - irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 - irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec - irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 - irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 - irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 - irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc - irqhandler EZ80_UNUSED+1 ; 48 0x100 - irqhandler EZ80_UNUSED+2 ; 49 0x104 - irqhandler EZ80_UNUSED+3 ; 50 0x108 - irqhandler EZ80_UNUSED+4 ; 51 0x10c - irqhandler EZ80_UNUSED+5 ; 52 0x110 - irqhandler EZ80_UNUSED+6 ; 53 0x114 - irqhandler EZ80_UNUSED+7 ; 54 0x118 - irqhandler EZ80_UNUSED+8 ; 55 0x11c - irqhandler EZ80_UNUSED+9 ; 56 0x120 - irqhandler EZ80_UNUSED+10 ; 57 0x124 - irqhandler EZ80_UNUSED+11 ; 58 0x128 - irqhandler EZ80_UNUSED+12 ; 59 0x12c - irqhandler EZ80_UNUSED+13 ; 60 0x130 - irqhandler EZ80_UNUSED+14 ; 61 0x134 - irqhandler EZ80_UNUSED+15 ; 62 0x138 - irqhandler EZ80_UNUSED+16 ; 63 0x13c - ;************************************************************************** ; Common Interrupt handler ;************************************************************************** @@ -340,3 +252,4 @@ _ez80_vecreserve: ds 64 _ez80_vectable: ds NVECTORS * 4 + end diff --git a/arch/z80/src/ez80/ez80f91_handlers.asm b/arch/z80/src/ez80/ez80f91_handlers.asm new file mode 100644 index 0000000000..ec907c6ee0 --- /dev/null +++ b/arch/z80/src/ez80/ez80f91_handlers.asm @@ -0,0 +1,147 @@ +;************************************************************************** +; arch/z80/src/ez80/ez80f91_handlers.asm +; +; Copyright (C) 2008-2009, 2020 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Constants +;************************************************************************** + +; The IRQ number to use for unused vectors + +EZ80_UNUSED EQU 40h + +;************************************************************************** +; Global Symbols Imported +;************************************************************************** + + xref _ez80_rstcommon + +;************************************************************************** +; Global Symbols Exported +;************************************************************************** + + xdef _ez80_handlers + +;************************************************************************** +; Macros +;************************************************************************** + +; Define one interrupt handler + +irqhandler: macro vectno + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #vectno ; A = vector number + jp _ez80_rstcommon ; Remaining RST handling is common + endmac irqhandler + +;************************************************************************** +; Interrupt Vector Handlers +;************************************************************************** + + define .STARTUP, space = ROM + segment .STARTUP + .assume ADL=1 + + ; Symbol Val VecNo Addr + ;----------------- --- ----- ----- +_ez80_handlers: + irqhandler 0 ; EZ80_EMACRX_IRQ 0 0 0x040 + handlersize equ $-_ez80_handlers + irqhandler 1 ; EZ80_EMACTX_IRQ 1 1 0x044 + irqhandler 2 ; EZ80_EMACSYS_IRQ 2 2 0x048 + irqhandler 3 ; EZ80_PLL_IRQ 3 3 0x04c + irqhandler 4 ; EZ80_FLASH_IRQ 4 4 0x050 + irqhandler 5 ; EZ80_TIMER0_IRQ 5 5 0x054 + irqhandler 6 ; EZ80_TIMER1_IRQ 6 6 0x058 + irqhandler 7 ; EZ80_TIMER2_IRQ 7 7 0x05c + irqhandler 8 ; EZ80_TIMER3_IRQ 8 8 0x060 + irqhandler EZ80_UNUSED ; 9 0x064 + irqhandler EZ80_UNUSED + 1 ; 10 0x068 + irqhandler 9 ; EZ80_RTC_IRQ 9 11 0x06C + irqhandler 10 ; EZ80_UART0_IRQ 10 12 0x070 + irqhandler 11 ; EZ80_UART1_IRQ 11 13 0x074 + irqhandler 12 ; EZ80_I2C_IRQ 12 14 0x078 + irqhandler 13 ; EZ80_SPI_IRQ 13 15 0x07c + irqhandler 14 ; EZ80_PORTA0_IRQ 14 16 0x080 + irqhandler 15 ; EZ80_PORTA1_IRQ 15 17 0x084 + irqhandler 16 ; EZ80_PORTA2_IRQ 16 18 0x088 + irqhandler 17 ; EZ80_PORTA3_IRQ 17 19 0x08c + irqhandler 18 ; EZ80_PORTA4_IRQ 18 20 0x090 + irqhandler 19 ; EZ80_PORTA5_IRQ 19 21 0x094 + irqhandler 20 ; EZ80_PORTA6_IRQ 20 22 0x098 + irqhandler 21 ; EZ80_PORTA7_IRQ 21 23 0x09c + irqhandler 22 ; EZ80_PORTB0_IRQ 22 24 0x0a0 + irqhandler 23 ; EZ80_PORTB1_IRQ 23 25 0x0a4 + irqhandler 24 ; EZ80_PORTB2_IRQ 24 26 0x0a8 + irqhandler 25 ; EZ80_PORTB3_IRQ 25 27 0x0ac + irqhandler 26 ; EZ80_PORTB4_IRQ 26 28 0x0b0 + irqhandler 27 ; EZ80_PORTB5_IRQ 27 29 0x0b4 + irqhandler 28 ; EZ80_PORTB6_IRQ 28 20 0x0b8 + irqhandler 29 ; EZ80_PORTB7_IRQ 29 21 0x0bc + irqhandler 30 ; EZ80_PORTC0_IRQ 30 22 0x0c0 + irqhandler 31 ; EZ80_PORTC1_IRQ 31 23 0x0c4 + irqhandler 32 ; EZ80_PORTC2_IRQ 32 24 0x0c8 + irqhandler 33 ; EZ80_PORTC3_IRQ 33 25 0x0cc + irqhandler 34 ; EZ80_PORTC4_IRQ 34 26 0x0d0 + irqhandler 35 ; EZ80_PORTC5_IRQ 35 27 0x0d4 + irqhandler 36 ; EZ80_PORTC6_IRQ 36 28 0x0d8 + irqhandler 37 ; EZ80_PORTC7_IRQ 37 29 0x0dc + irqhandler 38 ; EZ80_PORTD0_IRQ 38 40 0x0e0 + irqhandler 39 ; EZ80_PORTD1_IRQ 39 41 0x0e4 + irqhandler 40 ; EZ80_PORTD2_IRQ 40 42 0x0e8 + irqhandler 41 ; EZ80_PORTD3_IRQ 41 43 0x0ec + irqhandler 42 ; EZ80_PORTD4_IRQ 42 44 0x0f0 + irqhandler 43 ; EZ80_PORTD5_IRQ 43 45 0x0f4 + irqhandler 44 ; EZ80_PORTD6_IRQ 44 46 0x0f8 + irqhandler 45 ; EZ80_PORTD7_IRQ 45 47 0x0fc + irqhandler EZ80_UNUSED + 2 ; 48 0x100 + irqhandler EZ80_UNUSED + 3 ; 49 0x104 + irqhandler EZ80_UNUSED + 4 ; 50 0x108 + irqhandler EZ80_UNUSED + 5 ; 51 0x10c + irqhandler EZ80_UNUSED + 6 ; 52 0x110 + irqhandler EZ80_UNUSED + 7 ; 53 0x114 + irqhandler EZ80_UNUSED + 8 ; 54 0x118 + irqhandler EZ80_UNUSED + 9 ; 55 0x11c + irqhandler EZ80_UNUSED + 10 ; 56 0x120 + irqhandler EZ80_UNUSED + 11 ; 57 0x124 + irqhandler EZ80_UNUSED + 12 ; 58 0x128 + irqhandler EZ80_UNUSED + 13 ; 59 0x12c + irqhandler EZ80_UNUSED + 14 ; 60 0x130 + irqhandler EZ80_UNUSED + 15 ; 61 0x134 + irqhandler EZ80_UNUSED + 16 ; 62 0x138 + irqhandler EZ80_UNUSED + 17 ; 63 0x13c + end diff --git a/arch/z80/src/ez80/ez80f91_spi.h b/arch/z80/src/ez80/ez80f91_spi.h index 9e8da0f6fa..c1f9b635db 100644 --- a/arch/z80/src/ez80/ez80f91_spi.h +++ b/arch/z80/src/ez80/ez80f91_spi.h @@ -67,12 +67,13 @@ #define SPI_CTL_MASTEREN (1 << 4) /* Bit 4: 1=SPI operates as a master */ #define SPI_CTL_CPOL (1 << 3) /* Bit 3: 1=Master SCK pin idles in a high (1) state */ #define SPI_CTL_CPHA (1 << 2) /* Bit 2: 1=SS remains Low to transfer any number of data bytes */ + /* Bits 0-1: Reserved */ /* SR Register Definitions */ -#define SPI_SR_SPIF (1 << 7) /* Bit x: 1=SPI data transfer is finished */ -#define SPI_SR_WCOL (1 << 6) /* Bit x: 1=SPI write collision is detected*/ -#define SPI_SR_MODF (1 << 4) /* Bit x: 1=Mode fault (multimaster conflict) is detected */ +#define SPI_SR_SPIF (1 << 7) /* Bit 7: 1=SPI data transfer is finished */ +#define SPI_SR_WCOL (1 << 6) /* Bit 6: 1=SPI write collision is detected*/ +#define SPI_SR_MODF (1 << 4) /* Bit 4: 1=Mode fault (multimaster conflict) is detected */ /* RBR/TSR Register Definitions */ diff --git a/arch/z80/src/ez80/ez80f92.h b/arch/z80/src/ez80/ez80f92.h new file mode 100644 index 0000000000..c98e07a35f --- /dev/null +++ b/arch/z80/src/ez80/ez80f92.h @@ -0,0 +1,341 @@ +/************************************************************************************ + * arch/z80/src/ez80/ez80f92.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ************************************************************************************/ + +#ifndef __ARCH_Z80_SRC_EZ80_EZ80F92_H +#define __ARCH_Z80_SRC_EZ80_EZ80F92_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include "ez80f91_emac.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory map ***********************************************************************/ + +#define EZ80_ONCHIPFLASH 0x000000 /* CS0: 128Kb of on-chip flash */ +#define EZ80_OFFCHIPCS0 0x400000 /* CS0: Off chip use (usually flash) */ +#define EZ80_OFFCHIPCS2 0x800000 /* CS2: Off chip use (e.g. memory mapped I/O) */ +#define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */ +#define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (8Kb) on reset */ + +/* Product ID Registers ************************************************************/ + +#define EZ80_ZDI_ID_L 0x00 +#define EZ80_ZDI_ID_H 0x01 +#define EZ80_ZDI_ID_REV 0x02 + +/* Timer Registers *****************************************************************/ + +#define EZ80_TMR0_CTL 0x80 /* RW: Timer 0 control register */ +#define EZ80_TMR0_DRL 0x81 /* R : Timer 0 data register (low) */ +#define EZ80_TMR0_DRH 0x82 /* R : Timer 0 data register (high) */ +#define EZ80_TMR0_RRL 0x81 /* W: Timer 0 reload register (low) */ +#define EZ80_TMR0_RRH 0x82 /* W: Timer 0 reload register (high) */ + +#define EZ80_TMR1_CTL 0x83 /* RW: Timer 1 control register */ +#define EZ80_TMR1_DRL 0x84 /* R : Timer 1 data register (low) */ +#define EZ80_TMR1_DRH 0x85 /* R : Timer 1 data register (high) */ +#define EZ80_TMR1_RRL 0x84 /* W: Timer 1 reload register (low) */ +#define EZ80_TMR1_RRH 0x85 /* W: Timer 1 reload register (high) */ + +#define EZ80_TMR2_CTL 0x86 /* RW: Timer 2 control register */ +#define EZ80_TMR2_DRL 0x87 /* R : Timer 2 data register (low) */ +#define EZ80_TMR2_DRH 0x88 /* R : Timer 2 data register (high) */ +#define EZ80_TMR2_RRL 0x87 /* W: Timer 2 reload register (low) */ +#define EZ80_TMR2_RRH 0x88 /* W: Timer 2 reload register (high) */ + +#define EZ80_TMR3_CTL 0x89 /* RW: Timer 3 control register */ +#define EZ80_TMR3_DRL 0x8a /* R : Timer 3 data register (low) */ +#define EZ80_TMR3_DRH 0x8b /* R : Timer 3 data register (high) */ +#define EZ80_TMR3_RRL 0x8a /* W: Timer 3 reload register (low) */ +#define EZ80_TMR3_RRH 0x8b /* W: Timer 3 reload register (high) */ + +#define EZ80_TMR4_CTL 0x8c /* RW: Timer 4 control register */ +#define EZ80_TMR4_DRL 0x8d /* R : Timer 4 data register (low) */ +#define EZ80_TMR4_DRH 0x8e /* R : Timer 4 data register (high) */ +#define EZ80_TMR4_RRL 0x8d /* W: Timer 4 reload register (low) */ +#define EZ80_TMR4_RRH 0x8e /* W: Timer 4 reload register (high) */ + +#define EZ80_TMR5_CTL 0x8f /* RW: Timer 5 control register */ +#define EZ80_TMR5_DRL 0x90 /* R : Timer 5 data register (low) */ +#define EZ80_TMR5_DRH 0x91 /* R : Timer 5 data register (high) */ +#define EZ80_TMR5_RRL 0x90 /* W: Timer 5 reload register (low) */ +#define EZ80_TMR5_RRH 0x91 /* W: Timer 5 reload register (high) */ + +#define EZ80_TMR_ISS 0x92 /* Timer input source selection register */ + +/* TMR0/1/2/3 CTL Register Bit Definitions *******************************************/ + +#define EZ80_TMRCTL_IRQ 0x80 /* Bit 7: Generate interrupt request */ +#define EZ80_TMRCTL_EN 0x40 /* Bit 6: Enable timer interrupt requests */ + /* Bit 5: Reserved */ +#define EZ80_TMRCTL_TIMCONT 0x10 /* Bit 4: Continuous mode */ +#define EZ80_TMRCTL_CLKDIV 0x18 /* Bits 2-3: Timer input clock divider */ +# define EZ80_TMRCLKDIV_4 0x00 /* 00: 4 */ +# define EZ80_TMRCLKDIV_16 0x08 /* 01: 16 */ +# define EZ80_TMRCLKDIV_64 0x10 /* 10: 64 */ +# define EZ80_TMRCLKDIV_256 0x18 /* 11: 256 */ +#define EZ80_TMRCTL_RSTEN 0x02 /* Bit 1: Reload and start function enabled */ +#define EZ80_TMRCTL_TIMEN 0x01 /* Bit 0: Programmable reload timer enabled */ + +/* WDT Registers *********************************************************************/ + +#define EZ80_WDT_CTL 0x93 +#define EZ80_WDT_RR 0x94 + +/* GPIO Registers ********************************************************************/ + +#define EZ80_PB_DR 0x9a +#define EZ80_PB_DDR 0x9b +#define EZ80_PB_ALT1 0x9c +#define EZ80_PB_ALT2 0x9d +#define EZ80_PC_DR 0x9e +#define EZ80_PC_DDR 0x9f +#define EZ80_PC_ALT1 0xa0 +#define EZ80_PC_ALT2 0xa1 +#define EZ80_PD_DR 0xa2 +#define EZ80_PD_DDR 0xa3 +#define EZ80_PD_ALT1 0xa4 +#define EZ80_PD_ALT2 0xa5 + +/* CS Registers **********************************************************************/ + +#define EZ80_CS0_LBR 0xa8 +#define EZ80_CS0_UBR 0xa9 +#define EZ80_CS0_CTL 0xaa +#define EZ80_CS1_LBR 0xab +#define EZ80_CS1_UBR 0xac +#define EZ80_CS1_CTL 0xad +#define EZ80_CS2_LBR 0xae +#define EZ80_CS2_UBR 0xaf +#define EZ80_CS2_CTL 0xb0 +#define EZ80_CS3_LBR 0xb1 +#define EZ80_CS3_UBR 0xb2 +#define EZ80_CS3_CTL 0xb3 + +/* RAMCTL registers ******************************************************************/ + +#define EZ80_RAM_CTL 0xb4 +#define EZ80_RAM_ADDR_U 0xb5 + +/* RAMCTL bit definitions ************************************************************/ + +#define RAMCTL_ERAMEN (1 << 6) /* Bit 7: 1=On chip EMAC SRAM is enabled */ +#define RAMCTL_GPRAMEN (1 << 7) /* Bit 7: 1=On chip GP SRAM is enabled */ + +/* SPI Registers *********************************************************************/ + +#define EZ80_SPI_BRG_L 0xb8 +#define EZ80_SPI_BRG_H 0xb9 +#define EZ80_SPI_CTL 0xba +#define EZ80_SPI_SR 0xbb +#define EZ80_SPI_RBR 0xbc +#define EZ80_SPI_TSR 0xbc + +/* Infrared Encoder/Decoder Block ****************************************************/ + +#define EZ80_IR_CTL 0xbf /* Infrared Encoder/Decoder Control */ + +/* UART Register Offsets *************************************************************/ + /* DLAB=0: */ +#define EZ80_UART_THR 0x00 /* W: UART Transmit holding register */ +#define EZ80_UART_RBR 0x00 /* R : UART Receive buffer register */ +#define EZ80_UART_IER 0x01 /* RW: UART Interrupt enable register */ + /* DLAB=1: */ +#define EZ80_UART_BRG 0x00 /* RW: UART Baud rate generator register */ +#define EZ80_UART_BRGL 0x00 /* RW: UART Baud rate generator register (low) */ +#define EZ80_UART_BRGH 0x01 /* RW: UART Baud rate generator register (high) */ + /* DLAB=N/A: */ +#define EZ80_UART_IIR 0x02 /* R : UART Interrupt identification register */ +#define EZ80_UART_FCTL 0x02 /* W: UART FIFO control register */ +#define EZ80_UART_LCTL 0x03 /* RW: UART Line control register */ +#define EZ80_UART_MCTL 0x04 /* RW: UART Modem control register */ +#define EZ80_UART_LSR 0x05 /* R : UART Line status register */ +#define EZ80_UART_MSR 0x06 /* R : UART Modem status register */ +#define EZ80_UART_SPR 0x07 /* RW: UART Scratchpad register */ + +/* UART0/1 Base Register Addresses **************************************************/ + +#define EZ80_UART0_BASE 0xc0 +#define EZ80_UART1_BASE 0xd0 + +/* UART0/1 IER register bits ********************************************************/ + +#define EZ80_UARTEIR_INTMASK 0x1f /* Bits 5-7: Reserved */ +#define EZ80_UARTEIR_TCIE 0x10 /* Bit 4: Transmission complete interrupt */ +#define EZ80_UARTEIR_MIIE 0x08 /* Bit 3: Modem status input interrupt */ +#define EZ80_UARTEIR_LSIE 0x04 /* Bit 2: Line status interrupt */ +#define EZ80_UARTEIR_TIE 0x02 /* Bit 1: Transmit interrupt */ +#define EZ80_UARTEIR_RIE 0x01 /* Bit 0: Receive interrupt */ + +/* UART0/1 IIR register bits ********************************************************/ + +#define EZ80_UARTIIR_FSTS 0xc0 /* Bits 6-7: FIFO enable */ +#define EZ80_UARTIIR_FDIS 0x00 /* 00: FIFO disabled */ +#define EZ80_UARTIIR_FRXDIS 0x80 /* 10: Rx FIFO disabled */ +#define EZ80_UARTIIR_FEN 0xc0 /* 11: FIFO enabled */ + /* Bits 4-5: Reserved */ +#define EZ80_UARTIIR_INSTS 0x0e /* Bits 1-3: Interrupt status code */ +# define EZ80_UARTINSTS_CTO 0x0c /* 110: Character timeout */ +# define EZ80_UARTINSTS_TC 0x0a /* 101: Transmission complete */ +# define EZ80_UARTINSTS_RLS 0x06 /* 011: Receiver line status */ +# define EZ80_UARTINSTS_RDR 0x04 /* 010: Receive data ready or trigger level */ +# define EZ80_UARTINSTS_TBE 0x02 /* 001: Transmisson buffer empty */ +# define EZ80_UARTINSTS_MS 0x00 /* 000: Modem status */ +#define EZ80_UARTIIR_INTBIT 0x01 /* Bit 0: (NOT) Active interrupt source */ +#define EZ80_UARTIIR_CAUSEMASK 0x0f + +/* UART0/1 FCTL register bits *******************************************************/ + +#define EZ80_UARTFCTL_TRIG 0xc0 /* Bits 6-7: UART receive FIFO trigger level */ +# define EZ80_UARTTRIG_1 0x00 /* 00: Receive FIFO trigger level=1 */ +# define EZ80_UARTTRIG_4 0x40 /* 01: Receive FIFO trigger level=4 */ +# define EZ80_UARTTRIG_8 0x80 /* 10: Receive FIFO trigger level=8 */ +# define EZ80_UARTTRIG_14 0xc0 /* 11: Receive FIFO trigger level=14 */ + /* Bit 3-5: Reserved */ +#define EZ80_UARTFCTL_CLRTxF 0x04 /* Bit 2: Transmit enable */ +#define EZ80_UARTFCTL_CLRRxF 0x02 /* Bit 1: Receive enable */ +#define EZ80_UARTFCTL_FIFOEN 0x01 /* Bit 0: Enable receive/transmit FIFOs */ + +/* UART0/1 LCTL register bits *******************************************************/ + +#define EZ80_UARTLCTL_DLAB 0x80 /* Bit 7: Enable access to baud rate generator */ +#define EZ80_UARTLCTL_SB 0x40 /* Bit 6: Send break */ +#define EZ80_UARTLCTL_FPE 0x20 /* Bit 5: Force parity error */ +#define EZ80_UARTLCTL_EPS 0x10 /* Bit 4: Even parity select */ +#define EZ80_UARTLCTL_PEN 0x08 /* Bit 3: Parity enable */ +#define EZ80_UARTLCTL_2STOP 0x04 /* Bit 2: 2 stop bits */ +#define EZ80_UARTLCTL_CHAR 0x03 /* Bits 0-2: Number of data bits */ +# define EZ80_UARTCHAR_5BITS 0x00 /* 00: 5 data bits */ +# define EZ80_UARTCHAR_6BITS 0x01 /* 01: 6 data bits */ +# define EZ80_UARTCHAR_7BITS 0x02 /* 10: 7 data bits */ +# define EZ80_UARTCHAR_8BITS 0x03 /* 11: 8 data bits */ + +#define EZ80_UARTLCTL_MASK 0x3f + +/* UART0/1 MCTL register bits *******************************************************/ + + /* Bits 6-7: Reserved */ +#define EZ80_UARTMCTL_MDM 0x20 /* Bit 5: Multi-drop mode enable */ +#define EZ80_UARTMCTL_LOOP 0x10 /* Bit 4: Loopback mode enable */ +#define EZ80_UARTMCTL_OUT2 0x08 /* Bit 3: (loopback mode only) */ +#define EZ80_UARTMCTL_OUT1 0x04 /* Bit 2: (loopback mode only) */ +#define EZ80_UARTMCTL_RTS 0x02 /* Bit 1: Request to send */ +#define EZ80_UARTMCTL_DTR 0x01 /* Bit 0: Data termnal read */ + +/* UART0/1 LSR register bits ********************************************************/ + +#define EZ80_UARTLSR_ERR 0x80 /* Bit 7: Error detected in FIFO */ +#define EZ80_UARTLSR_TEMT 0x40 /* Bit 6: Transmit FIFO empty and idle */ +#define EZ80_UARTLSR_THRE 0x20 /* Bit 5: Transmit FIFO empty */ +#define EZ80_UARTLSR_BI 0x10 /* Bit 4: Break on input */ +#define EZ80_UARTLSR_FE 0x08 /* Bit 3: Framing error */ +#define EZ80_UARTLSR_PE 0x04 /* Bit 2: Parity error */ +#define EZ80_UARTLSR_OE 0x02 /* Bit 1: Overrun error */ +#define EZ80_UARTLSR_DR 0x01 /* Bit 0: Data ready */ + +/* UART0/1 MSR register bits ********************************************************/ + +#define EZ80_UARTMSR_DCD 0x80 /* Bit 7: Data carrier detect */ +#define EZ80_UARTMSR_RI 0x40 /* Bit 6: Ring indicator */ +#define EZ80_UARTMSR_DSR 0x20 /* Bit 5: Data set ready */ +#define EZ80_UARTMSR_CTS 0x10 /* Bit 4: Clear to send */ +#define EZ80_UARTMSR_DDCD 0x08 /* Bit 3: Delta on DCD input */ +#define EZ80_UARTMSR_TERI 0x04 /* Bit 2: Trailing edge change on RI */ +#define EZ80_UARTMSR_DDSR 0x02 /* Bit 1: Delta on DSR input */ +#define EZ80_UARTMSR_DCTS 0x01 /* Bit 0: Delta on CTS input */ + +/* I2C Registers *******************************************************************/ + +#define EZ80_I2C_SAR 0xc8 +#define EZ80_I2C_XSAR 0xc9 +#define EZ80_I2C_DR 0xca +#define EZ80_I2C_CTL 0xcb +#define EZ80_I2C_SR 0xcc +#define EZ80_I2C_CCR 0xcc +#define EZ80_I2C_SRR 0xcd + +/* CLK Registers *******************************************************************/ + +#define EZ80_CLK_PPD1 0xdb +#define EZ80_CLK_PPD2 0xdc + +/* RTC Registers *******************************************************************/ + +#define EZ80_RTC_SEC 0xe0 +#define EZ80_RTC_MIN 0xe1 +#define EZ80_RTC_HRS 0xe2 +#define EZ80_RTC_DOW 0xe3 +#define EZ80_RTC_DOM 0xe4 +#define EZ80_RTC_MON 0xe5 +#define EZ80_RTC_YR 0xe6 +#define EZ80_RTC_CEN 0xe7 +#define EZ80_RTC_ASEC 0xe8 +#define EZ80_RTC_AMIN 0xe9 +#define EZ80_RTC_AHRS 0xea +#define EZ80_RTC_ADOW 0xeb +#define EZ80_RTC_ACTRL 0xec +#define EZ80_RTC_CTRL 0xed + +/* CSBMC Registers *****************************************************************/ + +#define EZ80_CS0_BMC 0xf0 +#define EZ80_CS1_BMC 0xf1 +#define EZ80_CS2_BMC 0xf2 +#define EZ80_CS3_BMC 0xf3 + +/* FLASH Registers *****************************************************************/ + +#define EZ80_FLASH_KEY 0xf5 +#define EZ80_FLASH_DATA 0xf6 +#define EZ80_FLASH_ADDR_U 0xf7 +#define EZ80_FLASH_CTRL 0xf8 +#define EZ80_FLASH_FDIV 0xf9 +#define EZ80_FLASH_PROT 0xfa +#define EZ80_FLASH_INTC 0xfb +#define EZ80_FLASH_PAGE 0xfc +#define EZ80_FLASH_ROW 0xfd +#define EZ80_FLASH_COL 0xfe +#define EZ80_FLASH_PGCTL 0xff + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_Z80_SRC_EZ80_EZ80F92_H */ diff --git a/arch/z80/src/ez80/ez80f92_handlers.asm b/arch/z80/src/ez80/ez80f92_handlers.asm new file mode 100644 index 0000000000..cff752236e --- /dev/null +++ b/arch/z80/src/ez80/ez80f92_handlers.asm @@ -0,0 +1,147 @@ +;************************************************************************** +; arch/z80/src/ez80/ez80f91_handlers.asm +; +; Copyright (C) 2008-2009, 2020 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Constants +;************************************************************************** + +; The IRQ number to use for unused vectors + +EZ80_UNUSED EQU 40h + +;************************************************************************** +; Global Symbols Imported +;************************************************************************** + + xref _ez80_rstcommon + +;************************************************************************** +; Global Symbols Exported +;************************************************************************** + + xdef _ez80_handlers + +;************************************************************************** +; Macros +;************************************************************************** + +; Define one interrupt handler + +irqhandler: macro vectno + ; Save AF on the stack, set the interrupt number and jump to the + ; common reset handling logic. + ; Offset 8: Return PC is already on the stack + push af ; Offset 7: AF (retaining flags) + ld a, #vectno ; A = vector number + jp _ez80_rstcommon ; Remaining RST handling is common + endmac irqhandler + +;************************************************************************** +; Interrupt Vector Handlers +;************************************************************************** + + define .STARTUP, space = ROM + segment .STARTUP + .assume ADL=1 + + ; Symbol Val VecNo Addr + ;----------------- --- ----- ----- +_ez80_handlers: + irqhandler EZ80_UNUSED ; 0 0x040 + handlersize equ $-_ez80_handlers + irqhandler EZ80_UNUSED+1 ; 1 0x044 + irqhandler EZ80_UNUSED+2 ; 2 0x045 + irqhandler EZ80_UNUSED+3 ; 3 0x04c + irqhandler 0 ; EZ80_FLASH_IRQ 0 4 0x050 + irqhandler 1 ; EZ80_TIMER0_IRQ 1 5 0x054 + irqhandler 2 ; EZ80_TIMER1_IRQ 2 6 0x058 + irqhandler 3 ; EZ80_TIMER2_IRQ 3 7 0x05c + irqhandler 4 ; EZ80_TIMER3_IRQ 4 8 0x060 + irqhandler 5 ; EZ80_TIMER4_IRQ 5 9 0x064 + irqhandler 6 ; EZ80_TIMER5_IRQ 6 10 0x068 + irqhandler 7 ; EZ80_RTC_IRQ 7 11 0x06C + irqhandler 8 ; EZ80_UART0_IRQ 8 12 0x070 + irqhandler 9 ; EZ80_UART1_IRQ 9 13 0x074 + irqhandler 10 ; EZ80_I2C_IRQ 10 14 0x078 + irqhandler 11 ; EZ80_SPI_IRQ 11 15 0x07c + irqhandler EZ80_UNUSED+4 ; 16 0x080 + irqhandler EZ80_UNUSED+5 ; 17 0x084 + irqhandler EZ80_UNUSED+6 ; 18 0x088 + irqhandler EZ80_UNUSED+7 ; 19 0x08c + irqhandler EZ80_UNUSED+8 ; 16 0x080 + irqhandler EZ80_UNUSED+9 ; 17 0x094 + irqhandler EZ80_UNUSED+10 ; 18 0x098 + irqhandler EZ80_UNUSED+11 ; 19 0x09c + irqhandler 12 ; EZ80_PORTB0_IRQ 12 24 0x0a0 + irqhandler 13 ; EZ80_PORTB1_IRQ 13 25 0x0a4 + irqhandler 14 ; EZ80_PORTB2_IRQ 14 26 0x0a8 + irqhandler 15 ; EZ80_PORTB3_IRQ 15 27 0x0ac + irqhandler 16 ; EZ80_PORTB4_IRQ 16 28 0x0b0 + irqhandler 17 ; EZ80_PORTB5_IRQ 17 29 0x0b4 + irqhandler 18 ; EZ80_PORTB6_IRQ 18 20 0x0b8 + irqhandler 19 ; EZ80_PORTB7_IRQ 19 21 0x0bc + irqhandler 20 ; EZ80_PORTC0_IRQ 20 22 0x0c0 + irqhandler 21 ; EZ80_PORTC1_IRQ 21 23 0x0c4 + irqhandler 22 ; EZ80_PORTC2_IRQ 22 24 0x0c8 + irqhandler 23 ; EZ80_PORTC3_IRQ 23 25 0x0cc + irqhandler 24 ; EZ80_PORTC4_IRQ 24 26 0x0d0 + irqhandler 25 ; EZ80_PORTC5_IRQ 25 27 0x0d4 + irqhandler 26 ; EZ80_PORTC6_IRQ 26 28 0x0d8 + irqhandler 27 ; EZ80_PORTC7_IRQ 27 29 0x0dc + irqhandler 28 ; EZ80_PORTD0_IRQ 28 40 0x0e0 + irqhandler 29 ; EZ80_PORTD1_IRQ 29 41 0x0e4 + irqhandler 30 ; EZ80_PORTD2_IRQ 30 42 0x0e8 + irqhandler 31 ; EZ80_PORTD3_IRQ 31 43 0x0ec + irqhandler 32 ; EZ80_PORTD4_IRQ 32 44 0x0f0 + irqhandler 33 ; EZ80_PORTD5_IRQ 33 45 0x0f4 + irqhandler 34 ; EZ80_PORTD6_IRQ 34 46 0x0f8 + irqhandler 35 ; EZ80_PORTD7_IRQ 35 47 0x0fc + irqhandler EZ80_UNUSED+13 ; 48 0x100 + irqhandler EZ80_UNUSED+14 ; 49 0x104 + irqhandler EZ80_UNUSED+15 ; 50 0x108 + irqhandler EZ80_UNUSED+16 ; 51 0x10c + irqhandler EZ80_UNUSED+17 ; 52 0x110 + irqhandler EZ80_UNUSED+18 ; 53 0x114 + irqhandler EZ80_UNUSED+19 ; 54 0x118 + irqhandler EZ80_UNUSED+20 ; 55 0x11c + irqhandler EZ80_UNUSED+21 ; 56 0x120 + irqhandler EZ80_UNUSED+22 ; 57 0x124 + irqhandler EZ80_UNUSED+23 ; 58 0x128 + irqhandler EZ80_UNUSED+24 ; 59 0x12c + irqhandler EZ80_UNUSED+25 ; 60 0x130 + irqhandler EZ80_UNUSED+26 ; 61 0x134 + irqhandler EZ80_UNUSED+27 ; 62 0x138 + irqhandler EZ80_UNUSED+28 ; 63 0x13c + end diff --git a/arch/z80/src/ez80/ez80f92_init.asm b/arch/z80/src/ez80/ez80f92_init.asm new file mode 100644 index 0000000000..4afd698a3c --- /dev/null +++ b/arch/z80/src/ez80/ez80f92_init.asm @@ -0,0 +1,170 @@ +;************************************************************************** +; arch/z80/src/ez80/ez80f92_init.asm +; +; Copyright (C) 2008, 2020 Gregory Nutt. All rights reserved. +; Author: Gregory Nutt +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions +; are met: +; +; 1. Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in +; the documentation and/or other materials provided with the +; distribution. +; 3. Neither the name NuttX nor the names of its contributors may be +; used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +; "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +; FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +; COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +; OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +; AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +; ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +;************************************************************************** + +;************************************************************************** +; Included Files +;************************************************************************** + + include "ez80F92.inc" + +;************************************************************************** +; Global symbols used +;************************************************************************** + +; Exported symbols + xdef _ez80_init + xdef _ez80_initsysclk + +; Imported symbols + xref __CS0_LBR_INIT_PARAM + xref __CS0_UBR_INIT_PARAM + xref __CS0_CTL_INIT_PARAM + xref __CS1_LBR_INIT_PARAM + xref __CS1_UBR_INIT_PARAM + xref __CS1_CTL_INIT_PARAM + xref __CS2_LBR_INIT_PARAM + xref __CS2_UBR_INIT_PARAM + xref __CS2_CTL_INIT_PARAM + xref __CS3_LBR_INIT_PARAM + xref __CS3_UBR_INIT_PARAM + xref __CS3_CTL_INIT_PARAM + xref __CS0_BMC_INIT_PARAM + xref __CS1_BMC_INIT_PARAM + xref __CS2_BMC_INIT_PARAM + xref __CS3_BMC_INIT_PARAM + xref __FLASH_CTL_INIT_PARAM + xref __FLASH_ADDR_U_INIT_PARAM + xref __RAM_CTL_INIT_PARAM + xref __RAM_ADDR_U_INIT_PARAM + +;************************************************************************** +; Chip-specific initialization logic +;************************************************************************** + +; Minimum default initialization for eZ80F91 + + define .STARTUP, space = ROM + segment .STARTUP + .assume ADL = 1 + +_ez80_init: + ; Disable internal peripheral interrupt sources + + ld a, %ff + out0 (PB_DDR), a ; GPIO + out0 (PC_DDR), a + out0 (PD_DDR), a + + ld a, %00 + out0 (PB_ALT1), a + out0 (PC_ALT1), a + out0 (PD_ALT1), a + + out0 (PB_ALT2), a + out0 (PC_ALT2), a + out0 (PD_ALT2), a + + out0 (UART0_IER), a ; UARTs + out0 (UART1_IER), a + + out0 (I2C_CTL), a ; I2C + + out0 (FLASH_IRQ), a ; Flash + + ld a, %04 + out0 (SPI_CTL), a ; SPI + + in0 a, (RTC_CTRL) ; RTC, + and a, %be + out0 (RTC_CTRL), a + + ; Configure external memory/io + + ld a, __CS0_LBR_INIT_PARAM + out0 (CS0_LBR), a + ld a, __CS0_UBR_INIT_PARAM + out0 (CS0_UBR), a + ld a, __CS0_BMC_INIT_PARAM + out0 (CS0_BMC), a + ld a, __CS0_CTL_INIT_PARAM + out0 (CS0_CTL), a + + ld a, __CS1_LBR_INIT_PARAM + out0 (CS1_LBR), a + ld a, __CS1_UBR_INIT_PARAM + out0 (CS1_UBR), a + ld a, __CS1_BMC_INIT_PARAM + out0 (CS1_BMC), a + ld a, __CS1_CTL_INIT_PARAM + out0 (CS1_CTL), a + + ld a, __CS2_LBR_INIT_PARAM + out0 (CS2_LBR), a + ld a, __CS2_UBR_INIT_PARAM + out0 (CS2_UBR), a + ld a, __CS2_BMC_INIT_PARAM + out0 (CS2_BMC), a + ld a, __CS2_CTL_INIT_PARAM + out0 (CS2_CTL), a + + ld a, __CS3_LBR_INIT_PARAM + out0 (CS3_LBR), a + ld a, __CS3_UBR_INIT_PARAM + out0 (CS3_UBR), a + ld a, __CS3_BMC_INIT_PARAM + out0 (CS3_BMC), a + ld a, __CS3_CTL_INIT_PARAM + out0 (CS3_CTL), a + + ; Enable internal memory + + ld a, __FLASH_ADDR_U_INIT_PARAM + out0 (FLASH_ADDR_U), a + ld a, __FLASH_CTL_INIT_PARAM + out0 (FLASH_CTRL), a + + ld a, __RAM_ADDR_U_INIT_PARAM + out0 (RAM_ADDR_U), a + ld a, __RAM_CTL_INIT_PARAM + out0 (RAM_CTL), a + ret + +;***************************************************************************** +; eZ80F91 System Clock Initialization +;***************************************************************************** + +_ez80_initsysclk: + ret ; No PLL + end