added support for HSE and MSI clocks, and auto trim of MSI to LSE (needed for USB).

arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h

@@ -120,8 +120,8 @@
 
 /* Clock control register */
 
-#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Medium Speed clock enable */
+#define RCC_CR_MSION                (1 << 0)  /* Bit 0: Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Medium Speed clock ready flag */
+#define RCC_CR_MSIRDY               (1 << 1)  /* Bit 1: Internal Multi Speed clock ready flag */
 #define RCC_CR_MSIPLLEN             (1 << 2)  /* Bit 2: MSI clock PLL enable */
 #define RCC_CR_MSIRGSEL             (1 << 3)  /* Bit 2: MSI clock range selection */
 #define RCC_CR_MSIRANGE_SHIFT       (4)       /* Bits 7-4: MSI clock range */
@@ -161,9 +161,9 @@
 #define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
 #define RCC_CR_HSICAL_SHIFT         (16)      /* Bits 23-16: Internal High Speed clock Calibration */
 #define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
-#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Medium Speed clock trimming */
+#define RCC_CR_MSITRIM_SHIFT        (8)       /* Bits 15-8: Internal Multi Speed clock trimming */
 #define RCC_CR_MSITRIM_MASK         (0xff << RCC_CR_MSITRIM_SHIFT)
-#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Menium Speed clock Calibration */
+#define RCC_CR_MSICAL_SHIFT         (0)       /* Bits 7-0: Internal Multi Speed clock Calibration */
 #define RCC_CR_MSICAL_MASK          (0xff << RCC_CR_MSICAL_SHIFT)
 
 /* Clock configuration register */

arch/arm/src/stm32l4/stm32l4x6xx_rcc.c

@@ -57,9 +57,10 @@
 
 #define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
 
-/* Same for HSI */
+/* Same for HSI and MSI */
 
 #define HSIRDY_TIMEOUT HSERDY_TIMEOUT
+#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
 
 /* HSE divisor to yield ~1MHz RTC clock */
 
@@ -578,14 +579,38 @@ static void stm32l4_stdclockconfig(void)
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
 
-#  error STM32L4_BOARD_USEMSI not yet implemented in arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+  /* Wait until the MSI is either off or ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
   /* setting MSIRANGE */
-  /* setting MSIPLLEN */
 
   regval  = getreg32(STM32L4_RCC_CR);
-  regval |= RCC_CR_MSION;           /* Enable MSI */
+  regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION);    /* Enable MSI and frequ */
   putreg32(regval, STM32L4_RCC_CR);
 
+  /* Wait until the MSI is ready (or until a timeout elapsed) */
+
+  for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      /* Check if the MSIRDY flag is the set in the CR */
+
+      if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
+        {
+          /* If so, then break-out with timeout > 0 */
+
+          break;
+        }
+    }
+
 #elif defined(STM32L4_BOARD_USEHSE)
   /* Enable External High-Speed Clock (HSE) */
 
@@ -696,6 +721,8 @@ static void stm32l4_stdclockconfig(void)
 
 #ifdef STM32L4_BOARD_USEHSI
       regval |= RCC_PLLCFG_PLLSRC_HSI;
+#elif defined(STM32L4_BOARD_USEMSI)
+      regval |= RCC_PLLCFG_PLLSRC_MSI;
 #else /* if STM32L4_BOARD_USEHSE */
       regval |= RCC_PLLCFG_PLLSRC_HSE;
 #endif
@@ -833,6 +860,14 @@ static void stm32l4_stdclockconfig(void)
        */
 
       stm32l4_rcc_enablelse();
+
+#  if defined(STM32L4_BOARD_USEMSI)
+      /* now that LSE is up, auto trim the MSI */
+
+      regval  = getreg32(STM32L4_RCC_CR);
+      regval |= RCC_CR_MSIPLLEN;
+      putreg32(regval, STM32L4_RCC_CR);
+#  endif
 #endif
 
 #if defined(STM32L4_USE_CLK48)

configs/nucleo-l476rg/include/nucleo-l476rg.h

@@ -49,8 +49,19 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
+#if 1
+#define HSI_CLOCK_CONFIG            /* HSI-16 clock configuration */
+#elif 0
+/* make sure you installed one! */
+#define HSE_CLOCK_CONFIG            /* HSE with 8 MHz xtal */
+#else
+#define MSI_CLOCK_CONFIG            /* MSI @ 4 MHz autotrimmed via LSE */
+#endif
+
 /* Clocking *************************************************************************/
 
+#if defined(HSI_CLOCK_CONFIG)
+
 /* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3).  However, as
  * shipped, the X3 crystal is not populated.  Therefore the Nucleo-L476RG
  * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
@@ -88,6 +99,10 @@
 
 #define STM32L4_BOARD_USEHSI      1
 
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hsi */
+
 /* REVISIT: Trimming of the HSI and MSI is not yet supported. */
 
 /* Main PLL Configuration.
@@ -245,7 +260,7 @@
 
 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
-//#define STM32L4_USE_LSE           1
+#define STM32L4_USE_LSE           1
 
 /* AHB clock (HCLK) is SYSCLK (80MHz) */
 
@@ -287,6 +302,167 @@
 
 /* TODO SDMMC */
 
+#elif defined(HSE_CLOCK_CONFIG)
+
+/* use the HSE */
+
+#define STM32L4_BOARD_USEHSE      1
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hse */
+
+/* prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(20)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#elif defined(MSI_CLOCK_CONFIG)
+
+/* use the MSI; frequ = 4 MHz; autotrim from LSE */
+
+#define STM32L4_BOARD_USEMSI      1
+#define STM32L4_BOARD_MSIRANGE    RCC_CR_MSIRANGE_4M
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = msi */
+
+/* prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(40)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(24)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#endif
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/

configs/nucleo-l476rg/nsh/defconfig

@@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
 #
 # Build Configuration
 #
-CONFIG_APPS_DIR="../apps"
+# CONFIG_APPS_DIR="../apps"
 CONFIG_BUILD_FLAT=y
 # CONFIG_BUILD_2PASS is not set
 
@@ -49,7 +49,6 @@ CONFIG_DEBUG_VERBOSE=y
 #
 # Subsystem Debug Options
 #
-CONFIG_DEBUG_AUDIO=y
 CONFIG_DEBUG_BINFMT=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_GRAPHICS=y
@@ -60,6 +59,7 @@ CONFIG_DEBUG_LIB=y
 #
 # OS Function Debug Options
 #
+# CONFIG_DEBUG_DMA is not set
 # CONFIG_DEBUG_HEAP is not set
 # CONFIG_DEBUG_IRQ is not set
 
@@ -101,7 +101,8 @@ CONFIG_ARCH="arm"
 # CONFIG_ARCH_CHIP_CALYPSO is not set
 # CONFIG_ARCH_CHIP_DM320 is not set
 # CONFIG_ARCH_CHIP_EFM32 is not set
-# CONFIG_ARCH_CHIP_IMX is not set
+# CONFIG_ARCH_CHIP_IMX1 is not set
+# CONFIG_ARCH_CHIP_IMX6 is not set
 # CONFIG_ARCH_CHIP_KINETIS is not set
 # CONFIG_ARCH_CHIP_KL is not set
 # CONFIG_ARCH_CHIP_LM is not set
@@ -133,6 +134,7 @@ CONFIG_ARCH_CORTEXM4=y
 # CONFIG_ARCH_CORTEXM7 is not set
 # CONFIG_ARCH_CORTEXA5 is not set
 # CONFIG_ARCH_CORTEXA8 is not set
+# CONFIG_ARCH_CORTEXA9 is not set
 # CONFIG_ARCH_CORTEXR4 is not set
 # CONFIG_ARCH_CORTEXR4F is not set
 # CONFIG_ARCH_CORTEXR5 is not set
@@ -141,6 +143,7 @@ CONFIG_ARCH_CORTEXM4=y
 # CONFIG_ARCH_CORTEXR7F is not set
 CONFIG_ARCH_FAMILY="armv7-m"
 CONFIG_ARCH_CHIP="stm32l4"
+# CONFIG_ARM_TOOLCHAIN_IAR is not set
 CONFIG_ARM_TOOLCHAIN_GNU=y
 # CONFIG_ARMV7M_USEBASEPRI is not set
 CONFIG_ARCH_HAVE_CMNVECTOR=y
@@ -149,6 +152,7 @@ CONFIG_ARMV7M_CMNVECTOR=y
 CONFIG_ARCH_HAVE_FPU=y
 CONFIG_ARCH_HAVE_DPFPU=y
 # CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_HAVE_TRUSTZONE is not set
 CONFIG_ARM_HAVE_MPU_UNIFIED=y
 # CONFIG_ARM_MPU is not set
 # CONFIG_DEBUG_HARDFAULT is not set
@@ -162,6 +166,7 @@ CONFIG_ARMV7M_HAVE_ITCM=y
 CONFIG_ARMV7M_HAVE_DTCM=y
 # CONFIG_ARMV7M_ITCM is not set
 # CONFIG_ARMV7M_DTCM is not set
+# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set
 # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
 # CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
@@ -171,6 +176,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
 # CONFIG_ARMV7M_ITMSYSLOG is not set
 # CONFIG_SERIAL_TERMIOS is not set
 # CONFIG_USART2_RS485 is not set
+# CONFIG_USART2_RXDMA is not set
 # CONFIG_SERIAL_DISABLE_REORDERING is not set
 
 #
@@ -185,6 +191,12 @@ CONFIG_STM32L4_STM32L476XX=y
 # CONFIG_STM32L4_FLASH_512KB is not set
 CONFIG_STM32L4_FLASH_1024KB=y
 
+#
+# SRAM2 Options
+#
+CONFIG_STM32L4_SRAM2_HEAP=y
+CONFIG_STM32L4_SRAM2_INIT=y
+
 #
 # STM32L4 Peripheral Support
 #
@@ -192,7 +204,7 @@ CONFIG_STM32L4_FLASH_1024KB=y
 # CONFIG_STM32L4_ADC is not set
 # CONFIG_STM32L4_CAN is not set
 # CONFIG_STM32L4_DAC is not set
-# CONFIG_STM32L4_DMA is not set
+CONFIG_STM32L4_DMA=y
 # CONFIG_STM32L4_I2C is not set
 # CONFIG_STM32L4_SAI is not set
 # CONFIG_STM32L4_SPI is not set
@@ -202,8 +214,8 @@ CONFIG_STM32L4_USART=y
 #
 # AHB1 Peripherals
 #
-# CONFIG_STM32L4_DMA1 is not set
+CONFIG_STM32L4_DMA1=y
-# CONFIG_STM32L4_DMA2 is not set
+CONFIG_STM32L4_DMA2=y
 # CONFIG_STM32L4_CRC is not set
 # CONFIG_STM32L4_TSC is not set
 
@@ -215,17 +227,18 @@ CONFIG_STM32L4_USART=y
 # CONFIG_STM32L4_ADC2 is not set
 # CONFIG_STM32L4_ADC3 is not set
 # CONFIG_STM32L4_AES is not set
-# CONFIG_STM32L4_RNG is not set
+CONFIG_STM32L4_RNG=y
 
 #
 # AHB3 Peripherals
 #
 # CONFIG_STM32L4_FMC is not set
-# CONFIG_STM32L4_QUADSPI is not set
+# CONFIG_STM32L4_QSPI is not set
 
 #
 # APB1 Peripherals
 #
+CONFIG_STM32L4_PWR=y
 # CONFIG_STM32L4_TIM2 is not set
 # CONFIG_STM32L4_TIM3 is not set
 # CONFIG_STM32L4_TIM4 is not set
@@ -276,8 +289,8 @@ CONFIG_STM32L4_FIREWALL=y
 # CONFIG_STM32L4_WWDG is not set
 CONFIG_STM32L4_FLASH_PREFETCH=y
 CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-# CONFIG_STM32L4_CUSTOM_CLOCKCONFIG is not set
+# CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is not set
-# CONFIG_STM32L4_SAI1PLL is not set
+CONFIG_STM32L4_SAI1PLL=y
 # CONFIG_STM32L4_SAI2PLL is not set
 
 #
@@ -290,12 +303,13 @@ CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
 #
 # CONFIG_ARCH_NOINTC is not set
 # CONFIG_ARCH_VECNOTIRQ is not set
-# CONFIG_ARCH_DMA is not set
+CONFIG_ARCH_DMA=y
 CONFIG_ARCH_HAVE_IRQPRIO=y
 # CONFIG_ARCH_L2CACHE is not set
 # CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
 # CONFIG_ARCH_HAVE_ADDRENV is not set
 # CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
 CONFIG_ARCH_HAVE_VFORK=y
 # CONFIG_ARCH_HAVE_MMU is not set
 CONFIG_ARCH_HAVE_MPU=y
@@ -346,6 +360,7 @@ CONFIG_RAM_SIZE=98304
 # Board Selection
 #
 CONFIG_ARCH_BOARD_NUCLEO_L476RG=y
+# CONFIG_ARCH_BOARD_STM32L476VG_DISCO is not set
 # CONFIG_ARCH_BOARD_CUSTOM is not set
 CONFIG_ARCH_BOARD="nucleo-l476rg"
 
@@ -472,6 +487,8 @@ CONFIG_PTHREAD_STACK_DEFAULT=2048
 CONFIG_DISABLE_POLL=y
 CONFIG_DEV_NULL=y
 # CONFIG_DEV_ZERO is not set
+CONFIG_ARCH_HAVE_RNG=y
+CONFIG_DEV_RANDOM=y
 # CONFIG_DEV_LOOP is not set
 
 #
@@ -514,6 +531,7 @@ CONFIG_SPI_EXCHANGE=y
 # LED Support
 #
 # CONFIG_USERLED is not set
+# CONFIG_RGBLED is not set
 # CONFIG_PCA9635PW is not set
 # CONFIG_MMCSD is not set
 # CONFIG_MODEM is not set
@@ -579,7 +597,7 @@ CONFIG_USART2_2STOP=0
 # CONFIG_USART2_DMA is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
-# CONFIG_WIRELESS is not set
+# CONFIG_DRIVERS_WIRELESS is not set
 
 #
 # System Logging Device Options
@@ -642,7 +660,7 @@ CONFIG_FS_MQUEUE_MPATH="/var/mqueue"
 # Memory Management
 #
 # CONFIG_MM_SMALL is not set
-CONFIG_MM_REGIONS=1
+CONFIG_MM_REGIONS=2
 # CONFIG_ARCH_HAVE_HEAP2 is not set
 # CONFIG_GRAN is not set
 
@@ -651,6 +669,10 @@ CONFIG_MM_REGIONS=1
 #
 # CONFIG_AUDIO is not set
 
+#
+# Wireless Support
+#
+
 #
 # Binary Loader
 #
@@ -694,6 +716,8 @@ CONFIG_ARCH_LOWPUTC=y
 CONFIG_LIB_SENDFILE_BUFSIZE=512
 # CONFIG_ARCH_ROMGETC is not set
 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
+CONFIG_ARCH_HAVE_TLS=y
+# CONFIG_TLS is not set
 # CONFIG_LIBC_NETDB is not set
 
 #
@@ -731,6 +755,7 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024
 #
 # Examples
 #
+# CONFIG_EXAMPLES_CHAT is not set
 # CONFIG_EXAMPLES_CONFIGDATA is not set
 # CONFIG_EXAMPLES_CPUHOG is not set
 # CONFIG_EXAMPLES_CXXTEST is not set
@@ -770,7 +795,10 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # CONFIG_EXAMPLES_PIPE is not set
 # CONFIG_EXAMPLES_PPPD is not set
 # CONFIG_EXAMPLES_POSIXSPAWN is not set
-# CONFIG_EXAMPLES_QENCODER is not set
+CONFIG_EXAMPLES_RANDOM=y
+CONFIG_EXAMPLES_MAXSAMPLES=64
+CONFIG_EXAMPLES_NSAMPLES=8
+# CONFIG_EXAMPLES_RGBLED is not set
 # CONFIG_EXAMPLES_RGMP is not set
 # CONFIG_EXAMPLES_SENDMAIL is not set
 # CONFIG_EXAMPLES_SERIALBLASTER is not set
@@ -779,18 +807,24 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # CONFIG_EXAMPLES_SLCD is not set
 # CONFIG_EXAMPLES_SMART_TEST is not set
 # CONFIG_EXAMPLES_SMART is not set
+# CONFIG_EXAMPLES_SMP is not set
 # CONFIG_EXAMPLES_TCPECHO is not set
 # CONFIG_EXAMPLES_TELNETD is not set
 # CONFIG_EXAMPLES_TIFF is not set
 # CONFIG_EXAMPLES_TOUCHSCREEN is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
-# CONFIG_EXAMPLES_USBSERIAL is not set
 # CONFIG_EXAMPLES_USBTERM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
 
 #
 # File System Utilities
 #
+# CONFIG_FSUTILS_INIFILE is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
 
 #
 # Graphics Support
@@ -822,6 +856,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
 # NSH Library
 #
 CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
 
 #
 # Command Line Configuration
@@ -846,7 +881,7 @@ CONFIG_NSH_BUILTIN_APPS=y
 # CONFIG_NSH_DISABLE_CD is not set
 # CONFIG_NSH_DISABLE_CP is not set
 # CONFIG_NSH_DISABLE_CMP is not set
-CONFIG_NSH_DISABLE_DATE=y
+# CONFIG_NSH_DISABLE_DATE is not set
 # CONFIG_NSH_DISABLE_DD is not set
 # CONFIG_NSH_DISABLE_DF is not set
 # CONFIG_NSH_DISABLE_DELROUTE is not set
@@ -910,6 +945,8 @@ CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_CONSOLE=y
 # CONFIG_NSH_ALTCONDEV is not set
 # CONFIG_NSH_ARCHINIT is not set
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
 
 #
 # NxWidgets/NxWM
@@ -928,7 +965,6 @@ CONFIG_NSH_CONSOLE=y
 # CONFIG_SYSTEM_CUTERM is not set
 # CONFIG_SYSTEM_INSTALL is not set
 # CONFIG_SYSTEM_HEX2BIN is not set
-# CONFIG_SYSTEM_INIFILE is not set
 # CONFIG_SYSTEM_HEXED is not set
 # CONFIG_SYSTEM_RAMTEST is not set
 CONFIG_READLINE_HAVE_EXTMATCH=y
@@ -936,7 +972,8 @@ CONFIG_SYSTEM_READLINE=y
 CONFIG_READLINE_ECHO=y
 # CONFIG_READLINE_TABCOMPLETION is not set
 # CONFIG_READLINE_CMD_HISTORY is not set
-# CONFIG_SYSTEM_RAMTRON is not set
 # CONFIG_SYSTEM_SUDOKU is not set
 # CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
 # CONFIG_SYSTEM_ZMODEM is not set
+# CONFIG_SYSTEM_DISCOTEST is not set

configs/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h

@@ -51,9 +51,9 @@
 
 /* Clocking *************************************************************************/
 
-/* The stm32l476vg-disco supports both HSE and LSE crystals (X2 and X3).  However, as
+/* The stm32l476vg-disco supports both HSE and LSE crystals.  As shipped, the HSE
- * shipped, the HSE X2 crystal is not populated.  Therefore the stm32l476vg-disco
+   crystal is not populated.  Therefore the stm32l476vg-disco will need to run off the
- * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
+   16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
  */
 
 /* HSI - 16 MHz RC factory-trimmed
@@ -69,15 +69,23 @@
 
 #define BOARD_AHB_FREQUENCY       80000000ul
 
-/* XXX review the STM32L4_BOARD_USEHSI usage, it has too much influence in
+/* XXX there needs to be independent selections for the System Clock Mux and
- * stm32l4x6xx_rcc.c.  I suspect it is fine for it to turn on and off that
+   the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
- * ocillator, but really that's all it should do (e.g. it also controls
+   Source Mux is chosen by the following define.  This is probably OK in many
- * input of teh PLLs.  Also, it should be fine/desireable to support things
+   cases, but should be separated to support other power configurations.
- * like turning on both HSI and MSI, because they plausibly can both be
- * used at the same time; currently those choices HSE/HSI16/MSI are
- * mutually exclusive.
  */
 
+#if 0
+#define HSI_CLOCK_CONFIG            /* HSI-16 clock configuration */
+#elif 0
+/* make sure you actually installed one! */
+#define HSE_CLOCK_CONFIG            /* HSE with 8 MHz xtal */
+#else
+#define MSI_CLOCK_CONFIG            /* MSI @ 4 MHz autotrimmed via LSE */
+#endif
+
+#if defined(HSI_CLOCK_CONFIG)
+
 #define STM32L4_BOARD_USEHSI      1
 
 /* prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
@@ -178,6 +186,167 @@
  */
 /* REVISIT : this can be configured */
 
+#elif defined(HSE_CLOCK_CONFIG)
+
+/* use the HSE */
+
+#define STM32L4_BOARD_USEHSE      1
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = hse */
+
+/* prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(20)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#elif defined(MSI_CLOCK_CONFIG)
+
+/* use the MSI; frequ = 4 MHz; autotrim from LSE */
+
+#define STM32L4_BOARD_USEMSI      1
+#define STM32L4_BOARD_MSIRANGE    RCC_CR_MSIRANGE_4M
+
+/* XXX sysclk mux = pllclk */
+
+/* XXX pll source mux = msi */
+
+/* prescaler common to all PLL inputs */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(40)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             0
+#undef STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(24)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* enable CLK48; get it from PLLSAI1 */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* enable LSE (for the RTC) */
+
+#define STM32L4_USE_LSE           1
+
+/* configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+
+/* configure the APB1 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* configure the APB2 prescaler */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+#endif
+
 /************************************************************************************
  * Public Data
  ************************************************************************************/