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drivers/net/enc28j60.c: Replace non ascii character (0xB5, "micro")

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YAMAMOTO Takashi 2020-12-02 06:28:22 +09:00 committed by Xiang Xiao
parent 78caedd485
commit 3086ceb28a
1 changed files with 5 additions and 5 deletions
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10
drivers/net/enc28j60.c
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@ -567,7 +567,7 @@ static inline void enc_src(FAR struct enc_driver_s *priv)
* workaround this condition. * workaround this condition.
* *
* Also, "After a System Reset, all PHY registers should not be read or * Also, "After a System Reset, all PHY registers should not be read or
* written to until at least 50 µs have passed since the Reset has ended. * written to until at least 50 us have passed since the Reset has ended.
* All registers will revert to their Reset default values. The dual * All registers will revert to their Reset default values. The dual
* port buffer memory will maintain state throughout the System Reset." * port buffer memory will maintain state throughout the System Reset."
*/ */
@ -1000,7 +1000,7 @@ static uint16_t enc_rdphy(FAR struct enc_driver_s *priv, uint8_t phyaddr)
enc_wrbreg(priv, ENC_MICMD, MICMD_MIIRD); enc_wrbreg(priv, ENC_MICMD, MICMD_MIIRD);
/* 3. Wait 10.24 µs. Poll the MISTAT.BUSY bit to be certain that the /* 3. Wait 10.24 us. Poll the MISTAT.BUSY bit to be certain that the
* operation is complete. While busy, the host controller should not * operation is complete. While busy, the host controller should not
* start any MIISCAN operations or write to the MIWRH register. * start any MIISCAN operations or write to the MIWRH register.
* *
@ -1068,7 +1068,7 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
enc_wrbreg(priv, ENC_MIWRH, phydata >> 8); enc_wrbreg(priv, ENC_MIWRH, phydata >> 8);
/* The PHY register will be written after the MIIM operation completes, /* The PHY register will be written after the MIIM operation completes,
* which takes 10.24 µs. When the write operation has completed, BUSY * which takes 10.24 us. When the write operation has completed, BUSY
* bit will clear itself. * bit will clear itself.
* *
* The host controller should not start any MIISCAN or MIIRD operations * The host controller should not start any MIISCAN or MIIRD operations
@ -2387,7 +2387,7 @@ static void enc_pwrsave(FAR struct enc_driver_s *priv)
* a slightly modified procedure: * a slightly modified procedure:
* *
* 1. Wake-up by clearing ECON2.PWRSV. * 1. Wake-up by clearing ECON2.PWRSV.
* 2. Wait at least 300 ìs for the PHY to stabilize. To accomplish the * 2. Wait at least 300 us for the PHY to stabilize. To accomplish the
* delay, the host controller may poll ESTAT.CLKRDY and wait for it * delay, the host controller may poll ESTAT.CLKRDY and wait for it
* to become set. * to become set.
* 3. Restore receive capability by setting ECON1.RXEN. * 3. Restore receive capability by setting ECON1.RXEN.
@ -2418,7 +2418,7 @@ static void enc_pwrfull(FAR struct enc_driver_s *priv)
enc_bfcgreg(priv, ENC_ECON2, ECON2_PWRSV); enc_bfcgreg(priv, ENC_ECON2, ECON2_PWRSV);
/* 2. Wait at least 300 ìs for the PHY to stabilize. To accomplish the /* 2. Wait at least 300 us for the PHY to stabilize. To accomplish the
* delay, the host controller may poll ESTAT.CLKRDY and wait for it to * delay, the host controller may poll ESTAT.CLKRDY and wait for it to
* become set. * become set.
*/ */